From nobody Fri Sep 20 07:44:00 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B85BC4167B for ; Mon, 4 Dec 2023 08:43:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343600AbjLDImv (ORCPT ); Mon, 4 Dec 2023 03:42:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51640 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235037AbjLDImk (ORCPT ); Mon, 4 Dec 2023 03:42:40 -0500 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A67D1103 for ; Mon, 4 Dec 2023 00:42:34 -0800 (PST) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1d04d286bc0so13335845ad.3 for ; Mon, 04 Dec 2023 00:42:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1701679354; x=1702284154; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EtxwJB+gyX+Kun83a1WzYlUProLM+PYOcLnPqWgIwQU=; b=PbTb/3oVWSOTP/oG6eBJQaepq/5/XryBN4mk7LLiMJvmcuC52VD53f0PUM5IkLP/2a HDHHPq22apRNyZu6xuYXwenqnL38xrP9JZJSD0sKebu/Ld1r8CCv5e0/Fs/Sac5OwMbL S4ZhYd0q4QxhFwmBmG7LnoNiB+pMEEn9Q31R0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701679354; x=1702284154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EtxwJB+gyX+Kun83a1WzYlUProLM+PYOcLnPqWgIwQU=; b=Jt98NJwP0Y7FZx4g+VIQRjXuW8v9KJcKt+SA9wANK+7yhTdFFNxRcx0ZRhLXLnYdd5 EkK/1PDmb3UER18CEa9xsMEnXx0Tiy+mABi4Oq2M1vznlJ8/TclNuLT0P9pj54WXC6o7 2LxL3yU3zB71P2owv065vlpfA2M4sWXMgQ9KED3Yab0+HMsmE+M7b7ZmgA8CffFcQZmM 7hz0tA4iXvuMOzeVwbl4rXEfRwt6nyuIVCLINE9MS7euAR0q1Vp4P4YTLJC/j5uZJnVV p7J8bC2v1/rs9HeF9Ibx1JTHHq1KZukuHCzvxc2rQ9vIW6B+cbee1Kuu6ssc6Y+urcaz dsYA== X-Gm-Message-State: AOJu0Yy6X4r5OcytPui82xKeAfl3OvYz12ZlU57WV2O+p3C2UJiuwuEq 7szUolSjKWgVjauv5VxeNshUuA== X-Google-Smtp-Source: AGHT+IHjs1efUxU8PIZC7bPuZUL+egD8AeqZnRrzoov/LNuIduoaGApfdvfjcTYnSLtTvg3DMHMgLQ== X-Received: by 2002:a17:902:ed4d:b0:1d0:6d41:e99 with SMTP id y13-20020a170902ed4d00b001d06d410e99mr1403323plb.46.1701679353640; Mon, 04 Dec 2023 00:42:33 -0800 (PST) Received: from wenstp920.tpe.corp.google.com ([2401:fa00:1:10:6084:72e2:9ac2:f115]) by smtp.gmail.com with ESMTPSA id p14-20020a1709028a8e00b001cfc3f73927sm7871795plo.9.2023.12.04.00.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 00:42:33 -0800 (PST) From: Chen-Yu Tsai To: Matthias Brugger , AngeloGioacchino Del Regno Cc: Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v3 6/9] arm64: dts: mediatek: Add MT8186 Krabby platform based Tentacruel / Tentacool Date: Mon, 4 Dec 2023 16:40:08 +0800 Message-ID: <20231204084012.2281292-7-wenst@chromium.org> X-Mailer: git-send-email 2.43.0.rc2.451.g8631bc7472-goog In-Reply-To: <20231204084012.2281292-1-wenst@chromium.org> References: <20231204084012.2281292-1-wenst@chromium.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Tentacruel and Tentacool are MT8186 based Chromebooks based on the Krabby design. Tentacruel, also known as the ASUS Chromebook CM14 Flip CM1402F, is a convertible device with touchscreen and stylus. Tentacool, also known as the ASUS Chromebook CM14 CM1402C, is a laptop device. It does not have a touchscreen or stylus. The two devices both have two variants. The difference is a second source touchpad controller that shares the same address as the original, but is incompatible. The extra SKU IDs for the Tentacruel devices map to different sensor components attached to the Embedded Controller. These are not visible to the main processor. Signed-off-by: Chen-Yu Tsai Acked-by: Conor Dooley --- Changes since v2: - Picked up Conor's ack - Rename touchpad to trackpad - Drop pinctrl properties from trackpad in tentacruel/tentacool second source trackpad Changes since v1: - Reorder SKU numbers in descending order. - Fixed pinconfig node names - Moved pinctrl-* properties after interrupts-* - Switched to interrupts-extended for external components - Marked ADSP as explicitly disabled, with a comment explaining that it stalls the system - Renamed "touchpad" to "trackpad" - Dropped bogus "no-laneswap" property from it6505 node - Moved "realtek,jd-src" property to after all the regulator supplies - Switched to macros for MT6366 regulator "regulator-allowed-modes" - Renamed "vgpu" regulator name to allow coupling, with a comment containing the name used in the design - Renamed "cr50" node name to "tpm" - Moved trackpad_pins reference up to i2c2; workaround for second source component resource sharing. - Fix copyright year - Fixed touchscreen supply name arch/arm64/boot/dts/mediatek/Makefile | 4 + .../dts/mediatek/mt8186-corsola-krabby.dtsi | 129 ++ .../mt8186-corsola-tentacool-sku327681.dts | 57 + .../mt8186-corsola-tentacool-sku327683.dts | 24 + .../mt8186-corsola-tentacruel-sku262144.dts | 44 + .../mt8186-corsola-tentacruel-sku262148.dts | 26 + .../boot/dts/mediatek/mt8186-corsola.dtsi | 1719 +++++++++++++++++ 7 files changed, 2003 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-s= ku327681.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-s= ku327683.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-= sku262144.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-= sku262148.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index e6e7592a3645..442af61b1305 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -43,6 +43,10 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-kodama-sku= 32.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8183-pumpkin.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-tentacool-sku327681.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-tentacool-sku327683.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-tentacruel-sku262144.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-corsola-tentacruel-sku262148.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8192-asurada-hayato-r5-sku2.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi b/arch= /arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi new file mode 100644 index 000000000000..9b2b64525961 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-krabby.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola.dtsi" +#include + +/ { + aliases { + i2c4 =3D &i2c4; + }; +}; + +&dsi_out { + remote-endpoint =3D <&ps8640_in>; +}; + +&i2c0 { + clock-frequency =3D <400000>; + + ps8640: edp-bridge@8 { + compatible =3D "parade,ps8640"; + reg =3D <0x8>; + powerdown-gpios =3D <&pio 96 GPIO_ACTIVE_LOW>; + reset-gpios =3D <&pio 98 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ps8640_pins>; + vdd12-supply =3D <&mt6366_vrf12_reg>; + vdd33-supply =3D <&mt6366_vcn33_reg>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + ps8640_in: endpoint { + remote-endpoint =3D <&dsi_out>; + }; + }; + + port@1 { + reg =3D <1>; + + ps8640_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + + aux-bus { + panel { + compatible =3D "edp-panel"; + power-supply =3D <&pp3300_disp_x>; + backlight =3D <&backlight_lcd0>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&ps8640_out>; + }; + }; + }; + }; + }; +}; + +&i2c1 { + i2c-scl-internal-delay-ns =3D <10000>; + + touchscreen: touchscreen@10 { + compatible =3D "hid-over-i2c"; + reg =3D <0x10>; + interrupts-extended =3D <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&touchscreen_pins>; + post-power-on-delay-ms =3D <10>; + hid-descr-addr =3D <0x0001>; + vdd-supply =3D <&pp3300_s3>; + }; +}; + +&i2c4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c4_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; + + proximity@28 { + compatible =3D "semtech,sx9324"; + reg =3D <0x28>; + interrupts-extended =3D <&pio 5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sar_sensor_pins>; + vdd-supply =3D <&mt6366_vio18_reg>; + svdd-supply =3D <&mt6366_vio18_reg>; + #io-channel-cells =3D <1>; + }; +}; + +&pio { + i2c4_pins: i2c4-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <4>; + input-enable; + }; + }; + + ps8640_pins: ps8640-pins { + pins-pwrdn-rst { + pinmux =3D , + ; + output-low; + }; + }; + + sar_sensor_pins: sar-sensor-pins { + pins-irq { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku32768= 1.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327681.dts new file mode 100644 index 000000000000..9bb64353ca65 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327681.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-krabby.dtsi" + +/ { + model =3D "Google Tentacool board"; + compatible =3D "google,tentacruel-sku327681", "google,tentacruel", "media= tek,mt8186"; + chassis-type =3D "laptop"; +}; + +/* Tentacool omits the pen. */ +&gpio_keys { + status =3D "disabled"; +}; + +/* Tentacool omits the touchscreen; nothing else is on i2c1. */ +&i2c1 { + status =3D "disabled"; +}; + +&keyboard_controller { + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap =3D < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +/* Tentacool omits the touchscreen. */ +&touchscreen { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku32768= 3.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327683.dts new file mode 100644 index 000000000000..c3ae6f9616c8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacool-sku327683.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +#include "mt8186-corsola-tentacool-sku327681.dts" + +/ { + compatible =3D "google,tentacruel-sku327683", "google,tentacruel", "media= tek,mt8186"; +}; + +/* This variant replaces only the trackpad controller. */ +&i2c2 { + /delete-node/ trackpad@15; + + trackpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + interrupts-extended =3D <&pio 11 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr =3D <0x0001>; + vdd-supply =3D <&pp3300_s3>; + wakeup-source; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku2621= 44.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.d= ts new file mode 100644 index 000000000000..26d3451a5e47 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262144.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-krabby.dtsi" + +/ { + model =3D "Google Tentacruel board"; + compatible =3D "google,tentacruel-sku262147", "google,tentacruel-sku26214= 6", + "google,tentacruel-sku262145", "google,tentacruel-sku262144", + "google,tentacruel", "mediatek,mt8186"; + chassis-type =3D "convertible"; +}; + +&keyboard_controller { + function-row-physmap =3D < + MATRIX_KEY(0x00, 0x02, 0) /* T1 */ + MATRIX_KEY(0x03, 0x02, 0) /* T2 */ + MATRIX_KEY(0x02, 0x02, 0) /* T3 */ + MATRIX_KEY(0x01, 0x02, 0) /* T4 */ + MATRIX_KEY(0x03, 0x04, 0) /* T5 */ + MATRIX_KEY(0x02, 0x04, 0) /* T6 */ + MATRIX_KEY(0x01, 0x04, 0) /* T7 */ + MATRIX_KEY(0x02, 0x09, 0) /* T8 */ + MATRIX_KEY(0x01, 0x09, 0) /* T9 */ + MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + >; + + linux,keymap =3D < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku2621= 48.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262148.d= ts new file mode 100644 index 000000000000..447b57b12b41 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-tentacruel-sku262148.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2023 Google LLC + */ + +#include "mt8186-corsola-tentacruel-sku262144.dts" + +/ { + compatible =3D "google,tentacruel-sku262151", "google,tentacruel-sku26215= 0", + "google,tentacruel-sku262149", "google,tentacruel-sku262148", + "google,tentacruel", "mediatek,mt8186"; +}; + +/* This variant replaces only the trackpad controller. */ +&i2c2 { + /delete-node/ trackpad@15; + + trackpad@15 { + compatible =3D "hid-over-i2c"; + reg =3D <0x15>; + interrupts-extended =3D <&pio 11 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr =3D <0x0001>; + vdd-supply =3D <&pp3300_s3>; + wakeup-source; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/= boot/dts/mediatek/mt8186-corsola.dtsi new file mode 100644 index 000000000000..8726b2916ef1 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi @@ -0,0 +1,1719 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8186.dtsi" +#include +#include +#include +#include +#include + +/ { + aliases { + i2c0 =3D &i2c0; + i2c1 =3D &i2c1; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c5 =3D &i2c5; + mmc0 =3D &mmc0; + mmc1 =3D &mmc1; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@40000000 { + device_type =3D "memory"; + /* The size should be filled in by the bootloader. */ + reg =3D <0 0x40000000 0 0>; + }; + + backlight_lcd0: backlight-lcd0 { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm0 0 500000>; + power-supply =3D <&ppvar_sys>; + enable-gpios =3D <&pio 152 0>; + brightness-levels =3D <0 1023>; + num-interpolated-steps =3D <1023>; + default-brightness-level =3D <576>; + }; + + btsco: bt-sco { + compatible =3D "linux,bt-sco"; + #sound-dai-cells =3D <0>; + }; + + dmic_codec: dmic-codec { + compatible =3D "dmic-codec"; + num-channels =3D <2>; + wakeup-delay-ms =3D <50>; + #sound-dai-cells =3D <0>; + }; + + gpio_keys: gpio-keys { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pen_eject>; + + pen_insert: pen-insert-switch { + label =3D "Pen Insert"; + /* Insert =3D low, eject =3D high */ + gpios =3D <&pio 18 GPIO_ACTIVE_LOW>; + linux,code =3D ; + linux,input-type =3D ; + wakeup-event-action =3D ; + wakeup-source; + }; + }; + + pp1800_dpbrdg_dx: regulator-pp1800-dpbrdg-dx { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&en_pp1800_dpbrdg>; + regulator-name =3D "pp1800_dpbrdg_dx"; + enable-active-high; + gpio =3D <&pio 39 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&mt6366_vio18_reg>; + }; + + pp3300_disp_x: regulator-pp3300-disp-x { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_disp_x"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&edp_panel_fixed_pins>; + enable-active-high; + regulator-boot-on; + gpio =3D <&pio 153 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp3300_z2>; + }; + + /* system wide LDO 3.3V power rail */ + pp3300_z5: regulator-pp3300-ldo-z5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_ldo_z5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* separately switched 3.3V power rail */ + pp3300_s3: regulator-pp3300-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_s3"; + /* automatically sequenced by PMIC EXT_PMIC_EN2 */ + regulator-always-on; + regulator-boot-on; + vin-supply =3D <&pp3300_z2>; + }; + + /* system wide 3.3V power rail */ + pp3300_z2: regulator-pp3300-z2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp3300_z2"; + /* EN pin tied to pp4200_z2, which is controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide 4.2V power rail */ + pp4200_z2: regulator-pp4200-z2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp4200_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <4200000>; + regulator-max-microvolt =3D <4200000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide switching 5.0V power rail */ + pp5000_z2: regulator-pp5000-z2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pp5000_z2"; + /* controlled by EC */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&ppvar_sys>; + }; + + /* system wide semi-regulated power rail from battery or USB */ + ppvar_sys: regulator-ppvar-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + adsp_dma_mem: memory@61000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x61000000 0 0x100000>; + no-map; + }; + + adsp_mem: memory@60000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60000000 0 0xA00000>; + no-map; + }; + + scp_mem: memory@50000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x50000000 0 0x10a0000>; + no-map; + }; + }; + + sound: sound { + compatible =3D "mediatek,mt8186-mt6366-rt1019-rt5682s-sound"; + pinctrl-names =3D "aud_clk_mosi_off", + "aud_clk_mosi_on", + "aud_clk_miso_off", + "aud_clk_miso_on", + "aud_dat_miso_off", + "aud_dat_miso_on", + "aud_dat_mosi_off", + "aud_dat_mosi_on", + "aud_gpio_i2s0_off", + "aud_gpio_i2s0_on", + "aud_gpio_i2s1_off", + "aud_gpio_i2s1_on", + "aud_gpio_i2s2_off", + "aud_gpio_i2s2_on", + "aud_gpio_i2s3_off", + "aud_gpio_i2s3_on", + "aud_gpio_tdm_off", + "aud_gpio_tdm_on", + "aud_gpio_pcm_off", + "aud_gpio_pcm_on", + "aud_gpio_dmic_sec"; + pinctrl-0 =3D <&aud_clk_mosi_off>; + pinctrl-1 =3D <&aud_clk_mosi_on>; + pinctrl-2 =3D <&aud_clk_miso_off>; + pinctrl-3 =3D <&aud_clk_miso_on>; + pinctrl-4 =3D <&aud_dat_miso_off>; + pinctrl-5 =3D <&aud_dat_miso_on>; + pinctrl-6 =3D <&aud_dat_mosi_off>; + pinctrl-7 =3D <&aud_dat_mosi_on>; + pinctrl-8 =3D <&aud_gpio_i2s0_off>; + pinctrl-9 =3D <&aud_gpio_i2s0_on>; + pinctrl-10 =3D <&aud_gpio_i2s1_off>; + pinctrl-11 =3D <&aud_gpio_i2s1_on>; + pinctrl-12 =3D <&aud_gpio_i2s2_off>; + pinctrl-13 =3D <&aud_gpio_i2s2_on>; + pinctrl-14 =3D <&aud_gpio_i2s3_off>; + pinctrl-15 =3D <&aud_gpio_i2s3_on>; + pinctrl-16 =3D <&aud_gpio_tdm_off>; + pinctrl-17 =3D <&aud_gpio_tdm_on>; + pinctrl-18 =3D <&aud_gpio_pcm_off>; + pinctrl-19 =3D <&aud_gpio_pcm_on>; + pinctrl-20 =3D <&aud_gpio_dmic_sec>; + mediatek,adsp =3D <&adsp>; + mediatek,platform =3D <&afe>; + + playback-codecs { + sound-dai =3D <&it6505dptx>, <&rt1019p>; + }; + + headset-codec { + sound-dai =3D <&rt5682s 0>; + }; + }; + + rt1019p: speaker-codec { + compatible =3D "realtek,rt1019p"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rt1019p_pins_default>; + sdb-gpios =3D <&pio 150 GPIO_ACTIVE_HIGH>; + #sound-dai-cells =3D <0>; + }; + + usb_p1_vbus: regulator-usb-p1-vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "vbus1"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&pio 148 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&pp5000_z2>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_enable_pin>; + post-power-on-delay-ms =3D <50>; + reset-gpios =3D <&pio 54 GPIO_ACTIVE_LOW>; + }; + + wifi_wakeup: wifi-wakeup { + compatible =3D "gpio-keys"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wifi_wakeup_pin>; + + wowlan-event { + label =3D "Wake on WiFi"; + gpios =3D <&pio 7 GPIO_ACTIVE_LOW>; + linux,code =3D ; + wakeup-source; + }; + }; +}; + +&adsp { + memory-region =3D <&adsp_dma_mem>, <&adsp_mem>; + status =3D "disabled"; /* causes stall */ +}; + +&afe { + i2s0-share =3D "I2S1"; + i2s3-share =3D "I2S2"; + status =3D "okay"; +}; + +&cci { + proc-supply =3D <&mt6366_vproc12_reg>; +}; + +&cpu0 { + proc-supply =3D <&mt6366_vproc12_reg>; +}; + +&cpu1 { + proc-supply =3D <&mt6366_vproc12_reg>; +}; + +&cpu2 { + proc-supply =3D <&mt6366_vproc12_reg>; +}; + +&cpu3 { + proc-supply =3D <&mt6366_vproc12_reg>; +}; + +&cpu4 { + proc-supply =3D <&mt6366_vproc12_reg>; +}; + +&cpu5 { + proc-supply =3D <&mt6366_vproc12_reg>; +}; + +&cpu6 { + proc-supply =3D <&mt6366_vproc11_reg>; +}; + +&cpu7 { + proc-supply =3D <&mt6366_vproc11_reg>; +}; + +&dpi { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&dpi_pins_default>; + pinctrl-1 =3D <&dpi_pins_sleep>; + status =3D "okay"; +}; + +&dpi_out { + remote-endpoint =3D <&it6505_in>; +}; + +&dsi0 { + status =3D "okay"; +}; + +&gic { + mediatek,broken-save-restore-fw; +}; + +&gpu { + mali-supply =3D <&mt6366_vgpu_reg>; + status =3D "okay"; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clock-frequency =3D <400000>; + i2c-scl-internal-delay-ns =3D <8000>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + /* + * Trackpad pin put here to work around second source components + * sharing the pinmux in steelix designs. + */ + pinctrl-0 =3D <&i2c2_pins>, <&trackpad_pin>; + clock-frequency =3D <400000>; + i2c-scl-internal-delay-ns =3D <10000>; + status =3D "okay"; + + trackpad@15 { + compatible =3D "elan,ekth3000"; + reg =3D <0x15>; + interrupts-extended =3D <&pio 11 IRQ_TYPE_LEVEL_LOW>; + vcc-supply =3D <&pp3300_s3>; + wakeup-source; + }; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + clock-frequency =3D <100000>; + status =3D "okay"; + + it6505dptx: dp-bridge@5c { + compatible =3D "ite,it6505"; + reg =3D <0x5c>; + interrupts-extended =3D <&pio 8 IRQ_TYPE_LEVEL_LOW>; + ovdd-supply =3D <&mt6366_vsim2_reg>; + pwr18-supply =3D <&pp1800_dpbrdg_dx>; + reset-gpios =3D <&pio 177 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&it6505_pins>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + #sound-dai-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + it6505_in: endpoint { + link-frequencies =3D /bits/ 64 <150000000>; + remote-endpoint =3D <&dpi_out>; + }; + }; + + port@1 { + reg =3D <1>; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + status =3D "okay"; + + rt5682s: codec@1a { + compatible =3D "realtek,rt5682s"; + reg =3D <0x1a>; + interrupts-extended =3D <&pio 17 IRQ_TYPE_EDGE_BOTH>; + AVDD-supply =3D <&mt6366_vio18_reg>; + DBVDD-supply =3D <&mt6366_vio18_reg>; + LDO1-IN-supply =3D <&mt6366_vio18_reg>; + MICVDD-supply =3D <&pp3300_z2>; + realtek,jd-src =3D <1>; + #sound-dai-cells =3D <1>; + }; +}; + +&mfg0 { + domain-supply =3D <&mt6366_vsram_gpu_reg>; +}; + +&mfg1 { + domain-supply =3D <&mt6366_vgpu_reg>; +}; + +&mipi_tx0 { + status =3D "okay"; +}; + +&mmc0 { + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_pins_default>; + pinctrl-1 =3D <&mmc0_pins_uhs>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + non-removable; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + no-sd; + no-sdio; + cap-mmc-hw-reset; + hs400-ds-delay =3D <0x11814>; + mediatek,hs400-ds-dly3 =3D <0x14>; + vmmc-supply =3D <&mt6366_vemc_reg>; + vqmmc-supply =3D <&mt6366_vio18_reg>; + status =3D "okay"; +}; + +&mmc1 { + pinctrl-names =3D "default", "state_uhs", "state_eint"; + pinctrl-0 =3D <&mmc1_pins_default>; + pinctrl-1 =3D <&mmc1_pins_uhs>; + pinctrl-2 =3D <&mmc1_pins_eint>; + /delete-property/ interrupts; + interrupt-names =3D "msdc", "sdio_wakeup"; + interrupts-extended =3D <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 87 IRQ_TYPE_LEVEL_LOW>; + bus-width =3D <4>; + max-frequency =3D <200000000>; + cap-sd-highspeed; + sd-uhs-sdr104; + sd-uhs-sdr50; + keep-power-in-suspend; + wakeup-source; + cap-sdio-irq; + no-mmc; + no-sd; + non-removable; + vmmc-supply =3D <&pp3300_s3>; + vqmmc-supply =3D <&mt6366_vio18_reg>; + mmc-pwrseq =3D <&wifi_pwrseq>; + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + bluetooth@2 { + compatible =3D "mediatek,mt7921s-bluetooth"; + reg =3D <2>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&bt_pins_reset>; + reset-gpios =3D <&pio 155 GPIO_ACTIVE_LOW>; + }; +}; + +&nor_flash { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&nor_pins_default>; + assigned-clock-parents =3D <&topckgen CLK_TOP_MAINPLL_D7_D4>; + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <39000000>; + }; +}; + +&pio { + /* 185 lines */ + gpio-line-names =3D "TP", + "TP", + "TP", + "I2S0_HP_DI", + "I2S3_DP_SPKR_DO", + "SAR_INT_ODL", + "BT_WAKE_AP_ODL", + "WIFI_INT_ODL", + "DPBRDG_INT_ODL", + "EDPBRDG_INT_ODL", + "EC_AP_HPD_OD", + "TCHPAD_INT_ODL", + "TCHSCR_INT_1V8_ODL", + "EC_AP_INT_ODL", + "EC_IN_RW_ODL", + "GSC_AP_INT_ODL", + /* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics call it AP_WP_ODL= . */ + "AP_FLASH_WP_L", + "HP_INT_ODL", + "PEN_EJECT_OD", + "WCAM_PWDN_L", + "WCAM_RST_L", + "UCAM_SEN_EN", + "UCAM_RST_L", + "LTE_RESET_L", + "LTE_SAR_DETECT_L", + "I2S2_DP_SPK_MCK", + "I2S2_DP_SPKR_BCK", + "I2S2_DP_SPKR_LRCK", + "I2S2_DP_SPKR_DI (TP)", + "EN_PP1000_EDPBRDG", + "EN_PP1800_EDPBRDG", + "EN_PP3300_EDPBRDG", + "UART_GSC_TX_AP_RX", + "UART_AP_TX_GSC_RX", + "UART_DBGCON_TX_ADSP_RX", + "UART_ADSP_TX_DBGCON_RX", + "EN_PP1000_DPBRDG", + "TCHSCR_REPORT_DISABLE", + "EN_PP3300_DPBRDG", + "EN_PP1800_DPBRDG", + "SPI_AP_CLK_EC", + "SPI_AP_CS_EC_L", + "SPI_AP_DO_EC_DI", + "SPI_AP_DI_EC_DO", + "SPI_AP_CLK_GSC", + "SPI_AP_CS_GSC_L", + "SPI_AP_DO_GSC_DI", + "SPI_AP_DI_GSC_DO", + "UART_DBGCON_TX_SCP_RX", + "UART_SCP_TX_DBGCON_RX", + "EN_PP1200_CAM_X", + "EN_PP2800A_VCM_X", + "EN_PP2800A_UCAM_X", + "EN_PP2800A_WCAM_X", + "WLAN_MODULE_RST_L", + "EN_PP1200_UCAM_X", + "I2S1_HP_DO", + "I2S1_HP_BCK", + "I2S1_HP_LRCK", + "I2S1_HP_MCK", + "TCHSCR_RST_1V8_L", + "SPI_AP_CLK_ROM", + "SPI_AP_CS_ROM_L", + "SPI_AP_DO_ROM_DI", + "SPI_AP_DI_ROM_DO", + "NC", + "NC", + "EMMC_STRB", + "EMMC_CLK", + "EMMC_CMD", + "EMMC_RST_L", + "EMMC_DATA0", + "EMMC_DATA1", + "EMMC_DATA2", + "EMMC_DATA3", + "EMMC_DATA4", + "EMMC_DATA5", + "EMMC_DATA6", + "EMMC_DATA7", + "AP_KPCOL0", + "NC", + "NC", + "NC", + "TP", + "SDIO_CLK", + "SDIO_CMD", + "SDIO_DATA0", + "SDIO_DATA1", + "SDIO_DATA2", + "SDIO_DATA3", + "NC", + "NC", + "NC", + "NC", + "NC", + "NC", + "EDPBRDG_PWREN", + "BL_PWM_1V8", + "EDPBRDG_RST_L", + "MIPI_DPI_CLK", + "MIPI_DPI_VSYNC", + "MIPI_DPI_HSYNC", + "MIPI_DPI_DE", + "MIPI_DPI_D0", + "MIPI_DPI_D1", + "MIPI_DPI_D2", + "MIPI_DPI_D3", + "MIPI_DPI_D4", + "MIPI_DPI_D5", + "MIPI_DPI_D6", + "MIPI_DPI_DA7", + "MIPI_DPI_D8", + "MIPI_DPI_D9", + "MIPI_DPI_D10", + "MIPI_DPI_D11", + "PCM_BT_CLK", + "PCM_BT_SYNC", + "PCM_BT_DI", + "PCM_BT_DO", + "JTAG_TMS_TP", + "JTAG_TCK_TP", + "JTAG_TDI_TP", + "JTAG_TDO_TP", + "JTAG_TRSTN_TP", + "CLK_24M_WCAM", + "CLK_24M_UCAM", + "UCAM_DET_ODL", + "AP_I2C_EDPBRDG_SCL_1V8", + "AP_I2C_EDPBRDG_SDA_1V8", + "AP_I2C_TCHSCR_SCL_1V8", + "AP_I2C_TCHSCR_SDA_1V8", + "AP_I2C_TCHPAD_SCL_1V8", + "AP_I2C_TCHPAD_SDA_1V8", + "AP_I2C_DPBRDG_SCL_1V8", + "AP_I2C_DPBRDG_SDA_1V8", + "AP_I2C_WLAN_SCL_1V8", + "AP_I2C_WLAN_SDA_1V8", + "AP_I2C_AUD_SCL_1V8", + "AP_I2C_AUD_SDA_1V8", + "AP_I2C_TPM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_UCAM_SCL_1V8", + "AP_I2C_UCAM_SDA_1V8", + "AP_I2C_WCAM_SCL_1V8", + "AP_I2C_WCAM_SDA_1V8", + "SCP_I2C_SENSOR_SCL_1V8", + "SCP_I2C_SENSOR_SDA_1V8", + "AP_EC_WARM_RST_REQ", + "AP_XHCI_INIT_DONE", + "USB3_HUB_RST_L", + "EN_SPKR", + "BEEP_ON", + "AP_EDP_BKLTEN", + "EN_PP3300_DISP_X", + "EN_PP3300_SDBRDG_X", + "BT_KILL_1V8_L", + "WIFI_KILL_1V8_L", + "PWRAP_SPI0_CSN", + "PWRAP_SPI0_CK", + "PWRAP_SPI0_MO", + "PWRAP_SPI0_MI", + "SRCLKENA0", + "SRCLKENA1", + "SCP_VREQ_VAO", + "AP_RTC_CLK32K", + "AP_PMIC_WDTRST_L", + "AUD_CLK_MOSI", + "AUD_SYNC_MOSI", + "AUD_DAT_MOSI0", + "AUD_DAT_MOSI1", + "AUD_CLK_MISO", + "AUD_SYNC_MISO", + "AUD_DAT_MISO0", + "AUD_DAT_MISO1", + "NC", + "NC", + "DPBRDG_PWREN", + "DPBRDG_RST_L", + "LTE_W_DISABLE_L", + "LTE_SAR_DETECT_L", + "EN_PP3300_LTE_X", + "LTE_PWR_OFF_L", + "LTE_RESET_L", + "TP", + "TP"; + + aud_clk_mosi_off: aud-clk-mosi-off-pins { + pins-clk-sync { + pinmux =3D , + ; + input-enable; + bias-pull-down; + }; + }; + + aud_clk_mosi_on: aud-clk-mosi-on-pins { + pins-clk-sync { + pinmux =3D , + ; + }; + }; + + aud_clk_miso_off: aud-clk-miso-off-pins { + pins-clk-sync { + pinmux =3D , + ; + input-enable; + bias-pull-down; + }; + }; + + aud_clk_miso_on: aud-clk-miso-on-pins { + pins-clk-sync { + pinmux =3D , + ; + }; + }; + + aud_dat_mosi_off: aud-dat-mosi-off-pins { + pins-dat { + pinmux =3D , + ; + input-enable; + bias-pull-down; + }; + }; + + aud_dat_mosi_on: aud-dat-mosi-on-pins { + pins-dat { + pinmux =3D , + ; + }; + }; + + aud_dat_miso_off: aud-dat-miso-off-pins { + pins-dat { + pinmux =3D , + ; + input-enable; + bias-pull-down; + }; + }; + + aud_dat_miso_on: aud-dat-miso-on-pins { + pins-dat { + pinmux =3D , + ; + input-schmitt-enable; + bias-disable; + }; + }; + + aud_gpio_i2s0_off: aud-gpio-i2s0-off-pins { + pins-sdata { + pinmux =3D ; + }; + }; + + aud_gpio_i2s0_on: aud-gpio-i2s0-on-pins { + pins-sdata { + pinmux =3D ; + }; + }; + + aud_gpio_i2s1_off: aud-gpio-i2s-off-pins { + pins-clk-sdata { + pinmux =3D , + , + , + ; + output-low; + }; + }; + + aud_gpio_i2s1_on: aud-gpio-i2s1-on-pins { + pins-clk-sdata { + pinmux =3D , + , + , + ; + }; + }; + + aud_gpio_i2s2_off: aud-gpio-i2s2-off-pins { + pins-cmd-dat { + pinmux =3D , + ; + output-low; + }; + }; + + aud_gpio_i2s2_on: aud-gpio-i2s2-on-pins { + pins-clk { + pinmux =3D , + ; + drive-strength =3D <4>; + }; + }; + + aud_gpio_i2s3_off: aud-gpio-i2s3-off-pins { + pins-sdata { + pinmux =3D ; + output-low; + }; + }; + + aud_gpio_i2s3_on: aud-gpio-i2s3-on-pins { + pins-sdata { + pinmux =3D ; + drive-strength =3D <4>; + }; + }; + + aud_gpio_tdm_off: aud-gpio-tdm-off-pins { }; + + aud_gpio_tdm_on: aud-gpio-tdm-on-pins { }; + + aud_gpio_pcm_off: aud-gpio-pcm-off-pins { + pins-clk-sdata { + pinmux =3D , + , + , + ; + output-low; + }; + }; + + aud_gpio_pcm_on: aud-gpio-pcm-on-pins { + pins-clk-sdata { + pinmux =3D , + , + , + ; + }; + }; + + aud_gpio_dmic_sec: aud-gpio-dmic-sec-pins { + pins { + pinmux =3D ; + output-low; + }; + }; + + bt_pins_reset: bt-reset-pins { + pins-bt-reset { + pinmux =3D ; + output-high; + }; + }; + + dpi_pins_sleep: dpi-sleep-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength =3D <10>; + output-low; + }; + }; + + dpi_pins_default: dpi-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength =3D <10>; + }; + }; + + ec_ap_int: cros-ec-int-pins { + pins-ec-ap-int-odl { + pinmux =3D ; + input-enable; + }; + }; + + edp_panel_fixed_pins: edp-panel-fixed-pins { + pins-vreg-en { + pinmux =3D ; + output-high; + }; + }; + + en_pp1800_dpbrdg: en-pp1800-dpbrdg-pins { + pins-vreg-en { + pinmux =3D ; + output-low; + }; + }; + + gsc_int: gsc-int-pins { + pins-gsc-ap-int-odl { + pinmux =3D ; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c2_pins: i2c2-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c3_pins: i2c3-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <4>; + input-enable; + }; + }; + + i2c5_pins: i2c5-pins { + pins-bus { + pinmux =3D , + ; + bias-disable; + drive-strength =3D <4>; + input-enable; + }; + }; + + it6505_pins: it6505-pins { + pins-hpd { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-int { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux =3D ; + output-low; + bias-pull-up; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-clk { + pinmux =3D ; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up =3D ; + }; + + pins-rst { + pinmux =3D ; + bias-pull-up =3D ; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + bias-pull-up =3D ; + }; + }; + + mmc1_pins_default: mmc1-default-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + }; + + mmc1_pins_eint: mmc1-eint-pins { + pins-dat1 { + pinmux =3D ; + input-enable; + bias-pull-up =3D ; + }; + }; + + nor_pins_default: nor-default-pins { + pins-clk-dat { + pinmux =3D , + , + ; + drive-strength =3D <6>; + bias-pull-down; + }; + + pins-cs-dat { + pinmux =3D , + , + ; + drive-strength =3D <6>; + bias-pull-up; + }; + }; + + pen_eject: pen-eject-pins { + pins { + pinmux =3D ; + input-enable; + /* External pull-up. */ + bias-disable; + }; + }; + + pwm0_pin: disp-pwm-pins { + pins { + pinmux =3D ; + output-high; + }; + }; + + rt1019p_pins_default: rt1019p-default-pins { + pins-sdb { + pinmux =3D ; + output-low; + }; + }; + + scp_pins: scp-default-pins { + pins-scp-uart { + pinmux =3D , + ; + }; + }; + + spi1_pins: spi1-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-disable; + input-enable; + }; + }; + + spi2_pins: spi2-pins { + pins-bus { + pinmux =3D , + , + , + ; + bias-disable; + input-enable; + }; + }; + + spmi_pins: spmi-pins { + pins-bus { + pinmux =3D , + ; + }; + }; + + touchscreen_pins: touchscreen-pins { + pins-irq { + pinmux =3D ; + input-enable; + bias-pull-up; + }; + + pins-reset { + pinmux =3D ; + output-high; + }; + + pins-report-sw { + pinmux =3D ; + output-low; + }; + }; + + trackpad_pin: trackpad-default-pins { + pins-int-n { + pinmux =3D ; + input-enable; + bias-disable; /* pulled externally */ + }; + }; + + wifi_enable_pin: wifi-enable-pins { + pins-wifi-enable { + pinmux =3D ; + }; + }; + + wifi_wakeup_pin: wifi-wakeup-pins { + pins-wifi-wakeup { + pinmux =3D ; + input-enable; + }; + }; +}; + +&pwm0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm0_pin>; + status =3D "okay"; +}; + +&pwrap { + pmic { + compatible =3D "mediatek,mt6366", "mediatek,mt6358"; + interrupt-controller; + interrupts-extended =3D <&pio 201 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells =3D <2>; + + mt6366codec: codec { + compatible =3D "mediatek,mt6366-sound", "mediatek,mt6358-sound"; + Avdd-supply =3D <&mt6366_vaud28_reg>; + mediatek,dmic-mode =3D <1>; /* one-wire */ + }; + + mt6366_regulators: regulators { + compatible =3D "mediatek,mt6366-regulator", "mediatek,mt6358-regulator"; + vsys-ldo1-supply =3D <&pp4200_z2>; + vsys-ldo2-supply =3D <&pp4200_z2>; + vsys-ldo3-supply =3D <&pp4200_z2>; + vsys-vcore-supply =3D <&pp4200_z2>; + vsys-vdram1-supply =3D <&pp4200_z2>; + vsys-vgpu-supply =3D <&pp4200_z2>; + vsys-vmodem-supply =3D <&pp4200_z2>; + vsys-vpa-supply =3D <&pp4200_z2>; + vsys-vproc11-supply =3D <&pp4200_z2>; + vsys-vproc12-supply =3D <&pp4200_z2>; + vsys-vs1-supply =3D <&pp4200_z2>; + vsys-vs2-supply =3D <&pp4200_z2>; + vs1-ldo1-supply =3D <&mt6366_vs1_reg>; + vs2-ldo1-supply =3D <&mt6366_vdram1_reg>; + vs2-ldo2-supply =3D <&mt6366_vs2_reg>; + vs2-ldo3-supply =3D <&mt6366_vs2_reg>; + + vcore { + regulator-name =3D "pp0750_dvdd_core"; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <200>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + + mt6366_vdram1_reg: vdram1 { + regulator-name =3D "pp1125_emi_vdd2"; + regulator-min-microvolt =3D <1125000>; + regulator-max-microvolt =3D <1125000>; + regulator-ramp-delay =3D <12500>; + regulator-enable-ramp-delay =3D <0>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + + mt6366_vgpu_reg: vgpu { + /* + * Called "ppvar_dvdd_gpu" in the schematic. + * Called "ppvar_dvdd_vgpu" here to match + * regulator coupling requirements. + */ + regulator-name =3D "ppvar_dvdd_vgpu"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <200>; + regulator-allowed-modes =3D ; + regulator-coupled-with =3D <&mt6366_vsram_gpu_reg>; + regulator-coupled-max-spread =3D <10000>; + }; + + mt6366_vproc11_reg: vproc11 { + regulator-name =3D "ppvar_dvdd_proc_bc_mt6366"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <1200000>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <200>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + + mt6366_vproc12_reg: vproc12 { + regulator-name =3D "ppvar_dvdd_proc_lc"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <1200000>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <200>; + regulator-allowed-modes =3D ; + regulator-always-on; + }; + + mt6366_vs1_reg: vs1 { + regulator-name =3D "pp2000_vs1"; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-ramp-delay =3D <12500>; + regulator-enable-ramp-delay =3D <0>; + regulator-always-on; + }; + + mt6366_vs2_reg: vs2 { + regulator-name =3D "pp1350_vs2"; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; + regulator-ramp-delay =3D <12500>; + regulator-enable-ramp-delay =3D <0>; + regulator-always-on; + }; + + va12 { + regulator-name =3D "pp1200_va12"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-enable-ramp-delay =3D <270>; + regulator-always-on; + }; + + mt6366_vaud28_reg: vaud28 { + regulator-name =3D "pp2800_vaud28"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <270>; + }; + + mt6366_vaux18_reg: vaux18 { + regulator-name =3D "pp1840_vaux18"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1840000>; + regulator-enable-ramp-delay =3D <270>; + }; + + mt6366_vbif28_reg: vbif28 { + regulator-name =3D "pp2800_vbif28"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <270>; + }; + + mt6366_vcn18_reg: vcn18 { + regulator-name =3D "pp1800_vcn18_x"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <270>; + }; + + mt6366_vcn28_reg: vcn28 { + regulator-name =3D "pp2800_vcn28_x"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <270>; + }; + + mt6366_vefuse_reg: vefuse { + regulator-name =3D "pp1800_vefuse"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <270>; + }; + + mt6366_vfe28_reg: vfe28 { + regulator-name =3D "pp2800_vfe28_x"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <270>; + }; + + mt6366_vemc_reg: vemc { + regulator-name =3D "pp3000_vemc"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-enable-ramp-delay =3D <60>; + }; + + mt6366_vibr_reg: vibr { + regulator-name =3D "pp2800_vibr_x"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <60>; + }; + + mt6366_vio18_reg: vio18 { + regulator-name =3D "pp1800_vio18_s3"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <2700>; + regulator-always-on; + }; + + mt6366_vio28_reg: vio28 { + regulator-name =3D "pp2800_vio28_x"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-enable-ramp-delay =3D <270>; + }; + + mt6366_vm18_reg: vm18 { + regulator-name =3D "pp1800_emi_vdd1"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1840000>; + regulator-enable-ramp-delay =3D <325>; + regulator-always-on; + }; + + mt6366_vmc_reg: vmc { + regulator-name =3D "pp3000_vmc"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-enable-ramp-delay =3D <60>; + }; + + mt6366_vmddr_reg: vmddr { + regulator-name =3D "pm0750_emi_vmddr"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <750000>; + regulator-enable-ramp-delay =3D <325>; + regulator-always-on; + }; + + mt6366_vmch_reg: vmch { + regulator-name =3D "pp3000_vmch"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-enable-ramp-delay =3D <60>; + }; + + mt6366_vcn33_reg: vcn33 { + regulator-name =3D "pp3300_vcn33_x"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-enable-ramp-delay =3D <270>; + }; + + vdram2 { + regulator-name =3D "pp0600_emi_vddq"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <600000>; + regulator-enable-ramp-delay =3D <3300>; + regulator-always-on; + }; + + mt6366_vrf12_reg: vrf12 { + regulator-name =3D "pp1200_vrf12_x"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-enable-ramp-delay =3D <120>; + }; + + mt6366_vrf18_reg: vrf18 { + regulator-name =3D "pp1800_vrf18_x"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-enable-ramp-delay =3D <120>; + }; + + vsim1 { + regulator-name =3D "pp1860_vsim1_x"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1860000>; + regulator-enable-ramp-delay =3D <540>; + }; + + mt6366_vsim2_reg: vsim2 { + regulator-name =3D "pp2760_vsim2_x"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2760000>; + regulator-enable-ramp-delay =3D <540>; + }; + + mt6366_vsram_gpu_reg: vsram-gpu { + regulator-name =3D "pp0900_dvdd_sram_gpu"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <1050000>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <240>; + regulator-coupled-with =3D <&mt6366_vgpu_reg>; + regulator-coupled-max-spread =3D <10000>; + }; + + mt6366_vsram_others_reg: vsram-others { + regulator-name =3D "pp0900_dvdd_sram_core"; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <240>; + regulator-always-on; + }; + + mt6366_vsram_proc11_reg: vsram-proc11 { + regulator-name =3D "pp0900_dvdd_sram_bc"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <1120000>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <240>; + regulator-always-on; + }; + + mt6366_vsram_proc12_reg: vsram-proc12 { + regulator-name =3D "pp0900_dvdd_sram_lc"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <1120000>; + regulator-ramp-delay =3D <6250>; + regulator-enable-ramp-delay =3D <240>; + regulator-always-on; + }; + + vusb { + regulator-name =3D "pp3070_vusb"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3070000>; + regulator-enable-ramp-delay =3D <270>; + regulator-always-on; + }; + + vxo22 { + regulator-name =3D "pp2240_vxo22"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <2240000>; + regulator-enable-ramp-delay =3D <120>; + /* Feeds DCXO internally */ + regulator-always-on; + }; + }; + + rtc { + compatible =3D "mediatek,mt6366-rtc", "mediatek,mt6358-rtc"; + }; + }; +}; + +&scp { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&scp_pins>; + firmware-name =3D "mediatek/mt8186/scp.img"; + memory-region =3D <&scp_mem>; + status =3D "okay"; + + cros-ec-rpmsg { + compatible =3D "google,cros-ec-rpmsg"; + mediatek,rpmsg-name =3D "cros-ec-rpmsg"; + }; +}; + +&spi1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi1_pins>; + mediatek,pad-select =3D <0>; + status =3D "okay"; + + cros_ec: ec@0 { + compatible =3D "google,cros-ec-spi"; + reg =3D <0>; + spi-max-frequency =3D <1000000>; + interrupts-extended =3D <&pio 13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ec_ap_int>; + + i2c_tunnel: i2c-tunnel { + compatible =3D "google,cros-ec-i2c-tunnel"; + google,remote-bus =3D <1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + typec { + compatible =3D "google,cros-ec-typec"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + usb_c0: connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + label =3D "left"; + power-role =3D "dual"; + data-role =3D "host"; + try-power-role =3D "source"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + typec_port0: endpoint { }; + }; + }; + }; + + usb_c1: connector@1 { + compatible =3D "usb-c-connector"; + reg =3D <1>; + label =3D "right"; + power-role =3D "dual"; + data-role =3D "host"; + try-power-role =3D "source"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@1 { + reg =3D <1>; + + typec_port1: endpoint { }; + }; + }; + }; + }; + }; +}; + +&spi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&spi2_pins>; + cs-gpios =3D <&pio 45 GPIO_ACTIVE_LOW>; + mediatek,pad-select =3D <0>; + status =3D "okay"; + + tpm@0 { + compatible =3D "google,cr50"; + reg =3D <0>; + spi-max-frequency =3D <1000000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&gsc_int>; + interrupt-parent =3D <&pio>; + interrupts =3D <15 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&ssusb0 { + status =3D "okay"; +}; + +&ssusb1 { + status =3D "okay"; +}; + +&u3phy0 { + status =3D "okay"; +}; + +&u3phy1 { + status =3D "okay"; +}; + +&uart0 { + status =3D "okay"; +}; + +&usb_host0 { + vbus-supply =3D <&pp3300_s3>; + status =3D "okay"; +}; + +&usb_host1 { + vbus-supply =3D <&usb_p1_vbus>; + status =3D "okay"; + #address-cells =3D <2>; + #size-cells =3D <2>; +}; + +&watchdog { + mediatek,reset-by-toprgu; +}; + +#include +#include --=20 2.43.0.rc2.451.g8631bc7472-goog