From nobody Mon Dec 29 00:36:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D44FFC10F04 for ; Sat, 2 Dec 2023 14:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233026AbjLBOPs (ORCPT ); Sat, 2 Dec 2023 09:15:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232975AbjLBOPo (ORCPT ); Sat, 2 Dec 2023 09:15:44 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8563A12E for ; Sat, 2 Dec 2023 06:15:51 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E82F8C433C8; Sat, 2 Dec 2023 14:15:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701526551; bh=fwdhwt3eDeqZRwcBFACwkkWnjPtptuE2Wu5b5bty77c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oQ72I/i6LN9WRbDkrkT9M9kOLmigG1FyWGGpxqvKDzK8Ed7mBok7Xna5Rno92B6gj /XX0nb16HB6UkRBDog/J/WWTPO/5HtSFde3mvKL+Yo4z4M7PJyanFKMRJ0ecX0vpwu kW0h6cCwkSUUIOzNSolHE+92AyLd7syaH+iL98NweXOkA4xA5WEnnmMAVNqHUvYlDN fYOdl/nIa/HYzblmbtfeba1gDN0VzQEY7gta52VNWuc+y4S4MLdaGLanZV9Ne5H8uM yxx/DRCMIs+4u1zB+ol2wV6E7lqNnlKjcWNXa+lYHWlMxDrNxj8nY5kExp7zxqauhT 62de3GKfgbhDQ== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] riscv: select ARCH_USE_CMPXCHG_LOCKREF Date: Sat, 2 Dec 2023 22:03:22 +0800 Message-Id: <20231202140323.315-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231202140323.315-1-jszhang@kernel.org> References: <20231202140323.315-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Select ARCH_USE_CMPXCHG_LOCKREF to enable the cmpxchg-based lockless lockref implementation for riscv. Using Linus' test case[1] on TH1520 platform, I see a 11.2% improvement. On JH7110 platform, I see 12.0% improvement. Link: http://marc.info/?l=3Dlinux-fsdevel&m=3D137782380714721&w=3D4 [1] Signed-off-by: Jisheng Zhang Reviewed-by: Andrea Parri # code audit, QEMU tests --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 433ec617703e..da4ae76a892c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -51,6 +51,7 @@ config RISCV select ARCH_SUPPORTS_PAGE_TABLE_CHECK if MMU select ARCH_SUPPORTS_PER_VMA_LOCK if MMU select ARCH_SUPPORTS_SHADOW_CALL_STACK if HAVE_SHADOW_CALL_STACK + select ARCH_USE_CMPXCHG_LOCKREF if 64BIT select ARCH_USE_MEMTEST select ARCH_USE_QUEUED_RWLOCKS select ARCH_USES_CFI_TRAPS if CFI_CLANG --=20 2.42.0 From nobody Mon Dec 29 00:36:17 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4DE0C4167B for ; Sat, 2 Dec 2023 14:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233046AbjLBOPv (ORCPT ); Sat, 2 Dec 2023 09:15:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232987AbjLBOPq (ORCPT ); Sat, 2 Dec 2023 09:15:46 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A39A11C for ; Sat, 2 Dec 2023 06:15:53 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A3574C433B6; Sat, 2 Dec 2023 14:15:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701526552; bh=f5wYmmEc/6YNMD4xeSRCsSaZscE5Ri2p04isx1ogm+s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ial5msYMisNvSBLgaIv84BoLRvHY5kBgWPY2YeInOEJ03ZnAa+AU8INHjN48bxfof KJx5rAacZfFcgF1QYUUOkQyJSThnvmHmzlOlgdLg0I+occ47+4DyG91NJKP86M4RDs LPq3zhIgi1Gv/xvP4arCU2uAa8uhs2hTnlcWPYX0n4bSqHrVaf0RvoNZtQUL4xRKlF D1tCHvXQdP9MsjEsAAGX5Zq8SoFhlWsJdRz2FFTYbuS7DP8DJ3wgSFseWk4SMOzgF4 z0dqLn3uX6cT306Y3tErtpAcxAmmQ39Yhnb8KVYCdM27TkerisIXDEeXZ71zPmg/nT KSHPimVFypkpg== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} Date: Sat, 2 Dec 2023 22:03:23 +0800 Message-Id: <20231202140323.315-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231202140323.315-1-jszhang@kernel.org> References: <20231202140323.315-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" After selecting ARCH_USE_CMPXCHG_LOCKREF, one straight futher optimization is implementing the arch_cmpxchg64_relaxed() because the lockref code does not need the cmpxchg to have barrier semantics. At the same time, implement arch_cmpxchg64_acquire and arch_cmpxchg64_release as well. However, on both TH1520 and JH7110 platforms, I didn't see obvious performance improvement with Linus' test case [1]. IMHO, this may be related with the fence and lr.d/sc.d hw implementations. In theory, lr/sc without fence could give performance improvement over lr/sc plus fence, so add the code here to leave performance improvement room on newer HW platforms. Link: http://marc.info/?l=3Dlinux-fsdevel&m=3D137782380714721&w=3D4 [1] Signed-off-by: Jisheng Zhang Reviewed-by: Andrea Parri # code audit, QEMU tests --- arch/riscv/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 2f4726d3cfcc..6318187f426f 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -360,4 +360,22 @@ arch_cmpxchg_relaxed((ptr), (o), (n)); \ }) =20 +#define arch_cmpxchg64_relaxed(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_relaxed((ptr), (o), (n)); \ +}) + +#define arch_cmpxchg64_acquire(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_acquire((ptr), (o), (n)); \ +}) + +#define arch_cmpxchg64_release(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_release((ptr), (o), (n)); \ +}) + #endif /* _ASM_RISCV_CMPXCHG_H */ --=20 2.42.0