From nobody Mon Dec 29 02:44:37 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C2C4C4167B for ; Sat, 2 Dec 2023 11:30:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232554AbjLBLaq (ORCPT ); Sat, 2 Dec 2023 06:30:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48516 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232138AbjLBLan (ORCPT ); Sat, 2 Dec 2023 06:30:43 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1195E18C for ; Sat, 2 Dec 2023 03:30:50 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 854DEC433C9; Sat, 2 Dec 2023 11:30:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701516649; bh=oaq++MapooJ2EycnyO1+1SBXzHdLUChecLPa1P5lthc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZeZCW75wrX6ms+WZ1Q1JgUt/WzAHbFZf1HVXg2hrKN0kBjzw08Dy8KNefoQkj8QC9 CIbXEeuGws/75/j8IxDFJPY7WGCDnK4OnHFcKM+Jy+ijxoxxT0eRNeOCgzbKzZgh+d 8+ISGPYJgWL7hHCdil9LwMReV/TUPNhlFWZ4gkZKwKtmSNzfEDBSYPB0+ng5k+iV9g yckiS4b1k3jHwNDXGXit+F8HnicCnTOjKY3Nava6OZCxlh+d3jJ4iTookCYTDn7r1O ap+b3UJE72tLvB5dAFCaf1nxn0htHgn+LPssyVIvrUVOub1zx7vN2eRPm3GyWkb6gY K3uvO57syMwjw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESS Date: Sat, 2 Dec 2023 19:18:21 +0800 Message-Id: <20231202111822.3569-2-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231202111822.3569-1-jszhang@kernel.org> References: <20231202111822.3569-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some riscv implementations such as T-HEAD's C906, C908, C910 and C920 supports efficient unaligned access, for performance reason we want to enable HAVE_EFFICIENT_UNALIGNED_ACCESS on these platforms. To avoid performance regressions on other non efficient unaligned access platforms, HAVE_EFFICIENT_UNALIGNED_ACCESS can't be globaly selected. To solve this problem, runtime code patching based on the detected speed is a good solution. But that's not easy, it involves lots of work to modify vairous subsystems such as net, mm, lib and so on. This can be done step by step. Now let's introduce RISCV_EFFICIENT_UNALIGNED_ACCESS which depends on NONPORTABLE, if users know during config time that the kernel will be only run on those efficient unaligned access hw platforms, they can enable it. Obviously, generic unified kernel Image should enable it. Signed-off-by: Jisheng Zhang --- arch/riscv/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7f8aa25457ba..0a76209e9b02 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -654,6 +654,18 @@ config RISCV_MISALIGNED load/store for both kernel and userspace. When disable, misaligned accesses will generate SIGBUS in userspace and panic in kernel. =20 +config RISCV_EFFICIENT_UNALIGNED_ACCESS + bool "Use unaligned access for some functions" + depends on NONPORTABLE + select HAVE_EFFICIENT_UNALIGNED_ACCESS + default n + help + Say Y here if you want the kernel only run on hardware platforms which + support efficient unaligned access, then unaligned access will be used + in some functions for optimized performance. + + If unsure what to do here, say N. + endmenu # "Platform type" =20 menu "Kernel features" --=20 2.42.0