From nobody Mon Nov 18 02:57:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92A91C07E97 for ; Fri, 1 Dec 2023 12:16:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378789AbjLAMPw convert rfc822-to-8bit (ORCPT ); Fri, 1 Dec 2023 07:15:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378776AbjLAMPt (ORCPT ); Fri, 1 Dec 2023 07:15:49 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4021E1717; Fri, 1 Dec 2023 04:15:53 -0800 (PST) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 317B324E2A0; Fri, 1 Dec 2023 20:15:51 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 1 Dec 2023 20:15:51 +0800 Received: from jsia-virtual-machine.localdomain (60.54.3.230) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 1 Dec 2023 20:15:39 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , , , , , CC: , , , , Subject: [PATCH v3 6/6] riscv: dts: starfive: Add initial StarFive JH8100 device tree Date: Fri, 1 Dec 2023 20:14:10 +0800 Message-ID: <20231201121410.95298-7-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201121410.95298-1-jeeheng.sia@starfivetech.com> References: <20231201121410.95298-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [60.54.3.230] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add initial device tree for the StarFive JH8100 RISC-V SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Acked-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/Makefile | 2 + arch/riscv/boot/dts/starfive/jh8100-evb.dts | 28 ++ arch/riscv/boot/dts/starfive/jh8100.dtsi | 378 ++++++++++++++++++++ 3 files changed, 408 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/st= arfive/Makefile index 0141504c0f5c..ef5c7331c7ec 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -10,3 +10,5 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7100-starfive-visionfi= ve-v1.dtb =20 dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.3b.dtb + +dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh8100-evb.dtb diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/= dts/starfive/jh8100-evb.dts new file mode 100644 index 000000000000..c16bc25d8988 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +#include "jh8100.dtsi" + +/ { + model =3D "StarFive JH8100 EVB"; + compatible =3D "starfive,jh8100-evb", "starfive,jh8100"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@40000000 { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0x2 0x00000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts= /starfive/jh8100.dtsi new file mode 100644 index 000000000000..f26aff5c1ddf --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi @@ -0,0 +1,378 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +/dts-v1/; + +/ { + compatible =3D "starfive,jh8100"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <4000000>; + + cpu0: cpu@0 { + compatible =3D "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz =3D <768>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <512>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c0>; + reg =3D <0x0>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz =3D <768>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <512>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c1>; + reg =3D <0x1>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz =3D <1024>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <1024>; + d-cache-size =3D <65536>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <1024>; + i-cache-size =3D <65536>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + reg =3D <0x2>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz =3D <1024>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <1024>; + d-cache-size =3D <65536>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <1024>; + i-cache-size =3D <65536>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + reg =3D <0x3>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu4: cpu@4 { + compatible =3D "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz =3D <1024>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <1024>; + d-cache-size =3D <65536>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <1024>; + i-cache-size =3D <65536>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + reg =3D <0x4>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu5: cpu@5 { + compatible =3D "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz =3D <1024>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <1024>; + d-cache-size =3D <65536>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <1024>; + i-cache-size =3D <65536>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + reg =3D <0x5>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu1>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu2>; + }; + + core1 { + cpu =3D <&cpu3>; + }; + + core2 { + cpu =3D <&cpu4>; + }; + + core3 { + cpu =3D <&cpu5>; + }; + }; + }; + + l2c0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <512>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2c1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <512>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2c2: cache-controller-2{ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <4096>; + cache-size =3D <0x200000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l3_cache: cache-controller-3 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-sets =3D <8192>; + cache-size =3D <0x400000>; + cache-unified; + }; + }; + + clk_uart: clk-uart { + compatible =3D "fixed-clock"; /* Initial clock handler for UART */ + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clint: clint@2000000 { + compatible =3D "starfive,jh8100-clint", "sifive,clint0"; + reg =3D <0x0 0x2000000 0x0 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + compatible =3D "starfive,jh8100-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0x0c000000 0x0 0x4000000>; + riscv,ndev =3D <200>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>; + }; + + uart0: serial@12160000 { + compatible =3D "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg =3D <0x0 0x12160000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&clk_uart>, <&clk_uart>; + interrupts =3D <67>; + status =3D "disabled"; + }; + + uart1: serial@12170000 { + compatible =3D "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg =3D <0x0 0x12170000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&clk_uart>, <&clk_uart>; + interrupts =3D <68>; + status =3D "disabled"; + }; + + uart2: serial@12180000 { + compatible =3D "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg =3D <0x0 0x12180000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&clk_uart>, <&clk_uart>; + interrupts =3D <69>; + status =3D "disabled"; + }; + + uart3: serial@12190000 { + compatible =3D "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg =3D <0x0 0x12190000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&clk_uart>, <&clk_uart>; + interrupts =3D <70>; + status =3D "disabled"; + }; + + uart4: serial@121a0000 { + compatible =3D "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg =3D <0x0 0x121a0000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&clk_uart>, <&clk_uart>; + interrupts =3D <71>; + status =3D "disabled"; + }; + + uart5: serial@127d0000 { + compatible =3D "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg =3D <0x0 0x127d0000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&clk_uart>, <&clk_uart>; + interrupts =3D <72>; + status =3D "disabled"; + }; + + uart6: serial@127e0000 { + compatible =3D "starfive,jh8100-uart", "cdns,uart-r1p8"; + reg =3D <0x0 0x127e0000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + clocks =3D <&clk_uart>, <&clk_uart>; + interrupts =3D <73>; + status =3D "disabled"; + }; + }; +}; --=20 2.34.1