From nobody Tue Dec 16 14:09:02 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 20DABC10DCE for ; Fri, 1 Dec 2023 10:40:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378329AbjLAKkb (ORCPT ); Fri, 1 Dec 2023 05:40:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378239AbjLAKk3 (ORCPT ); Fri, 1 Dec 2023 05:40:29 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3716D4A for ; Fri, 1 Dec 2023 02:40:35 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A31F6660739D; Fri, 1 Dec 2023 10:40:33 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1701427234; bh=UdqAnQyqUpZF3YGNOviQ2mxK+3TR9j8a8/SIDFRzpkA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TcZPEQmPQ3RJ9k95K1YM75cPXqO5FMKLgLedx0yqCugFsRH7QTEDL2+jJFBOmWuyW xLWJ3/uez5Cj4VrqYfqCWhFrqLJjn2qcPtdgPJ6cL7Exvk3jMJXrvMJESZuyzhWVhY +/9VUcMasAnbvibVG1GIlrmZ9WehDXpXQ5faC+V0XhGog0CjYfryMieThrR+z/tXjT ZjSl6B9m3qo3RrYAMH/wJWyqqTQPIh5yGCjyxKjVf49UhaNBO8gsjRmJ5srNv+2BJF 1U5M8lBY7EjkDqUmvds3BzKEQ9WUw2deb2WsgVHLuFKafX/js4SJHCOy/e2xnrjsFt 26V3cp06vH5Pw== From: AngeloGioacchino Del Regno To: boris.brezillon@collabora.com Cc: robh@kernel.org, steven.price@arm.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, daniel@ffwll.ch, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, kernel@collabora.com, m.szyprowski@samsung.com, krzysztof.kozlowski@linaro.org Subject: [PATCH v3 1/3] drm/panfrost: Ignore core_mask for poweroff and disable PWRTRANS irq Date: Fri, 1 Dec 2023 11:40:25 +0100 Message-ID: <20231201104027.35273-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231201104027.35273-1-angelogioacchino.delregno@collabora.com> References: <20231201104027.35273-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Some SoCs may be equipped with a GPU containing two core groups and this is exactly the case of Samsung's Exynos 5422 featuring an ARM Mali-T628 MP6 GPU: the support for this GPU in Panfrost is partial, as this driver currently supports using only one core group and that's reflected on all parts of it, including the power on (and power off, previously to this patch) function. The issue with this is that even though executing the soft reset operation should power off all cores unconditionally, on at least one platform we're seeing a crash that seems to be happening due to an interrupt firing which may be because we are calling power transition only on the first core group, leaving the second one unchanged, or because ISR execution was pending before entering the panfrost_gpu_power_off() function and executed after powering off the GPU cores, or all of the above. Finally, solve this by: - Avoid to enable the power transition interrupt on reset; and - Ignoring the core_mask and ask the GPU to poweroff both core groups Fixes: 22aa1a209018 ("drm/panfrost: Really power off GPU cores in panfrost_= gpu_power_off()") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Boris Brezillon Reviewed-by: Steven Price --- drivers/gpu/drm/panfrost/panfrost_gpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panf= rost/panfrost_gpu.c index 09f5e1563ebd..bd41617c5e4b 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -78,7 +78,12 @@ int panfrost_gpu_soft_reset(struct panfrost_device *pfde= v) } =20 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); - gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL); + + /* Only enable the interrupts we care about */ + gpu_write(pfdev, GPU_INT_MASK, + GPU_IRQ_MASK_ERROR | + GPU_IRQ_PERFCNT_SAMPLE_COMPLETED | + GPU_IRQ_CLEAN_CACHES_COMPLETED); =20 /* * All in-flight jobs should have released their cycle @@ -425,11 +430,10 @@ void panfrost_gpu_power_on(struct panfrost_device *pf= dev) =20 void panfrost_gpu_power_off(struct panfrost_device *pfdev) { - u64 core_mask =3D panfrost_get_core_mask(pfdev); int ret; u32 val; =20 - gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present & core_= mask); + gpu_write(pfdev, SHADER_PWROFF_LO, pfdev->features.shader_present); ret =3D readl_relaxed_poll_timeout(pfdev->iomem + SHADER_PWRTRANS_LO, val, !val, 1, 1000); if (ret) @@ -441,7 +445,7 @@ void panfrost_gpu_power_off(struct panfrost_device *pfd= ev) if (ret) dev_err(pfdev->dev, "tiler power transition timeout"); =20 - gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present & core_mask); + gpu_write(pfdev, L2_PWROFF_LO, pfdev->features.l2_present); ret =3D readl_poll_timeout(pfdev->iomem + L2_PWRTRANS_LO, val, !val, 0, 1000); if (ret) --=20 2.43.0