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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2024 21:36:50.9721 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 050e7f43-421e-4550-47d6-08dc12ed6c22 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6167 Content-Type: text/plain; charset="utf-8" The QOS Memory Bandwidth Enforcement Limit is reported by CPUID_Fn80000020_EAX_x01 and CPUID_Fn80000020_EAX_x02. Bits Description 31:0 BW_LEN: Size of the QOS Memory Bandwidth Enforcement Limit. Newer processors can support higher bandwidth limit than the current hard-coded value. Remove the hard-coded value and detect using CPUID command. Also update the register variables eax and edx to match the AMD CPUID definition. The CPUID details are documented in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature") Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- v4: Minor text changes and re-order of commit tags. v3: No change. Just updated with Reviewed-by v2: Earlier Sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ Sending it separate now. Addressed comments from Reinette about registe= rs being used from Intel definition. Also updated commit message. --- arch/x86/kernel/cpu/resctrl/core.c | 10 ++++------ arch/x86/kernel/cpu/resctrl/internal.h | 1 - 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 19e0681f0435..d04371e851b4 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -231,9 +231,7 @@ static bool __get_mem_config_intel(struct rdt_resource = *r) static bool __rdt_get_mem_config_amd(struct rdt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); - union cpuid_0x10_3_eax eax; - union cpuid_0x10_x_edx edx; - u32 ebx, ecx, subleaf; + u32 eax, ebx, ecx, edx, subleaf; =20 /* * Query CPUID_Fn80000020_EDX_x01 for MBA and @@ -241,9 +239,9 @@ static bool __rdt_get_mem_config_amd(struct rdt_resourc= e *r) */ subleaf =3D (r->rid =3D=3D RDT_RESOURCE_SMBA) ? 2 : 1; =20 - cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full); - hw_res->num_closid =3D edx.split.cos_max + 1; - r->default_ctrl =3D MAX_MBA_BW_AMD; + cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); + hw_res->num_closid =3D edx + 1; + r->default_ctrl =3D 1 << eax; =20 /* AMD does not use delay */ r->membw.delay_linear =3D false; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index a4f1aa15f0a2..d2979748fae4 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -18,7 +18,6 @@ #define MBM_OVERFLOW_INTERVAL 1000 #define MAX_MBA_BW 100u #define MBA_IS_LINEAR 0x4 -#define MAX_MBA_BW_AMD 0x800 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 =20 #define RMID_VAL_ERROR BIT_ULL(63) --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8AC0C4167D for ; Tue, 12 Dec 2023 18:02:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377082AbjLLSCW (ORCPT ); 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Tue, 12 Dec 2023 12:02:18 -0600 Subject: [PATCH v2 1/2] x86/resctrl: Remove hard-coded memory bandwidth limit From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 12 Dec 2023 12:02:18 -0600 Message-ID: <170240413801.760665.7930294172146734221.stgit@bmoger-ubuntu> In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D3:EE_|CH2PR12MB4891:EE_ X-MS-Office365-Filtering-Correlation-Id: 980fff2d-40e2-412d-5bb5-08dbfb3c7c99 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nlnqwDLMTf1ukKC8b1v3UVbQg6zS6v3P+aJkmmhyC+SD/b+iU9E1K0aWMVICJAkNjWfcPK+uKshUmUknMGnc8/jq2P6anuad/bXnMU0RP3AH+BhllOYA+3KeJOPVcQndJNigfsezGYHnOsTb4vmilUcWkhvKeA6Hxu1Jwq9Znqw6MILHcd+Zg3zGoqnsO0t3dsjLKcoj0up6PunUyVD8mCqYxs21aCZmYhZGuSUTSg/BooejJncT0B3N8u492bXz+KsoalG9Ptttl2/w+X3rR9oSVgQkVDw0njV0ak7D6DqeL6Epd4Hkw72G8DyrcGRCaPsr087GCp9eJ3dlD9WVOmPoeSNvR3eivNOMV2XrdaR7oz37m22iUcblZqAo8GKdz82DKzN/MNPmvqDZryPkMk6hZtnrHgzax1Hi3eVf3wzdSM1t1hxhl5kCq7FYUPl3mlH/SDrRy+ypJBa8DpmX562olLqaqDtDNoFwHIkQSAbBS2fa5Ntjly0T5/cbkDqgBxkCKS2W0pb3X929oJi6jiCdZnLEgyIDo6crTfDyuSMxQ5hv1/KQvwr9g03rK/ekR0LDxelTVIqj49Dd4Z4PTLanWAwdrCF8fa3N8BK3uqs7OMm+uconWzoSgoLZnVsD9zIufD8RySVONsSBW2/oGLF10Az5IYlQc302EjEQHYUZbHqOKIZhRml1wxbyfRsCCR34L4TdbJ0dUHJ7mJXDU+Cx31rgAehWp0YtWmj6K3oIUvxLiKeN7jnbdHMTVSEAaahV3BFf7RPasr8PZkULPHzsCZj5CFcA39JF9oMMjqod18qem8Gc9j9lFiK07nxaThpVVTYu161q7nY/V2D7eg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(7916004)(346002)(39860400002)(376002)(396003)(136003)(230922051799003)(451199024)(82310400011)(186009)(1800799012)(64100799003)(36840700001)(40470700004)(46966006)(16576012)(110136005)(316002)(70206006)(70586007)(54906003)(40460700003)(9686003)(41300700001)(16526019)(81166007)(26005)(336012)(426003)(33716001)(82740400003)(86362001)(356005)(103116003)(83380400001)(36860700001)(47076005)(478600001)(966005)(40480700001)(2906002)(44832011)(7416002)(5660300002)(4326008)(8936002)(8676002)(71626019)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2023 18:02:20.8841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 980fff2d-40e2-412d-5bb5-08dbfb3c7c99 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D3.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4891 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The QOS Memory Bandwidth Enforcement Limit is reported by CPUID_Fn80000020_EAX_x01 and CPUID_Fn80000020_EAX_x02. Bits Description 31:0 BW_LEN: Size of the QOS Memory Bandwidth Enforcement Limit. Newer processors can support higher bandwidth limit than the current hard-coded value. Remove the hard-coded value and detect using CPUID command. Also update the register variables eax and edx to match the AMD CPUID definition. The CPUID details are documentation in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature") Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v2: Earlier Sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ Sending it separate now. Addressed comments from Reinette about registe= rs being used from Intel definition. Also updated commit message. --- arch/x86/kernel/cpu/resctrl/core.c | 10 ++++------ arch/x86/kernel/cpu/resctrl/internal.h | 1 - 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 19e0681f0435..d04371e851b4 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -231,9 +231,7 @@ static bool __get_mem_config_intel(struct rdt_resource = *r) static bool __rdt_get_mem_config_amd(struct rdt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); - union cpuid_0x10_3_eax eax; - union cpuid_0x10_x_edx edx; - u32 ebx, ecx, subleaf; + u32 eax, ebx, ecx, edx, subleaf; =20 /* * Query CPUID_Fn80000020_EDX_x01 for MBA and @@ -241,9 +239,9 @@ static bool __rdt_get_mem_config_amd(struct rdt_resourc= e *r) */ subleaf =3D (r->rid =3D=3D RDT_RESOURCE_SMBA) ? 2 : 1; =20 - cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full); - hw_res->num_closid =3D edx.split.cos_max + 1; - r->default_ctrl =3D MAX_MBA_BW_AMD; + cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); + hw_res->num_closid =3D edx + 1; + r->default_ctrl =3D 1 << eax; =20 /* AMD does not use delay */ r->membw.delay_linear =3D false; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index a4f1aa15f0a2..d2979748fae4 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -18,7 +18,6 @@ #define MBM_OVERFLOW_INTERVAL 1000 #define MAX_MBA_BW 100u #define MBA_IS_LINEAR 0x4 -#define MAX_MBA_BW_AMD 0x800 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 =20 #define RMID_VAL_ERROR BIT_ULL(63) From nobody Mon Dec 29 04:18:10 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2046.outbound.protection.outlook.com [40.107.92.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1322D1B7E0; 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Mon, 15 Jan 2024 16:52:41 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 1/2] x86/resctrl: Remove hard-coded memory bandwidth limit Date: Mon, 15 Jan 2024 16:52:27 -0600 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4E:EE_|BY5PR12MB4178:EE_ X-MS-Office365-Filtering-Correlation-Id: 92ea1f0d-2ae4-4c0b-517c-08dc161caf57 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WXItU872YqD+uybYw/igxX1O+G2DvpN71ZNWqOvOfSCGCBIOnbUBXAzjiV9DkWJl/HXUiRKgR+SiUHU1nzxpFoGzrexlmUHo04MkkGyREByGsB91q1OnYOPkSFgnt04cdpyXnS/MiHOYqkhqHH8hTPX5/kCwaZailohDTSvCzIsVWtF89gbpMpMweNCsyuS6ssefufXP5vHMzRLor2GFYoKtKpLB7XKFPMYt2qUJK/499ZpKbp+m6b7FBmnoqcFLdf7Z+Hvv2kHZ8vCXkKm4YChoyqhDD3iCx0WvBdU5ma898VDHfbPxXMOVP4jMSSJwAuMZn/XJt0yisk4I65PoHsrAmsLKToDl44IlmG5i24f4kNgZ1ePnWZbsEccYcPIa0HvRagbb35Od6kIQ9vdDlhzgWgoXUTZvBxeMxrX3c7l2J8TST17Vb/Z+nEbHmoN/AzsRNCeqT+HX/M7X2GhV7YxQdVBpkWp3PjJ3zeFy7lggXMhCJU/qOxJhw0NNCZxC8Myz7grimmM6bbdRSQcnRlnTkwS1QtWWhXWxw7Iy91MZXt4WfYBuav5CfZVNGp4Hkilk+NH7YZAVZTM8vYPL4XdzedY+9KftJHhMG0Z/nmfJE7KlnKsiRdnO0BIc8PycKFLz9NU9zYzUNvl/WvBy/P9CsPn7eUBkH/SXFrveAB/KWorknvsAl/nGE3FDSRWDDp7vsIuNrIqZoPnKRTRQE30lznfmpAzeTBKG4YZ9WDUHE5AefdoW4GkFW2Q212YBMFQQskPg+6c9VuovmdxU3RPs0ZsS+XvczUhqjzLIZvA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(376002)(39860400002)(396003)(136003)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(82310400011)(36840700001)(40470700004)(46966006)(426003)(336012)(356005)(6666004)(16526019)(26005)(2616005)(966005)(7696005)(478600001)(36860700001)(83380400001)(4326008)(5660300002)(2906002)(44832011)(47076005)(70586007)(110136005)(316002)(54906003)(7416002)(8936002)(70206006)(8676002)(82740400003)(81166007)(86362001)(36756003)(41300700001)(40480700001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2024 22:52:43.5773 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92ea1f0d-2ae4-4c0b-517c-08dc161caf57 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4178 Content-Type: text/plain; charset="utf-8" The QOS Memory Bandwidth Enforcement Limit is reported by CPUID_Fn80000020_EAX_x01 and CPUID_Fn80000020_EAX_x02. Bits Description 31:0 BW_LEN: Size of the QOS Memory Bandwidth Enforcement Limit. Newer processors can support higher bandwidth limit than the current hard-coded value. Remove the hard-coded value and detect using CPUID command. Also update the register variables eax and edx to match the AMD CPUID definition. The CPUID details are documented in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature") Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- v5: No changes. v4: Minor text changes and re-order of commit tags. v3: No change. Just updated with Reviewed-by v2: Earlier Sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ Sending it separate now. Addressed comments from Reinette about registe= rs being used from Intel definition. Also updated commit message. --- arch/x86/kernel/cpu/resctrl/core.c | 10 ++++------ arch/x86/kernel/cpu/resctrl/internal.h | 1 - 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 19e0681f0435..d04371e851b4 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -231,9 +231,7 @@ static bool __get_mem_config_intel(struct rdt_resource = *r) static bool __rdt_get_mem_config_amd(struct rdt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); - union cpuid_0x10_3_eax eax; - union cpuid_0x10_x_edx edx; - u32 ebx, ecx, subleaf; + u32 eax, ebx, ecx, edx, subleaf; =20 /* * Query CPUID_Fn80000020_EDX_x01 for MBA and @@ -241,9 +239,9 @@ static bool __rdt_get_mem_config_amd(struct rdt_resourc= e *r) */ subleaf =3D (r->rid =3D=3D RDT_RESOURCE_SMBA) ? 2 : 1; =20 - cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full); - hw_res->num_closid =3D edx.split.cos_max + 1; - r->default_ctrl =3D MAX_MBA_BW_AMD; + cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); + hw_res->num_closid =3D edx + 1; + r->default_ctrl =3D 1 << eax; =20 /* AMD does not use delay */ r->membw.delay_linear =3D false; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index a4f1aa15f0a2..d2979748fae4 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -18,7 +18,6 @@ #define MBM_OVERFLOW_INTERVAL 1000 #define MAX_MBA_BW 100u #define MBA_IS_LINEAR 0x4 -#define MAX_MBA_BW_AMD 0x800 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 =20 #define RMID_VAL_ERROR BIT_ULL(63) --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0AAEC4167B for ; Fri, 1 Dec 2023 00:57:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229943AbjLAA5b (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:29.8277 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c427b9f2-90ed-4fb5-fa54-08dbf2087e7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4120 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The QOS Memory Bandwidth Enforcement Limit is reported by CPUID_Fn80000020_EAX_x01. Bits Description 31:0 BW_LEN: Size of the QOS Memory Bandwidth Enforcement Limit. Remove the hardcoded bandwidth limit value and detect using CPUID command. The CPUID details are documentation in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature") Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- arch/x86/kernel/cpu/resctrl/core.c | 2 +- arch/x86/kernel/cpu/resctrl/internal.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 19e0681f0435..3fbae10b662d 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -243,7 +243,7 @@ static bool __rdt_get_mem_config_amd(struct rdt_resourc= e *r) =20 cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full); hw_res->num_closid =3D edx.split.cos_max + 1; - r->default_ctrl =3D MAX_MBA_BW_AMD; + r->default_ctrl =3D 1 << eax.full; =20 /* AMD does not use delay */ r->membw.delay_linear =3D false; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index a4f1aa15f0a2..d2979748fae4 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -18,7 +18,6 @@ #define MBM_OVERFLOW_INTERVAL 1000 #define MAX_MBA_BW 100u #define MBA_IS_LINEAR 0x4 -#define MAX_MBA_BW_AMD 0x800 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 =20 #define RMID_VAL_ERROR BIT_ULL(63) --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2048.outbound.protection.outlook.com [40.107.102.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B6822C69C; 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Thu, 4 Jan 2024 15:21:53 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 1/2] x86/resctrl: Remove hard-coded memory bandwidth limit Date: Thu, 4 Jan 2024 15:21:29 -0600 Message-ID: <20240104212130.209490-1-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|MN6PR12MB8541:EE_ X-MS-Office365-Filtering-Correlation-Id: f1196c47-cc5a-43ba-0d11-08dc0d6b418f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: epyfQ1DtocKSOaug3Y4V9En72VcjcazNZ+X0p7mRB2wCXu3k03ztP7PjoYAmKbmYgt2jI58x8EppYiCPLFpmjUC7kCorsMYRE2wrX6TF3hrjil5IvY31L/uAbgLy0el3lnDBzy33mifZqFabzajpA2EMViQchz44vOTahDNKxKAOdo9Xnap2jLy/rLmiNZiMQCWwn8cdFE7+Wr26ZQkD5kavZsp/vjdkwSELEmxQQ1gbiKQBIBr0oIfsPvt48gsgdLgv4zT+LwOLS2MI9YimetW4Dh2JQS+trUBSk2kUlfiYpGF72Us2Gxgu7RrEXWXZ2VVY1R7xpE78LuTwycR2s5qlYRIYOKQcuJ9A0cxI5Eq045XXAph8KkTRMC8wivBEZAhCbX1BbpOBGNivQl71UhsZndP/0fxk8V6viGLx5CPK3njWPKpX8Q6TJD70GF+hAFFTSj3eN69ph980lC6pYcc+faCqteywYV0mmXBJMULiUycG3y5bkOrdCpicR0VUPFiWnQbfCf0vtg5G+nP7yH8V9qbeksgUArFwmozdOaig1vR6Wl3a0D6xWB0etpvx2aHee6Y5PKuloBT1jNCfecK3eJnTh0JgZ11T/8iL4knIGyOLegzwl/vNRUGdkVW4PKsh1hyux9M3pdhg2BvAr3PcoZIjQM7zdCgh8Avf01NMuFYAtQhS40JQ11u/+mmmt23AdEcdM3PRemGcT7DLpV0qlICCuoLlczlfPJH/uNQIF5BV/aO+U6ZNoit8FOE/HWcnNvjIAcPyCGOfqtGwKw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(39860400002)(396003)(230922051799003)(1800799012)(64100799003)(451199024)(82310400011)(186009)(36840700001)(46966006)(40470700004)(426003)(1076003)(26005)(2616005)(336012)(16526019)(36860700001)(81166007)(70206006)(83380400001)(356005)(82740400003)(47076005)(110136005)(70586007)(36756003)(966005)(478600001)(54906003)(86362001)(5660300002)(2906002)(7416002)(8936002)(44832011)(4326008)(8676002)(316002)(40460700003)(40480700001)(6666004)(7696005)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jan 2024 21:22:28.9823 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1196c47-cc5a-43ba-0d11-08dc0d6b418f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN6PR12MB8541 Content-Type: text/plain; charset="utf-8" The QOS Memory Bandwidth Enforcement Limit is reported by CPUID_Fn80000020_EAX_x01 and CPUID_Fn80000020_EAX_x02. Bits Description 31:0 BW_LEN: Size of the QOS Memory Bandwidth Enforcement Limit. Newer processors can support higher bandwidth limit than the current hard-coded value. Remove the hard-coded value and detect using CPUID command. Also update the register variables eax and edx to match the AMD CPUID definition. The CPUID details are documentation in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature") Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Reinette Chatre --- v3: No change. Just updated with Reviewed-by v2: Earlier Sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ Sending it separate now. Addressed comments from Reinette about registe= rs being used from Intel definition. Also updated commit message. --- arch/x86/kernel/cpu/resctrl/core.c | 10 ++++------ arch/x86/kernel/cpu/resctrl/internal.h | 1 - 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 19e0681f0435..d04371e851b4 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -231,9 +231,7 @@ static bool __get_mem_config_intel(struct rdt_resource = *r) static bool __rdt_get_mem_config_amd(struct rdt_resource *r) { struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); - union cpuid_0x10_3_eax eax; - union cpuid_0x10_x_edx edx; - u32 ebx, ecx, subleaf; + u32 eax, ebx, ecx, edx, subleaf; =20 /* * Query CPUID_Fn80000020_EDX_x01 for MBA and @@ -241,9 +239,9 @@ static bool __rdt_get_mem_config_amd(struct rdt_resourc= e *r) */ subleaf =3D (r->rid =3D=3D RDT_RESOURCE_SMBA) ? 2 : 1; =20 - cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full); - hw_res->num_closid =3D edx.split.cos_max + 1; - r->default_ctrl =3D MAX_MBA_BW_AMD; + cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx); + hw_res->num_closid =3D edx + 1; + r->default_ctrl =3D 1 << eax; =20 /* AMD does not use delay */ r->membw.delay_linear =3D false; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index a4f1aa15f0a2..d2979748fae4 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -18,7 +18,6 @@ #define MBM_OVERFLOW_INTERVAL 1000 #define MAX_MBA_BW 100u #define MBA_IS_LINEAR 0x4 -#define MAX_MBA_BW_AMD 0x800 #define MBM_CNTR_WIDTH_OFFSET_AMD 20 =20 #define RMID_VAL_ERROR BIT_ULL(63) --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4286BC4167B for ; Fri, 1 Dec 2023 00:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230246AbjLAA5k (ORCPT ); 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Thu, 30 Nov 2023 18:57:29 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 02/15] x86/resctrl: Remove hard-coded memory bandwidth event configuration Date: Thu, 30 Nov 2023 18:57:07 -0600 Message-ID: <20231201005720.235639-3-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A0:EE_|DM6PR12MB4465:EE_ X-MS-Office365-Filtering-Correlation-Id: 380d9b1b-d262-4ccd-1009-08dbf2087ff9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: FJKbQNJDWQMI42J2EZ9Q5EMqxO17sLtN+rSEdVI9CTB+h5YPMoVbY4Oooa8K9dQogqLLAQkDkMnaYFMbuxsJcE5pUW3JiGKhbOQ2VcZJvGOFHAmCHPb/xT8wEcj+QI1Rt+8IAcqRHcaaSd05zVZUBg9kMrJP6DNCMAVlGGIRnZYIHL7tU6wPK8XHVVPiPY5AnyFg2AlFy2iAyOO8IoiMX26LIT/14PwosLc8AXbsSHdVA9ch3AK0ICeSM7wLzEGR1HOc4+QKSMDydG8PrgOp5hIZxzQ6JS80M6lhIr4O4yMqpwm1JSY5msbBnaEbVJq1rFfT27m+b6hlskT2n38DjrOs+WJ99/7NyO7ybX/UbGOuAaEBZCg7xEVZI1CitREx4kKzQ0Mi5FS9pnzdH83wFp7BWG89ZYHliSC5orz/SJCkMYdaENSw1mN3GPs93WB6TJT+D5SgOk1M0jCFZDn5ARdN85SVtOLxh85PrWQeHtpE4QsdmMY4i7LJqqwgdXwvbYeyQN6hmzjnOl8IASXPC84Iol5x3O2SnxMV3no6RjWr/UOHEyI0z7d7xnx3f9Kj9nOaqKwiB+oofKDN740jvzko7Jqs5BMR9k8JK1K1EN0IJ6NiD4zTzYwh6zjXdy/VjiuphBZCAKVLRZvOdeVRRZ5NsiH4nuRqkMVFlEn1v9IifSWy/4uZWL8e8YMEr2QrZIk6QbILFiaCEmOlfg2PZvMGyW+i2k4YrliU4VlSBrCuy6jnSHk9p6/Jh2WDH2Px7u2E/f7ljIW0Pq+bPmn+Og== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(39860400002)(346002)(396003)(376002)(230922051799003)(451199024)(64100799003)(1800799012)(186009)(82310400011)(46966006)(36840700001)(40470700004)(8936002)(8676002)(4326008)(36756003)(54906003)(70586007)(70206006)(316002)(110136005)(2906002)(41300700001)(44832011)(86362001)(40460700003)(5660300002)(7416002)(426003)(81166007)(356005)(26005)(16526019)(40480700001)(82740400003)(336012)(47076005)(83380400001)(36860700001)(1076003)(478600001)(966005)(2616005)(6666004)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:32.3121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 380d9b1b-d262-4ccd-1009-08dbf2087ff9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4465 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured. Currently, the maximum supported event bitmask is hard-coded. This information can be detected by the CPUID_Fn80000020_ECX_x03. CPUID_Fn80000020_ECX_x03 [Platform QoS Monitoring Bandwidth Event Configuration] Read-only. Reset: 0000_007Fh. Bits Description 31:7 Reserved 6:0 Identifies the bandwidth sources that can be tracked. Remove the hardcoded value and detect using CPUID command. The CPUID details are documentation in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: dc2a3e857981 ("x86/resctrl: Add interface to read mbm_total_bytes_co= nfig") Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- arch/x86/kernel/cpu/resctrl/internal.h | 4 +--- arch/x86/kernel/cpu/resctrl/monitor.c | 11 +++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 ++-- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index d2979748fae4..524d8bec1439 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -50,9 +50,6 @@ /* Dirty Victims to All Types of Memory */ #define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) =20 -/* Max event bits supported */ -#define MAX_EVT_CONFIG_BITS GENMASK(6, 0) - struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -117,6 +114,7 @@ extern bool rdt_alloc_capable; extern bool rdt_mon_capable; extern unsigned int rdt_mon_features; extern struct list_head resctrl_schema_all; +extern unsigned int resctrl_max_evt_bitmask; =20 enum rdt_group_type { RDTCTRL_GROUP =3D 0, diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index f136ac046851..c611b16ba259 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -127,6 +127,11 @@ static const struct mbm_correction_factor_table { static u32 mbm_cf_rmidthreshold __read_mostly =3D UINT_MAX; static u64 mbm_cf __read_mostly; =20 +/* + * Identifies the list of QoS Bandwidth Sources to track + */ +unsigned int resctrl_max_evt_bitmask; + static inline u64 get_corrected_mbm_count(u32 rmid, unsigned long val) { /* Correct MBM value. */ @@ -813,6 +818,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *= r) return ret; =20 if (rdt_cpu_has(X86_FEATURE_BMEC)) { + u32 eax, ebx, ecx, edx; + + /* Detect list of bandwidth sources that can be tracked */ + cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx); + resctrl_max_evt_bitmask =3D ecx; + if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable =3D true; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2024 21:36:59.1345 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 30870af5-722d-4b5b-61d1-08dc12ed70fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7629 Content-Type: text/plain; charset="utf-8" If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured. The maximum supported bandwidth bitmask can be determined by following CPUID command. CPUID_Fn80000020_ECX_x03 [Platform QoS Monitoring Bandwidth Event Configuration] Read-only. Reset: 0000_007Fh. Bits Description 31:7 Reserved 6:0 Identifies the bandwidth sources that can be tracked. The bandwidth sources can change with the processor generations. Read the supported bandwidth sources using the CPUID command. While at it, move the mask checking to mon_config_write() before iterating over all the domains. Also, print the valid bitmask when the user tries to configure invalid event configuration value. The CPUID details are documented in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: dc2a3e857981 ("x86/resctrl: Add interface to read mbm_total_bytes_co= nfig") Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- v4: Minor text changes and re-order of commit tags. Moved the mask check to mon_config_write() before iterating over all the domains. v3: Changed the event_mask name to mbm_cfg_mask. Added comments about the f= ield. Reverted the masking of event configuration to original code. Few minor comment changes. v2: Earlier sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ But this is not related to ABMC. Sending it separate now. Removed the global resctrl_max_evt_bitmask. Added event_mask as part of the resource. --- arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 14 ++++++++------ 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index d2979748fae4..e3dc35a00a19 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -394,6 +394,8 @@ struct rdt_parse_data { * @msr_update: Function pointer to update QOS MSRs * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. + * @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth + * Monitoring Event Configuration (BMEC) is supported. * @cdp_enabled: CDP state of this resource * * Members of this structure are either private to the architecture @@ -408,6 +410,7 @@ struct rdt_hw_resource { struct rdt_resource *r); unsigned int mon_scale; unsigned int mbm_width; + unsigned int mbm_cfg_mask; bool cdp_enabled; }; =20 diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index f136ac046851..acca577e2b06 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -813,6 +813,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *= r) return ret; =20 if (rdt_cpu_has(X86_FEATURE_BMEC)) { + u32 eax, ebx, ecx, edx; + + /* Detect list of bandwidth sources that can be tracked */ + cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx); + hw_res->mbm_cfg_mask =3D ecx & MAX_EVT_CONFIG_BITS; + if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable =3D true; mbm_config_rftype_init("mbm_total_bytes_config"); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 69a1de92384a..8e9c96d0ee84 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1620,12 +1620,6 @@ static int mbm_config_write_domain(struct rdt_resour= ce *r, struct mon_config_info mon_info =3D {0}; int ret =3D 0; =20 - /* mon_config cannot be more than the supported set of events */ - if (val > MAX_EVT_CONFIG_BITS) { - rdt_last_cmd_puts("Invalid event configuration\n"); - return -EINVAL; - } - /* * Read the current config value first. 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Thu, 4 Jan 2024 15:22:22 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/2] x86/resctrl: Remove hard-coded memory bandwidth event configuration Date: Thu, 4 Jan 2024 15:21:30 -0600 Message-ID: <20240104212130.209490-2-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F5:EE_|IA1PR12MB8286:EE_ X-MS-Office365-Filtering-Correlation-Id: c4dab9b8-a66b-4951-7709-08dc0d6b429c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qFN5vhK2ZVbs6aLfqYlBZ6H9UkpJ6m6o0Jr19i6KVM826MVEl/lDr1SUpWAYSJboNQRNDlZO61OSI498mW49vMWpxsvdOiVWcU9ltxxn7wj7OkuBed08ypByC/pyrqMGZEHB8JbZmFJ4KFgYXyXdIDIM4ZgcBXehPVKRU7if8u1v/sZkrC6kKDqahysZID4+iMpGikw97Lw7unh2Mda7jIjoYEkM8gByL4pd/qQk5va7K5t7yYiVMckO+y6il5hv6rJhcsA565pCO7kjUvwu0FeGmfZRloq5HT0U1MkM0sjtQHiLfSkpKtnWHkebE2G+1oO6TClwuysxlM8JCw+2zNCaLyZMN7jcs80zvacyo9PcCgDgDYKu/+SGnNfO+a8EaxsSqP128Fixfo6cNLeumfhoOVvjhkTQhf15Kv6EFkQMuRe3bzyUrLI7Ep4IJoln/ecAU5hmmrvChg1TjYmjN1NWSes4Qxz+BjzJ+FaWAWhJnqWCUjx65rK3St/hf0af3pycVfBpSX4Uv2ixtNCPub4NBp2fFaHbaoi3QY4OwF/wFWxtW720B4Wu97wdL70A2bBBclpEiMJ1dEnk8iSsw0IOYHXYA1ZZ2w5j7DspECYQpa9ZBkFbjDXZJCLUO+rDsfqrafaAWJKIXNIQImUZcj0QfrXqbo4v5Qc1F6xCl61x2FdR0KG2TFgDRbqz22RHlbsS0L+jrUtJrw0ns+ImKzWfBnMxZ4OsMOmJ4SeBRp414aPWyQbIV1d+Hli0uBTf/wIXo+84bCFb/CivGKEV7g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(376002)(39860400002)(136003)(230922051799003)(64100799003)(186009)(1800799012)(451199024)(82310400011)(36840700001)(46966006)(40470700004)(8936002)(966005)(47076005)(8676002)(478600001)(316002)(4326008)(70206006)(2616005)(83380400001)(70586007)(36860700001)(110136005)(54906003)(6666004)(7696005)(1076003)(26005)(16526019)(44832011)(7416002)(2906002)(41300700001)(5660300002)(336012)(426003)(36756003)(82740400003)(356005)(81166007)(40480700001)(86362001)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Jan 2024 21:22:30.7323 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4dab9b8-a66b-4951-7709-08dc0d6b429c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8286 Content-Type: text/plain; charset="utf-8" If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured. The maximum supported bandwidth bitmask can be determined by following CPUID command. CPUID_Fn80000020_ECX_x03 [Platform QoS Monitoring Bandwidth Event Configuration] Read-only. Reset: 0000_007Fh. Bits Description 31:7 Reserved 6:0 Identifies the bandwidth sources that can be tracked. The bandwidth sources can change with the processor generations. Remove the hard-coded value and detect using CPUID command. Also, print the valid bitmask when the user tries to configure invalid value. The CPUID details are documentation in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: dc2a3e857981 ("x86/resctrl: Add interface to read mbm_total_bytes_co= nfig") Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v3: Changed the event_mask name to mbm_cfg_mask. Added comments about the f= ield. Reverted the masking of event configuration to original code. Few minor comment changes. v2: Earlier sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ But this is not related to ABMC. Sending it separate now. Removed the global resctrl_max_evt_bitmask. Added event_mask as part of the resource. --- arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 6 ++++-- 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index d2979748fae4..e3dc35a00a19 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -394,6 +394,8 @@ struct rdt_parse_data { * @msr_update: Function pointer to update QOS MSRs * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. + * @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth + * Monitoring Event Configuration (BMEC) is supported. * @cdp_enabled: CDP state of this resource * * Members of this structure are either private to the architecture @@ -408,6 +410,7 @@ struct rdt_hw_resource { struct rdt_resource *r); unsigned int mon_scale; unsigned int mbm_width; + unsigned int mbm_cfg_mask; bool cdp_enabled; }; =20 diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index f136ac046851..acca577e2b06 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -813,6 +813,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *= r) return ret; =20 if (rdt_cpu_has(X86_FEATURE_BMEC)) { + u32 eax, ebx, ecx, edx; + + /* Detect list of bandwidth sources that can be tracked */ + cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx); + hw_res->mbm_cfg_mask =3D ecx & MAX_EVT_CONFIG_BITS; + if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable =3D true; mbm_config_rftype_init("mbm_total_bytes_config"); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 69a1de92384a..5b5a8f0ffb2f 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1617,12 +1617,14 @@ static void mon_event_config_write(void *info) static int mbm_config_write_domain(struct rdt_resource *r, struct rdt_domain *d, u32 evtid, u32 val) { + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); struct mon_config_info mon_info =3D {0}; int ret =3D 0; =20 /* mon_config cannot be more than the supported set of events */ - if (val > MAX_EVT_CONFIG_BITS) { - rdt_last_cmd_puts("Invalid event configuration\n"); + if ((val & hw_res->mbm_cfg_mask) !=3D val) { + rdt_last_cmd_printf("Invalid input: The maximum valid bitmask is 0x%02x\= n", + hw_res->mbm_cfg_mask); return -EINVAL; } =20 --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 39963C4332F for ; Tue, 12 Dec 2023 18:03:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377073AbjLLSDJ (ORCPT ); Tue, 12 Dec 2023 13:03:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377055AbjLLSDI (ORCPT ); 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Tue, 12 Dec 2023 12:03:03 -0600 Subject: [PATCH v2 2/2] x86/resctrl: Remove hard-coded memory bandwidth event configuration From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , Date: Tue, 12 Dec 2023 12:02:25 -0600 Message-ID: <170240414535.760665.1609957728181418569.stgit@bmoger-ubuntu> In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> User-Agent: StGit/1.1.dev103+g5369f4c MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|BL1PR12MB5825:EE_ X-MS-Office365-Filtering-Correlation-Id: 63379046-8f51-4837-2ce5-08dbfb3c996a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jOtkfbmmOKwwOZyYUfUDpfHOxxoc3UNC1Mly85k7F/1i/5R0KQCm3jYY/VgcckL1trwShOzZU2UFIlvOMFTKaL2yZEBIXPBrtyVyuFdaMWFJBGGh0BjQYfRPBAjqWk/awJtu51BaUmYfwTpBZeTUGXGu4v83vi5zaitIg5NV1KEbK5cFgSnNvYo02wu1A9dpf6hIpYLIScW9ZW9/WYv4U6utwpj0P9jdCjJhRGNT7hoeeMIZLU17BVnfG3mH0ajNmVyPYB8tyLeZDeJD3AxUIRvwL+4zVgKM2PfZc2GDKzKp5sJoDlmHqzm5sXRoaep+N4uK9Uhm98/vH9tcAIRPy//3U3EORrJX7T9CVdKK9FfE7b+txkdvvjutaGHBC5V6tOvd2uKBUaCEjDLGXIsVLH+aDV2Yg25/3cCWuEFzF/ks6m82lZv27O/PuTaYe19gbz5OTVhlK5tipbU+ol0UwA/FCitpJS7CMmI1EvRCvveQbZ5rJH3kbsz/4uBwArlEtXyC7s3yexVmNdX0qEfZ7m+suCiqJfDqFvoa3cUrAUfpvoEGiHoVO3z/pJxZd5O6zWwf7SEUAt+llfmxDordBJZPqoBM4MawNexMItbMMtPs5beOQb7MwkZo01GegGcUuqpQOreVLA1CqQpGRrhE+RQ68c9b2/D04AKxLgGI/9m34zz75oI5sBQKN7W96WHvuqtrFXQjP/bDMjmmec2nDHkrlFpr5YcJJnRpn4xLW7xEG//7bbDgAUfdJHk0EbX+siEZ3uEAQRR8JClW4ocp0+XYEhlegdO4/N1hIkwBdu440r70itRY0uimBRPmTRmj/ercRGcjaOQr+6zrFNLJYg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(7916004)(376002)(136003)(39860400002)(346002)(396003)(230922051799003)(451199024)(1800799012)(64100799003)(186009)(82310400011)(36840700001)(40470700004)(46966006)(8936002)(8676002)(41300700001)(2906002)(4326008)(44832011)(5660300002)(7416002)(33716001)(478600001)(36860700001)(966005)(103116003)(16526019)(426003)(83380400001)(26005)(336012)(40480700001)(47076005)(6666004)(9686003)(82740400003)(54906003)(110136005)(16576012)(316002)(70586007)(70206006)(86362001)(81166007)(356005)(40460700003)(71626019)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Dec 2023 18:03:09.2289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63379046-8f51-4837-2ce5-08dbfb3c996a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5825 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured. The maximum supported bandwidth bitmask can be determined by following CPUID command. CPUID_Fn80000020_ECX_x03 [Platform QoS Monitoring Bandwidth Event Configuration] Read-only. Reset: 0000_007Fh. Bits Description 31:7 Reserved 6:0 Identifies the bandwidth sources that can be tracked. The bandwidth sources can change with the processor generations. Currently, this information is hard-coded. Remove the hard-coded value and detect using CPUID command. Also print the valid bitmask when the user tries to configure invalid value. The CPUID details are documentation in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: dc2a3e857981 ("x86/resctrl: Add interface to read mbm_total_bytes_co= nfig") Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger --- v2: Earlier Sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ But this is not related to ABMC. Sending it separate now. Removed the global resctrl_max_evt_bitmask. Added event_mask as part of the resource. --- arch/x86/kernel/cpu/resctrl/internal.h | 5 ++--- arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 18 ++++++++++-------- 3 files changed, 18 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index d2979748fae4..3e2f505614d8 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -50,9 +50,6 @@ /* Dirty Victims to All Types of Memory */ #define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) =20 -/* Max event bits supported */ -#define MAX_EVT_CONFIG_BITS GENMASK(6, 0) - struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -394,6 +391,7 @@ struct rdt_parse_data { * @msr_update: Function pointer to update QOS MSRs * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. + * @event_mask: Max supported event bitmask. * @cdp_enabled: CDP state of this resource * * Members of this structure are either private to the architecture @@ -408,6 +406,7 @@ struct rdt_hw_resource { struct rdt_resource *r); unsigned int mon_scale; unsigned int mbm_width; + unsigned int event_mask; bool cdp_enabled; }; =20 diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index f136ac046851..30bf919edfda 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -813,6 +813,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *= r) return ret; =20 if (rdt_cpu_has(X86_FEATURE_BMEC)) { + u32 eax, ebx, ecx, edx; + + /* Detect list of bandwidth sources that can be tracked */ + cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx); + hw_res->event_mask =3D ecx; + if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable =3D true; mbm_config_rftype_init("mbm_total_bytes_config"); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 69a1de92384a..8a1e9fdab974 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1537,17 +1537,14 @@ static void mon_event_config_read(void *info) { struct mon_config_info *mon_info =3D info; unsigned int index; - u64 msrval; + u32 h; =20 index =3D mon_event_config_index_get(mon_info->evtid); if (index =3D=3D INVALID_CONFIG_INDEX) { pr_warn_once("Invalid event id %d\n", mon_info->evtid); return; } - rdmsrl(MSR_IA32_EVT_CFG_BASE + index, msrval); - - /* Report only the valid event configuration bits */ - mon_info->mon_config =3D msrval & MAX_EVT_CONFIG_BITS; + rdmsr(MSR_IA32_EVT_CFG_BASE + index, mon_info->mon_config, h); } =20 static void mondata_config_read(struct rdt_domain *d, struct mon_config_in= fo *mon_info) @@ -1557,6 +1554,7 @@ static void mondata_config_read(struct rdt_domain *d,= struct mon_config_info *mo =20 static int mbm_config_show(struct seq_file *s, struct rdt_resource *r, u32= evtid) { + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); struct mon_config_info mon_info =3D {0}; struct rdt_domain *dom; bool sep =3D false; @@ -1571,7 +1569,9 @@ static int mbm_config_show(struct seq_file *s, struct= rdt_resource *r, u32 evtid mon_info.evtid =3D evtid; mondata_config_read(dom, &mon_info); =20 - seq_printf(s, "%d=3D0x%02x", dom->id, mon_info.mon_config); + /* Report only the valid event configuration bits */ + seq_printf(s, "%d=3D0x%02x", dom->id, + mon_info.mon_config & hw_res->event_mask); sep =3D true; } seq_puts(s, "\n"); @@ -1617,12 +1617,14 @@ static void mon_event_config_write(void *info) static int mbm_config_write_domain(struct rdt_resource *r, struct rdt_domain *d, u32 evtid, u32 val) { + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); struct mon_config_info mon_info =3D {0}; int ret =3D 0; =20 /* mon_config cannot be more than the supported set of events */ - if (val > MAX_EVT_CONFIG_BITS) { - rdt_last_cmd_puts("Invalid event configuration\n"); + if ((val & hw_res->event_mask) !=3D val) { + rdt_last_cmd_printf("Invalid input: The maximum valid bitmask is 0x%02x\= n", + hw_res->event_mask); return -EINVAL; } =20 From nobody Mon Dec 29 04:18:10 2025 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 042FE1B7E0; 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Mon, 15 Jan 2024 16:52:50 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v5 2/2] x86/resctrl: Read supported bandwidth sources using CPUID command Date: Mon, 15 Jan 2024 16:52:28 -0600 Message-ID: <669896fa512c7451319fa5ca2fdb6f7e015b5635.1705359148.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA51:EE_|DS0PR12MB6488:EE_ X-MS-Office365-Filtering-Correlation-Id: 14630462-b43c-4552-33f0-08dc161cb43e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2024 22:52:51.8013 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 14630462-b43c-4552-33f0-08dc161cb43e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA51.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6488 Content-Type: text/plain; charset="utf-8" If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured. The maximum supported bandwidth bitmask can be determined by following CPUID command. CPUID_Fn80000020_ECX_x03 [Platform QoS Monitoring Bandwidth Event Configuration] Read-only. Reset: 0000_007Fh. Bits Description 31:7 Reserved 6:0 Identifies the bandwidth sources that can be tracked. The bandwidth sources can change with the processor generations. Read the supported bandwidth sources using the CPUID command. While at it, move the mask checking to mon_config_write() before iterating over all the domains. Also, print the valid bitmask when the user tries to configure invalid event configuration value. The CPUID details are documented in the PPR listed below [1]. [1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model 11h B1 - 55901 Rev 0.25. Fixes: dc2a3e857981 ("x86/resctrl: Add interface to read mbm_total_bytes_co= nfig") Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Reviewed-by: Reinette Chatre --- v5: Revised the text in mon_config_write when user tries invalid config. Few other comment update. v4: Minor text changes and re-order of commit tags. Moved the mask check to mon_config_write() before iterating over all the domains. v3: Changed the event_mask name to mbm_cfg_mask. Added comments about the f= ield. Reverted the masking of event configuration to original code. Few minor comment changes. v2: Earlier sent as a part of ABMC feature. https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com/ But this is not related to ABMC. Sending it separate now. Removed the global resctrl_max_evt_bitmask. Added event_mask as part of the resource. --- arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 14 ++++++++------ 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index d2979748fae4..e3dc35a00a19 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -394,6 +394,8 @@ struct rdt_parse_data { * @msr_update: Function pointer to update QOS MSRs * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. + * @mbm_cfg_mask: Bandwidth sources that can be tracked when Bandwidth + * Monitoring Event Configuration (BMEC) is supported. * @cdp_enabled: CDP state of this resource * * Members of this structure are either private to the architecture @@ -408,6 +410,7 @@ struct rdt_hw_resource { struct rdt_resource *r); unsigned int mon_scale; unsigned int mbm_width; + unsigned int mbm_cfg_mask; bool cdp_enabled; }; =20 diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index f136ac046851..acca577e2b06 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -813,6 +813,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *= r) return ret; =20 if (rdt_cpu_has(X86_FEATURE_BMEC)) { + u32 eax, ebx, ecx, edx; + + /* Detect list of bandwidth sources that can be tracked */ + cpuid_count(0x80000020, 3, &eax, &ebx, &ecx, &edx); + hw_res->mbm_cfg_mask =3D ecx & MAX_EVT_CONFIG_BITS; + if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable =3D true; mbm_config_rftype_init("mbm_total_bytes_config"); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 69a1de92384a..2b69e560b05f 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1620,12 +1620,6 @@ static int mbm_config_write_domain(struct rdt_resour= ce *r, struct mon_config_info mon_info =3D {0}; int ret =3D 0; =20 - /* mon_config cannot be more than the supported set of events */ - if (val > MAX_EVT_CONFIG_BITS) { - rdt_last_cmd_puts("Invalid event configuration\n"); - return -EINVAL; - } - /* * Read the current config value first. If both are the same then * no need to write it again. @@ -1663,6 +1657,7 @@ static int mbm_config_write_domain(struct rdt_resourc= e *r, =20 static int mon_config_write(struct rdt_resource *r, char *tok, u32 evtid) { + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); char *dom_str =3D NULL, *id_str; unsigned long dom_id, val; struct rdt_domain *d; @@ -1686,6 +1681,13 @@ static int mon_config_write(struct rdt_resource *r, = char *tok, u32 evtid) return -EINVAL; } =20 + /* Value from user cannot be more than the supported set of events */ + if ((val & hw_res->mbm_cfg_mask) !=3D val) { + rdt_last_cmd_printf("Invalid event configuration: max valid mask is 0x%0= 2x\n", + hw_res->mbm_cfg_mask); + return -EINVAL; + } + list_for_each_entry(d, &r->domains, list) { if (d->id =3D=3D dom_id) { ret =3D mbm_config_write_domain(r, d, evtid, val); --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8FD6FC4167B for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A0.mail.protection.outlook.com (10.167.242.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7046.17 via Frontend Transport; Fri, 1 Dec 2023 00:57:33 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Thu, 30 Nov 2023 18:57:31 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 03/15] x86/resctrl: Add support for Assignable Bandwidth Monitoring Counters (ABMC) Date: Thu, 30 Nov 2023 18:57:08 -0600 Message-ID: <20231201005720.235639-4-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A0:EE_|CYYPR12MB8870:EE_ X-MS-Office365-Filtering-Correlation-Id: e3fa0eae-ecba-4fda-8092-08dbf208806b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:33.0621 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3fa0eae-ecba-4fda-8092-08dbf208806b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8870 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" AMD hardware can support 256 or more RMIDs. However, bandwidth monitoring feature only guarantees that RMIDs currently assigned to a processor will be tracked by hardware. The counters of any other RMIDs which are no longer being tracked will be reset to zero. The MBM event counters return "Unavailable" for the RMIDs that are not active. Users can create 256 or more monitor groups. But there can be only limited number of groups that can be give guaranteed monitoring numbers. With ever changing configurations there is no way to definitely know which of these groups will be active for certain point of time. Users do not have the option to monitor a group or set of groups for certain period of time without worrying about RMID being reset in between. The ABMC feature provides an option to the user to pin (or assign) the RMID to the hardware counter and monitor the bandwidth for a longer duration. The pinned RMID will be active until the user unpins (or unassigns) it. There is no need to worry about counters being reset during this period. Additionally, the user can specify a bitmask identifying the specific bandwidth types from the given source to track with the counter. Linux resctrl subsystem provides the interface to count maximum of two memory bandwidth events per group, from a combination of available total and local events. Keeping the current interface, users can assign a maximum of 2 ABMC counters per group. User will also have the option to assign only one counter to the group. If the system runs out of assignable counters, kernel will display an error. Users need to unassign an already assigned counter to make space for new assignments. AMD hardware provides total of 32 ABMC counters when supported. The feature can be detected via CPUID_Fn80000020_EBX_x00 bit 5. Bits Description 5 ABMC (Assignable Bandwidth Monitoring Counters) The feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 2 ++ arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 149cc5d5c2ae..c9ff7e0b216f 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -315,6 +315,7 @@ #define X86_FEATURE_ZEN2 (11*32+28) /* "" CPU based on Zen2 microarchitec= ture */ #define X86_FEATURE_ZEN3 (11*32+29) /* "" CPU based on Zen3 microarchitec= ture */ #define X86_FEATURE_ZEN4 (11*32+30) /* "" CPU based on Zen4 microarchitec= ture */ +#define X86_FEATURE_ABMC (11*32+31) /* "" Assignable Bandwidth Monitoring= Counters */ =20 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index e462c1d3800a..e4e71e46dfd8 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -70,6 +70,8 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_ABMC, X86_FEATURE_CQM_MBM_TOTAL }, + { X86_FEATURE_ABMC, X86_FEATURE_CQM_MBM_LOCAL }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index 0dad49a09b7a..698f2ccb9ac1 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -47,6 +47,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_ABMC, CPUID_EBX, 5, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF57AC4167B for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:34.5172 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9a398c6c-2a5d-4729-87fa-08dbf2088149 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5739 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the command line options to enable or disable the new resctrl feature ABMC (Assignable Bandwidth Monitoring Counters). Signed-off-by: Babu Moger --- Documentation/admin-guide/kernel-parameters.txt | 2 +- Documentation/arch/x86/resctrl.rst | 1 + arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 65731b060e3f..59a9e486fbbf 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5475,7 +5475,7 @@ rdt=3D [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, abmc. E.g. to turn on cmt and turn off mba use: rdt=3Dcmt,!mba =20 diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index a6279df64a9d..d816ded93c22 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -26,6 +26,7 @@ MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_= mbm_local" MBA (Memory Bandwidth Allocation) "mba" SMBA (Slow Memory Bandwidth Allocation) "" BMEC (Bandwidth Monitoring Event Configuration) "" +ABMC (Assignable Bandwidth Monitoring Counters) "" =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D =20 Historically, new features were made visible by default in /proc/cpuinfo. = This diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 3fbae10b662d..a257017b4de5 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -678,6 +678,7 @@ enum { RDT_FLAG_MBA, RDT_FLAG_SMBA, RDT_FLAG_BMEC, + RDT_FLAG_ABMC, }; =20 #define RDT_OPT(idx, n, f) \ @@ -703,6 +704,7 @@ static struct rdt_options rdt_options[] __initdata =3D= { RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), + RDT_OPT(RDT_FLAG_ABMC, "abmc", X86_FEATURE_ABMC), }; #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) =20 --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59AFAC4167B for ; Fri, 1 Dec 2023 00:58:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376534AbjLAA5x (ORCPT ); Thu, 30 Nov 2023 19:57:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232267AbjLAA5m (ORCPT ); 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Thu, 30 Nov 2023 18:57:34 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 05/15] x86/resctrl: Detect ABMC feature details Date: Thu, 30 Nov 2023 18:57:10 -0600 Message-ID: <20231201005720.235639-6-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A4:EE_|SJ0PR12MB6878:EE_ X-MS-Office365-Filtering-Correlation-Id: 70e43324-1f87-48d1-5582-08dbf208823a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gjjdN4VkFaGuDEweVxYu2KOsxdJLw7W/vmQ24teLEY1X4Fm57WOaAidQD+O2mpnbtKa2bWKo1AtVucRDFQjemQZ5ENSGS1DKMh2QBd+vGmfVEgx62H/eAdL0vaExk2oPD1DL0znD9TV3IuFC9gktMY/I5/ty+947LZnUSkV94OC7xIW5NxwZJtMe1du686Z/BzltgZW/0ZGpj+ErqX+iPXOgDASx1QCI9SE/vs2aILbYwFmwWZB/6aNDijQl3Nza81MRuRhr/HoFqD7YazBCxivsNve/jEiQTvjmEg4S8ADcKwgdSvoRp5g6mH/tbk2c+HWlKAO+MeRtANEmh0SkAoYTatnAbU/NVqWaEgC0BOBYaX240BCwXp8FlqzftDbRp1KkEqoIHE22JbIK2legEkftLSq1vX1mNIoXXrtAn57JibAgiMmngi03K1HTz4rIHt7wujATqF2rpv3IzpSEetDRdBQ+2jTVuFf1BNb4yAmJK53xsTz23n4gMBertHWh7CoHf01LVNjZWebscO1inm8jq+Tmzt8isBGmCBOpHeQTvhk7B7FiPnK5jYK3BzJq6NQag5HzSCW6VNOdEcBW2gnCAricXJ5txCodC5cpV98fb8VYBxZ6Xc94XLjavzCvt2l6BH3vuUPVg9/4Ufzpj2WpWWlOGi3+zD7OSA8z08P7ej988C88kNdR4Vy3hiug+qFbinarfwqPFjw0z4XO2L8NI1kCuqGuTYK7rgQUVD89bGFzTUKvBukDzOMfjZMipfbQVeOoqQ4PgQL9Ejnkeg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(136003)(346002)(396003)(39860400002)(230922051799003)(82310400011)(451199024)(64100799003)(186009)(1800799012)(36840700001)(40470700004)(46966006)(356005)(81166007)(40460700003)(36860700001)(82740400003)(47076005)(316002)(41300700001)(83380400001)(2616005)(110136005)(54906003)(7696005)(70206006)(6666004)(966005)(478600001)(336012)(36756003)(426003)(1076003)(7416002)(5660300002)(2906002)(70586007)(8676002)(8936002)(26005)(16526019)(44832011)(86362001)(4326008)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:36.0953 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 70e43324-1f87-48d1-5582-08dbf208823a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6878 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" ABMC feature details are reported via CPUID Fn8000_0020_EBX_x5. Bits Description 15:0 MAX_ABMC Maximum Supported Assignable Bandwidth Monitoring Counter ID + 1 Detect the feature details and update /sys/fs/resctrl/info/L3_MON/mon_features. The feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- Documentation/arch/x86/resctrl.rst | 7 +++++++ arch/x86/kernel/cpu/resctrl/core.c | 17 +++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 2 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 3 +++ include/linux/resctrl.h | 2 ++ 5 files changed, 31 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index d816ded93c22..1293cb6cba98 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -197,6 +197,13 @@ with the following files: mbm_local_bytes mbm_local_bytes_config =20 + If the system supports Assignable Bandwidth Monitoring + Counters (ABMC), the output will have additional text. + Example:: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + abmc_capable + "mbm_total_bytes_config", "mbm_local_bytes_config": Read/write files containing the configuration for the mbm_total_bytes and mbm_local_bytes events, respectively, when the Bandwidth diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index a257017b4de5..278698a74c49 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -303,6 +303,17 @@ static void rdt_get_cdp_l2_config(void) rdt_get_cdp_config(RDT_RESOURCE_L2); } =20 +static void rdt_get_abmc_cfg(struct rdt_resource *r) +{ + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + u32 eax, ebx, ecx, edx; + + r->abmc_capable =3D true; + /* Query CPUID_Fn80000020_EBX_x05 for number of ABMC counters */ + cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); + hw_res->abmc_counters =3D (ebx & 0xFFFF) + 1; +} + static void mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resour= ce *r) { @@ -815,6 +826,12 @@ static __init bool get_rdt_alloc_resources(void) if (get_slow_mem_config()) ret =3D true; =20 + if (rdt_cpu_has(X86_FEATURE_ABMC)) { + r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + rdt_get_abmc_cfg(r); + ret =3D true; + } + return ret; } =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 524d8bec1439..0b22be85a444 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -388,6 +388,7 @@ struct rdt_parse_data { * resctrl_arch_get_num_closid() to avoid confusion * with struct resctrl_schema's property of the same name, * which has been corrected for features like CDP. + * @abmc_countes: Maximum number of ABMC counters supported * @msr_base: Base MSR address for CBMs * @msr_update: Function pointer to update QOS MSRs * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes @@ -401,6 +402,7 @@ struct rdt_parse_data { struct rdt_hw_resource { struct rdt_resource r_resctrl; u32 num_closid; + u32 abmc_counters; unsigned int msr_base; void (*msr_update) (struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 6c22718dbaa2..feeb57ee7888 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1077,6 +1077,9 @@ static int rdt_mon_features_show(struct kernfs_open_f= ile *of, seq_printf(seq, "%s_config\n", mevt->name); } =20 + if (r->abmc_capable) + seq_printf(seq, "abmc_capable\n"); + return 0; } =20 diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 66942d7fba7f..656af479a19b 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -162,6 +162,7 @@ struct resctrl_schema; * @evt_list: List of monitoring events * @fflags: flags to choose base and info files * @cdp_capable: Is the CDP feature available on this resource + * @abmc_capable: Does system capable of supporting ABMC feature? */ struct rdt_resource { int rid; @@ -182,6 +183,7 @@ struct rdt_resource { struct list_head evt_list; unsigned long fflags; bool cdp_capable; + bool abmc_capable; }; =20 /** --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D43DC4167B for ; Fri, 1 Dec 2023 00:57:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376367AbjLAA5r (ORCPT ); Thu, 30 Nov 2023 19:57:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46910 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230014AbjLAA5e (ORCPT ); Thu, 30 Nov 2023 19:57:34 -0500 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2052.outbound.protection.outlook.com [40.107.94.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DDBFE10FF; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:37.6886 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f61f6692-5dbf-493a-756e-08dbf208832d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8064 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the mount option for ABMC (Assignable Bandwidth Monitoring Counters) feature. Signed-off-by: Babu Moger --- Documentation/arch/x86/resctrl.rst | 2 ++ arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 5 +++++ 3 files changed, 8 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 1293cb6cba98..19e906f629d4 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -50,6 +50,8 @@ mount options are: "debug": Make debug files accessible. Available debug files are annotated with "Available only with debug option". +"abmc": + Enable ABMC (Assignable Bandwidth Monitoring Counters) feature. =20 L2 and L3 CDP are controlled separately. =20 diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 0b22be85a444..b8f3a0b1ca41 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -56,6 +56,7 @@ struct rdt_fs_context { bool enable_cdpl3; bool enable_mba_mbps; bool enable_debug; + bool enable_abmc; }; =20 static inline struct rdt_fs_context *rdt_fc2context(struct fs_context *fc) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index feeb57ee7888..a4328e12a8f6 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2687,6 +2687,7 @@ enum rdt_param { Opt_cdpl2, Opt_mba_mbps, Opt_debug, + Opt_abmc, nr__rdt_params }; =20 @@ -2695,6 +2696,7 @@ static const struct fs_parameter_spec rdt_fs_paramete= rs[] =3D { fsparam_flag("cdpl2", Opt_cdpl2), fsparam_flag("mba_MBps", Opt_mba_mbps), fsparam_flag("debug", Opt_debug), + fsparam_flag("abmc", Opt_abmc), {} }; =20 @@ -2723,6 +2725,9 @@ static int rdt_parse_param(struct fs_context *fc, str= uct fs_parameter *param) case Opt_debug: ctx->enable_debug =3D true; return 0; + case Opt_abmc: + ctx->enable_abmc =3D true; + return 0; } =20 return -EINVAL; --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6260FC10DCE for ; Fri, 1 Dec 2023 00:58:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376868AbjLAA6A (ORCPT ); Thu, 30 Nov 2023 19:58:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232366AbjLAA5t (ORCPT ); Thu, 30 Nov 2023 19:57:49 -0500 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2065.outbound.protection.outlook.com [40.107.93.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59FD2172C; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:39.2183 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37a322eb-2310-4d2e-de17-08dbf2088416 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8980 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Set up the system to enable or disable ABMC feature. By default, the ABMC is disabled. User needs to mount resctrl with -o abmc option to enabled the feature. ABMC is enabled by setting enabled bit(0) in MSR L3_QOS_EXT_CFG. When the state of ABMC is changed, it must be changed to the updated value on all logical processors in the QOS Domain. The ABMC feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 10 ++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 79 +++++++++++++++++++++++++- 3 files changed, 89 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index 737a52b89e64..a2086aad580c 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1123,6 +1123,7 @@ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff =20 /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index b8f3a0b1ca41..2801bc0dc132 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -50,6 +50,9 @@ /* Dirty Victims to All Types of Memory */ #define DIRTY_VICTIMS_TO_ALL_MEM BIT(6) =20 +/* ABMC ENABLE */ +#define ABMC_ENABLE BIT(0) + struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -395,6 +398,7 @@ struct rdt_parse_data { * @mon_scale: cqm counter * mon_scale =3D occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. * @cdp_enabled: CDP state of this resource + * @abmc_enabled: ABMC feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -410,6 +414,7 @@ struct rdt_hw_resource { unsigned int mon_scale; unsigned int mbm_width; bool cdp_enabled; + bool abmc_enabled; }; =20 static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resou= rce *r) @@ -455,6 +460,11 @@ static inline bool resctrl_arch_get_cdp_enabled(enum r= esctrl_res_level l) =20 int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable); =20 +static inline bool resctrl_arch_get_abmc_enabled(enum resctrl_res_level l) +{ + return rdt_resources_all[l].abmc_enabled; +} + /* * To return the common struct rdt_resource, which is contained in struct * rdt_hw_resource, walk the resctrl member of struct rdt_hw_resource. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index a4328e12a8f6..7f6ed903ba17 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2365,6 +2365,72 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_le= vel l, bool enable) return 0; } =20 +static void resctrl_abmc_msrwrite(void *arg) +{ + bool *enable =3D arg; + u64 msrval; + + rdmsrl(MSR_IA32_L3_QOS_EXT_CFG, msrval); + + if (*enable) + msrval |=3D ABMC_ENABLE; + else + msrval &=3D ~ABMC_ENABLE; + + wrmsrl(MSR_IA32_L3_QOS_EXT_CFG, msrval); +} + +static int resctrl_abmc_setup(enum resctrl_res_level l, bool enable) +{ + struct rdt_resource *r =3D &rdt_resources_all[l].r_resctrl; + struct rdt_domain *d; + + /* Update QOS_CFG MSR on all the CPUs in cpu_mask */ + list_for_each_entry(d, &r->domains, list) + on_each_cpu_mask(&d->cpu_mask, resctrl_abmc_msrwrite, &enable, 1); + + return 0; +} + +static int resctrl_abmc_enable(enum resctrl_res_level l) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[l]; + int ret =3D 0; + + if (!hw_res->abmc_enabled) { + ret =3D resctrl_abmc_setup(l, true); + if (!ret) + hw_res->abmc_enabled =3D true; + } + + return ret; +} + +static void resctrl_abmc_disable(enum resctrl_res_level l) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[l]; + + if (hw_res->abmc_enabled) { + resctrl_abmc_setup(l, false); + hw_res->abmc_enabled =3D false; + } +} + +int resctrl_arch_set_abmc_enabled(enum resctrl_res_level l, bool enable) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[l]; + + if (!hw_res->r_resctrl.abmc_capable) + return -EINVAL; + + if (enable) + return resctrl_abmc_enable(l); + + resctrl_abmc_disable(l); + + return 0; +} + /* * We don't allow rdtgroup directories to be created anywhere * except the root directory. Thus when looking for the rdtgroup @@ -2449,7 +2515,7 @@ static void rdt_disable_ctx(void) resctrl_arch_set_cdp_enabled(RDT_RESOURCE_L3, false); resctrl_arch_set_cdp_enabled(RDT_RESOURCE_L2, false); set_mba_sc(false); - + resctrl_arch_set_abmc_enabled(RDT_RESOURCE_L3, false); resctrl_debug =3D false; } =20 @@ -2475,11 +2541,19 @@ static int rdt_enable_ctx(struct rdt_fs_context *ct= x) goto out_cdpl3; } =20 + if (ctx->enable_abmc) { + ret =3D resctrl_arch_set_abmc_enabled(RDT_RESOURCE_L3, true); + if (ret) + goto out_mba_mbps; + } + if (ctx->enable_debug) resctrl_debug =3D true; =20 return 0; =20 +out_mba_mbps: + set_mba_sc(false); out_cdpl3: resctrl_arch_set_cdp_enabled(RDT_RESOURCE_L3, false); out_cdpl2: @@ -3802,6 +3876,9 @@ static int rdtgroup_show_options(struct seq_file *seq= , struct kernfs_root *kf) if (resctrl_debug) seq_puts(seq, ",debug"); =20 + if (resctrl_arch_get_abmc_enabled(RDT_RESOURCE_L3)) + seq_puts(seq, ",abmc"); + return 0; } =20 --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E8AD8C4167B for ; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:40.7468 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9e9749e6-cce5-40b4-b6af-08dbf20884fd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002529F.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6906 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ABMC feature provides an option to the user to pin (or assign) the RMID to the hardware counter and monitor the bandwidth for a longer duration. There are only a limited number of hardware counters. Provide the interface to display the number of ABMC counters supported. Signed-off-by: Babu Moger --- Documentation/arch/x86/resctrl.rst | 4 ++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 29 +++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 19e906f629d4..87aa8eec71b7 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -266,6 +266,10 @@ with the following files: # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=3D0x30;1=3D0x30;3=3D0x15;4=3D0x15 =20 +"abmc_counters": + Available when ABMC feature is enabled. The number of ABMC counters + available for assignment. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 7f6ed903ba17..897707694cc8 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -811,6 +811,17 @@ static int rdtgroup_rmid_show(struct kernfs_open_file = *of, return ret; } =20 +static int rdtgroup_abmc_counters_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r =3D of->kn->parent->priv; + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); + + seq_printf(s, "%d\n", hw_res->abmc_counters); + + return 0; +} + #ifdef CONFIG_PROC_CPU_RESCTRL =20 /* @@ -1861,6 +1872,12 @@ static struct rftype res_common_files[] =3D { .seq_show =3D mbm_local_bytes_config_show, .write =3D mbm_local_bytes_config_write, }, + { + .name =3D "abmc_counters", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D rdtgroup_abmc_counters_show, + }, { .name =3D "cpus", .mode =3D 0644, @@ -2419,12 +2436,22 @@ static void resctrl_abmc_disable(enum resctrl_res_l= evel l) int resctrl_arch_set_abmc_enabled(enum resctrl_res_level l, bool enable) { struct rdt_hw_resource *hw_res =3D &rdt_resources_all[l]; + struct rftype *rft; =20 if (!hw_res->r_resctrl.abmc_capable) return -EINVAL; =20 - if (enable) + if (enable) { + rft =3D rdtgroup_get_rftype_by_name("abmc_counters"); + if (rft) + rft->fflags =3D RFTYPE_MON_INFO; + return resctrl_abmc_enable(l); + } + + rft =3D rdtgroup_get_rftype_by_name("abmc_counters"); + if (rft) + rft->fflags &=3D ~RFTYPE_MON_INFO; =20 resctrl_abmc_disable(l); =20 --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6C45C4167B for ; Fri, 1 Dec 2023 00:58:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229623AbjLAA6J (ORCPT ); Thu, 30 Nov 2023 19:58:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229952AbjLAA5t (ORCPT ); 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Thu, 30 Nov 2023 18:57:40 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 09/15] x86/resctrl: Add interface to display monitor state of the group Date: Thu, 30 Nov 2023 18:57:14 -0600 Message-ID: <20231201005720.235639-10-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|CY8PR12MB7705:EE_ X-MS-Office365-Filtering-Correlation-Id: f6343044-e6cf-4553-6e25-08dbf20885f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 9gnhT7lQADbFNxsgQl2kk8kvevspRSs8kkrHWbiFHrIEqdCW/0tZySSH6TlmdyqpuoKoHzCum4AvhnlOqWU50QrZ6FGgiHTWVIFMpnrhldSremlhTGcyDPwVMels/NtU7Aabu7SuVZcroXwnScdaMYZDtXbXkTVxyR7EfzmxjuTzkGduJE1opNbos93ryOgC6ajoaiwX9M5bKUL7uI6fyKVnE4dKPvZBQkN7D/rlU2UqMVRAOtxK+mvZm7g1E3yTrb8kQrlaNs7iWB16RhEwBZpZhI2wvu+oLXxBzPECbY/2Z8/ZSB7RBTbNsPAmF14u4BHUqhaPRdyw/eHGJoTLMC+q4oVR9ocVYSMq/r2FHT36anGdaPTthuuWpxzy3+ub1EPM5me4NS8PUkSgB/SwhML0vqVkMnwv/hguQkaRFMv0OvL9Ef4QbhfBtZ2ck/PbLlgrXCcdsHttnfp7KsegF7BpxIi8btskUEsX6Xbd9bXG8rpg3rRuIClztv7EIZJtJ3XsJnBLE6ntPOLoGIBamwAJwZ4CEMqVb0woPMTaGIdgnak/MRQAjA+zCeUSEqOyXp+4ytnEqyY+h3WJzg4O6BhMazqsSJBg0V/JVcbLxPR8nzIAScCh/oe+Q+2qUADiBA+0O9Cg89WuI0ibgGjgKKO/iwVBi1NwJdioQtGsqaUC2+uf4xQWujhoxjUKtfWoexsEterflSX5yRhR53L+674skspqhbE5Sm3yZFl1dURMqClUN2Tj3G7MoqpI+6i62q2p3eE4YJ6rmBUWiGGyCw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(346002)(376002)(230922051799003)(1800799012)(186009)(64100799003)(451199024)(82310400011)(46966006)(40470700004)(36840700001)(86362001)(40460700003)(83380400001)(26005)(1076003)(6666004)(7696005)(2616005)(47076005)(426003)(36860700001)(478600001)(44832011)(7416002)(8936002)(5660300002)(8676002)(41300700001)(336012)(2906002)(110136005)(16526019)(4326008)(316002)(81166007)(70206006)(70586007)(54906003)(36756003)(356005)(82740400003)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:42.3677 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6343044-e6cf-4553-6e25-08dbf20885f7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7705 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The ABMC feature provides an option to the user to pin (or assign) the RMID to the hardware counter and monitor the bandwidth for the longer duration. The RMID will be active until user unpins (unassigns) the RMID. Add a new field monitor_state in resctrl group interface to display the assignment state of the group. This field is available when resctrl interface is mounted with "-o abmc". By default the monitor_state is initialized to unassigned state. $cat /sys/fs/resctrl/monitor_state total=3Dunassign;local=3Dunassign Signed-off-by: Babu Moger --- Documentation/arch/x86/resctrl.rst | 20 ++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 8 ++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 36 ++++++++++++++++++++++++++ 3 files changed, 64 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 87aa8eec71b7..d3df7d467eec 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -390,6 +390,26 @@ When monitoring is enabled all MON groups will also co= ntain: the sum for all tasks in the CTRL_MON group and all tasks in MON groups. Please see example section for more details on usage. =20 +"monitor_state": + Available when ABMC feature is enabled. ABMC feature provides an + option to the user to pin (or assign) the RMID to hardware counter + and monitor the bandwidth for the longer duration. The RMID will + be active until user unpins (unassigns) it manually. Each group + will have two events that are assignable. By default, the events + are unassigned. Index 0 holds the monitor_state for MBM total bytes. + Index 1 holds the monitor_state for MBM local bytes. + + Example:: + + # cat /sys/fs/resctrl/monitor_state + total=3Dunassign;local=3Dunassign + + When the events are assigned, the output will look like below. + Example:: + + # cat /sys/fs/resctrl/monitor_state + total=3Dassign;local=3Dassign + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index 2801bc0dc132..bc36acd152be 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -53,6 +53,12 @@ /* ABMC ENABLE */ #define ABMC_ENABLE BIT(0) =20 +/* + * monitor group's state when ABMC is enabled + */ +#define TOTAL_ASSIGN BIT(0) +#define LOCAL_ASSIGN BIT(1) + struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -161,12 +167,14 @@ enum rdtgrp_mode { * @parent: parent rdtgrp * @crdtgrp_list: child rdtgroup node list * @rmid: rmid for this rdtgroup + * @monitor_state: ABMC state of the group */ struct mongroup { struct kernfs_node *mon_data_kn; struct rdtgroup *parent; struct list_head crdtgrp_list; u32 rmid; + u32 monitor_state; }; =20 /** diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 897707694cc8..edb679b22b7b 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -779,6 +779,26 @@ static int rdtgroup_tasks_show(struct kernfs_open_file= *of, return ret; } =20 +static int rdtgroup_monitor_state_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdtgroup *rdtgrp; + int ret =3D 0; + + rdtgrp =3D rdtgroup_kn_lock_live(of->kn); + if (rdtgrp) + seq_printf(s, "total=3D%s;local=3D%s\n", + rdtgrp->mon.monitor_state & TOTAL_ASSIGN ? + "assign" : "unassign", + rdtgrp->mon.monitor_state & LOCAL_ASSIGN ? + "assign" : "unassign"); + else + ret =3D -ENOENT; + rdtgroup_kn_unlock(of->kn); + + return ret; +} + static int rdtgroup_closid_show(struct kernfs_open_file *of, struct seq_file *s, void *v) { @@ -1895,6 +1915,12 @@ static struct rftype res_common_files[] =3D { .flags =3D RFTYPE_FLAGS_CPUS_LIST, .fflags =3D RFTYPE_BASE, }, + { + .name =3D "monitor_state", + .mode =3D 0444, + .kf_ops =3D &rdtgroup_kf_single_ops, + .seq_show =3D rdtgroup_monitor_state_show, + }, { .name =3D "tasks", .mode =3D 0644, @@ -2446,6 +2472,12 @@ int resctrl_arch_set_abmc_enabled(enum resctrl_res_l= evel l, bool enable) if (rft) rft->fflags =3D RFTYPE_MON_INFO; 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Thu, 30 Nov 2023 18:57:42 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 10/15] x86/resctrl: Initialize ABMC counters bitmap Date: Thu, 30 Nov 2023 18:57:15 -0600 Message-ID: <20231201005720.235639-11-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|CH3PR12MB9282:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a0c02a4-1594-44d9-1ec0-08dbf20886d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: UavEWFiWEDUFi6IWp5nvohx5ggflfljacyyOKZzYJf4/KAmBxIwQT1KtVRi95KEgUWLolDqDa7lDGUIJszukATWHhtDInZLvQTeZKSfqgnXAZSvJy5T+ZLRRXlwy7iUNjahvvtScSkJt8TXjP5EGpz4o32mEzpNDUCOTZk8i0qPRPLERp2h2Zk28RyUMVx2pbeMITnI9kXJnTYobK3Yl0RePlQRMoHcqIMRCn0T/bgFrjEYRnQTxjeS9hnVmlJ43Yve3eu3o3TCeNRPDzsVbzS630hZRV+ZPQYRV2My9oQ6U0ypA9lyuKhw3WIVVJodT0kPNAPdeNOe/7vnEh0MCo/pckh58PM/kxyQx7WLLMyaWwZNeStsKZJmyOGiuhTFHih48L5FDuNcpGRcM5UC8Wh0W1ouMwIPKwyVwaXyVeeM/zicL/zdDejgHoX5FLtAeBuXXmsSclX8OSJvcsQBMRtRZgiW4kIIX5XSPWOCJ3Tg7iYKypC3F0NcJB0AdJU1Ux02u12vcnIJTES3YM4nanySXkmXqQX9OK3LVyagaK7bYlFC44o3dB+Lw6PX2DGIIypKoZ6vAhKGpeQPVfP5XgiE3wnmQFDEuVUJBw5+ovRHQ60vbi8UvBDeR94W7rzdlukw0f597km6y6D6gwTIHuIp3u+Z6oLSCvDq91Vy6K1oI3nYiXh28jIkIZm+LrnVQY4qOGMZT7VYK5pRh13fUW4wvWviFPiStBanX1fowKZsvOR/rkDxPMpP/GYD4f80+vy243i2FmWrHhvczem/iQg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(346002)(376002)(136003)(230922051799003)(64100799003)(451199024)(1800799012)(82310400011)(186009)(46966006)(40470700004)(36840700001)(26005)(40480700001)(40460700003)(36860700001)(81166007)(356005)(82740400003)(47076005)(7416002)(2906002)(5660300002)(336012)(6666004)(83380400001)(426003)(16526019)(1076003)(2616005)(7696005)(70206006)(86362001)(41300700001)(70586007)(478600001)(36756003)(4326008)(54906003)(8676002)(110136005)(44832011)(8936002)(316002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:43.8402 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0a0c02a4-1594-44d9-1ec0-08dbf20886d8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9282 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" AMD Hardware provides 32 ABMC(Bandwidth Monitoring Event Configuration) counters when supported. These hardware counters are used to assign (or pin) the RMID to the group. Introduce the bitmap abmc_free_map to allocate and free counters. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index edb679b22b7b..f72d6d8c12df 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -164,6 +164,22 @@ static bool closid_allocated(unsigned int closid) return (closid_free_map & (1 << closid)) =3D=3D 0; } =20 +static u64 abmc_free_map; +static u32 abmc_free_map_len; + +static void abmc_counters_init(void) +{ + struct rdt_hw_resource *hw_res =3D &rdt_resources_all[RDT_RESOURCE_L3]; + + if (hw_res->abmc_counters > 64) { + hw_res->abmc_counters =3D 64; + WARN(1, "Cannot support more than 64 abmc counters\n"); + } + + abmc_free_map =3D BIT_MASK(hw_res->abmc_counters) - 1; + abmc_free_map_len =3D hw_res->abmc_counters; +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group @@ -2715,6 +2731,7 @@ static int rdt_get_tree(struct fs_context *fc) { struct rdt_fs_context *ctx =3D rdt_fc2context(fc); unsigned long flags =3D RFTYPE_CTRL_BASE; + struct rdt_hw_resource *hw_res; struct rdt_domain *dom; struct rdt_resource *r; int ret; @@ -2745,6 +2762,12 @@ static int rdt_get_tree(struct fs_context *fc) =20 closid_init(); =20 + r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + hw_res =3D resctrl_to_arch_res(r); + + if (r->abmc_capable && hw_res->abmc_enabled) + abmc_counters_init(); + if (rdt_mon_capable) flags |=3D RFTYPE_MON; =20 @@ -2789,7 +2812,6 @@ static int rdt_get_tree(struct fs_context *fc) static_branch_enable_cpuslocked(&rdt_enable_key); =20 if (is_mbm_enabled()) { - r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; list_for_each_entry(dom, &r->domains, list) mbm_setup_overflow_handler(dom, MBM_OVERFLOW_INTERVAL); } --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92994C4167B for ; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|CY8PR12MB7435:EE_ X-MS-Office365-Filtering-Correlation-Id: b35c1e24-f1cb-4361-262b-08dbf20887e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: D2PF84T2vcfUvMASw3+F+ZXu6IOBI0m5kj43/fUxx/usp41RjAfyzkPk1Vzn8tUc+pHKhVwFHWi+RzwiktyLsP0Ux7bSKsFGWUy5+Ny+Eu7M4aOVebb4cb4KHW8i3fM3YD8fRJmfCwTG7eJTN9rn7XK+NnEuTreibDsXlxDZZnIVoPhZxvRGETsmddPo7JxwvI+YNQypO0GNzEbvKchfw8jIEZTTDbsGmcBfzk9MrUzdRRgDNidTA1ocirrQBYDR9EHDB3d2aPCZBPNOGkIpHcPhxbFZwsBWR9q+vjT9KnzOs9uD3pXLGD1QUSMXBI5wX6H6NJOAF1d3WW7kfIYgSUK7MlahVioO5+rPfyDfa7vdC/6Auvj/F8UhrKkhtMakcvwO+au2CNmAqBOAKLyPgyeUeYcqvQDGr4cpj3NlNm8HPtUOym5gzqGtSgjj5N3RIcefyuCEN9Q5WU+ZKVK2gb/SrBTCAFxG/LJvppU6fJPH4V718riFku9xfClo8SMZRVr69aNCi25upRqSlkzItsCX6IgL4VG+Jdscs711n+6SwumUCcqWdm2CJELYoPLnCh+l3R4e3fpklibgsMZZpcfMfvLWJQChEWZSlm0wPTKXBUlKny7I7oc4kfxvs8qsgX0FHh2KTpfy+txMpGrxWbLEyzMnddYVP69DRU57RO6vuA4/pcL0E9BoxcMPe3bg5HQTGloRRKWJaz9TulqFje0f3XUWSyfCyJSwML5ormQRIags+/azeGWgoEebBSopRUBYxz2Wh8xBGT8PwvD3OA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(376002)(39860400002)(136003)(346002)(230922051799003)(1800799012)(82310400011)(64100799003)(186009)(451199024)(36840700001)(40470700004)(46966006)(82740400003)(36756003)(7696005)(6666004)(2616005)(86362001)(26005)(1076003)(70206006)(110136005)(316002)(426003)(54906003)(40480700001)(70586007)(16526019)(336012)(4326008)(8936002)(83380400001)(8676002)(966005)(47076005)(44832011)(36860700001)(7416002)(5660300002)(478600001)(356005)(81166007)(2906002)(40460700003)(41300700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:45.5902 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b35c1e24-f1cb-4361-262b-08dbf20887e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7435 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org ABMC(Bandwidth Monitoring Event Configuration) counters can be configured by writing to L3_QOS_ABMC_CFG MSR. When ABMC is enabled, the user can configure a counter by writing to L3_QOS_ABMC_CFG setting the CfgEn field while specifying the Bandwidth Source, Bandwidth Types, and Counter Identifier. Add the MSR definition and individual field definitions. MSR L3_QOS_ABMC_CFG (C000_03FDh) definitions. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Bits Mnemonic Description Access Type Reset Value =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 63 CfgEn Configuration Enable R/W 0 62 CtrEn Counter Enable R/W 0 61:53 =E2=80=93 Reserved MBZ 0 52:48 CtrID Counter Identifier R/W 0 47 IsCOS BwSrc field is a COS R/W 0 (not an RMID) R/W 0 46:44 =E2=80=93 Reserved MBZ 0 43:32 BwSrc Bandwidth Source R/W 0 (RMID or COS) 31:0 BwType Bandwidth types to R/W 0 track for this counter =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-in= dex.h index a2086aad580c..ec85f6733eda 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1124,6 +1124,7 @@ #define MSR_IA32_SMBA_BW_BASE 0xc0000280 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff +#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd =20 /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index bc36acd152be..ca4b551dc808 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -59,6 +59,8 @@ #define TOTAL_ASSIGN BIT(0) #define LOCAL_ASSIGN BIT(1) =20 +#define ABMC_MAX_PER_GROUP 2 + struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -168,6 +170,7 @@ enum rdtgrp_mode { * @crdtgrp_list: child rdtgroup node list * @rmid: rmid for this rdtgroup * @monitor_state: ABMC state of the group + * @abmc_ctr_id: ABMC counterids assigned to this group */ struct mongroup { struct kernfs_node *mon_data_kn; @@ -175,6 +178,7 @@ struct mongroup { struct list_head crdtgrp_list; u32 rmid; u32 monitor_state; + u32 abmc_ctr_id[ABMC_MAX_PER_GROUP]; }; =20 /** @@ -527,6 +531,24 @@ union cpuid_0x10_x_edx { unsigned int full; }; =20 +/* + * L3_QOS_ABMC_CFG MSR details. ABMC counters can be configured + * by writing to L3_QOS_ABMC_CFG. + */ +union l3_qos_abmc_cfg { + struct { + unsigned long bw_type :32, + bw_src :12, + rsvrd1 : 3, + is_cos : 1, + ctr_id : 5, + rsvrd : 9, + ctr_en : 1, + cfg_en : 1; + } split; + unsigned long full; +}; + void rdt_last_cmd_clear(void); void rdt_last_cmd_puts(const char *s); __printf(1, 2) --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B1074C4167B for ; Fri, 1 Dec 2023 00:58:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232274AbjLAA6c (ORCPT ); Thu, 30 Nov 2023 19:58:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36742 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376736AbjLAA5z (ORCPT ); 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:47.6106 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8d5040c0-431a-440f-6d24-08dbf2088917 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5779 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured. The event configuration is domain specific. ABMC (Assignable Bandwidth Monitoring Counters) feature needs the event configuration information to assign the hardware counters. Save the event configuration information in the rdt_hw_domain, so it can be used for ABMC assignment. Signed-off-by: Babu Moger --- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ arch/x86/kernel/cpu/resctrl/monitor.c | 11 +++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 11 +++++++++++ 4 files changed, 27 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct= rl/core.c index 278698a74c49..5ac9991e81bc 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -556,6 +556,8 @@ static void domain_add_cpu(int cpu, struct rdt_resource= *r) return; } =20 + arch_domain_mbm_evt_config(hw_dom); + list_add_tail(&d->list, add_pos); =20 err =3D resctrl_online_domain(r, d); diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r= esctrl/internal.h index ca4b551dc808..bc1756a596f0 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -346,6 +346,8 @@ struct rdt_hw_domain { u32 *ctrl_val; struct arch_mbm_state *arch_mbm_total; struct arch_mbm_state *arch_mbm_local; + u32 mbm_total_cfg; + u32 mbm_local_cfg; }; =20 static inline struct rdt_hw_domain *resctrl_to_arch_dom(struct rdt_domain = *r) @@ -605,5 +607,6 @@ void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void __init thread_throttle_mode_init(void); void __init mbm_config_rftype_init(const char *config); void rdt_staged_configs_clear(void); +void arch_domain_mbm_evt_config(struct rdt_hw_domain *hw_dom); =20 #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/re= sctrl/monitor.c index c611b16ba259..34d3b0c7f2c6 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -854,3 +854,14 @@ void __init intel_rdt_mbm_apply_quirk(void) mbm_cf_rmidthreshold =3D mbm_cf_table[cf_index].rmidthreshold; mbm_cf =3D mbm_cf_table[cf_index].cf; } + +void arch_domain_mbm_evt_config(struct rdt_hw_domain *hw_dom) +{ + if (mbm_total_event.configurable) + hw_dom->mbm_total_cfg =3D resctrl_max_evt_bitmask; + + if (mbm_local_event.configurable) + hw_dom->mbm_local_cfg =3D READS_TO_LOCAL_MEM | + NON_TEMP_WRITE_TO_LOCAL_MEM | + READS_TO_LOCAL_S_MEM; +} diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index f72d6d8c12df..047aea628e2e 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1667,6 +1667,7 @@ static void mon_event_config_write(void *info) static int mbm_config_write_domain(struct rdt_resource *r, struct rdt_domain *d, u32 evtid, u32 val) { + struct rdt_hw_domain *hw_dom =3D resctrl_to_arch_dom(d); struct mon_config_info mon_info =3D {0}; int ret =3D 0; =20 @@ -1696,6 +1697,16 @@ static int mbm_config_write_domain(struct rdt_resour= ce *r, smp_call_function_any(&d->cpu_mask, mon_event_config_write, &mon_info, 1); =20 + /* + * Update event config value in the domain when user changes it. + */ + if (evtid =3D=3D QOS_L3_MBM_TOTAL_EVENT_ID) + hw_dom->mbm_total_cfg =3D val; + else if (evtid =3D=3D QOS_L3_MBM_LOCAL_EVENT_ID) + hw_dom->mbm_local_cfg =3D val; + else + goto out; + /* * When an Event Configuration is changed, the bandwidth counters * for all RMIDs and Events will be cleared by the hardware. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000252A3.mail.protection.outlook.com (10.167.242.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7046.17 via Frontend Transport; Fri, 1 Dec 2023 00:57:49 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Thu, 30 Nov 2023 18:57:46 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 13/15] x86/resctrl: Add the interface to assign a ABMC counter Date: Thu, 30 Nov 2023 18:57:18 -0600 Message-ID: <20231201005720.235639-14-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A3:EE_|CY8PR12MB8214:EE_ X-MS-Office365-Filtering-Correlation-Id: 26528513-e21e-41f9-fd28-08dbf2088a4a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:49.6262 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26528513-e21e-41f9-fd28-08dbf2088a4a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8214 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With the support of ABMC (Assignable Bandwidth Monitoring Counters) feature, the user has the option to pin (or assign) or unpin (or unassign) the RMID to hardware counter and monitor the bandwidth for the longer duration. Provide the interface to pin (or assign) the counter to the group. The ABMC feature implements a pair of MSRs, L3_QOS_ABMC_CFG (MSR C000_03FDh) and L3_QOS_ABMC_DSC (MSR C000_3FEh). Each logical processor implements a separate copy of these registers. Attempts to read or write these MSRs when ABMC is not enabled will result in a #GP(0) exception. Individual assignable bandwidth counters are configured by writing to L3_QOS_ABMC_CFG MSR and specifying the Counter ID, Bandwidth Source, and Bandwidth Types. Reading L3_QOS_ABMC_DSC returns the configuration of the counter specified by L3_QOS_ABMC_CFG [CtrID]. The feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- Documentation/arch/x86/resctrl.rst | 7 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 152 ++++++++++++++++++++++++- 2 files changed, 158 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index d3df7d467eec..65306e7d01b6 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -410,6 +410,13 @@ When monitoring is enabled all MON groups will also co= ntain: # cat /sys/fs/resctrl/monitor_state total=3Dassign;local=3Dassign =20 + The user needs to pin (or assign) RMID to read the MBM event in + ABMC mode. Each event can be assigned or unassigned separately. + Example:: + + # echo total=3Dassign > /sys/fs/resctrl/monitor_state + # echo total=3Dassign;local=3Dassign > /sys/fs/resctrl/monitor_state + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 047aea628e2e..671ff732992c 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -180,6 +180,18 @@ static void abmc_counters_init(void) abmc_free_map_len =3D hw_res->abmc_counters; } =20 +static int abmc_counters_alloc(void) +{ + u32 counterid =3D ffs(abmc_free_map); + + if (counterid =3D=3D 0) + return -ENOSPC; + counterid--; + abmc_free_map &=3D ~(1 << counterid); + + return counterid; +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group @@ -1583,6 +1595,143 @@ static inline unsigned int mon_event_config_index_g= et(u32 evtid) } } =20 +static void rdtgroup_abmc_msrwrite(void *info) +{ + u64 *msrval =3D info; + + wrmsrl(MSR_IA32_L3_QOS_ABMC_CFG, *msrval); +} + +static void rdtgroup_abmc_domain(struct rdt_domain *d, + struct rdtgroup *rdtgrp, + u32 evtid, int index, bool assign) +{ + struct rdt_hw_domain *hw_dom =3D resctrl_to_arch_dom(d); + union l3_qos_abmc_cfg abmc_cfg =3D { 0 }; + struct arch_mbm_state *arch_mbm; + + abmc_cfg.split.cfg_en =3D 1; + abmc_cfg.split.ctr_en =3D assign ? 1 : 0; + abmc_cfg.split.ctr_id =3D rdtgrp->mon.abmc_ctr_id[index]; + abmc_cfg.split.bw_src =3D rdtgrp->mon.rmid; + + /* + * Read the event configuration from the domain and pass it as + * bw_type. + */ + if (evtid =3D=3D QOS_L3_MBM_TOTAL_EVENT_ID) { + abmc_cfg.split.bw_type =3D hw_dom->mbm_total_cfg; + arch_mbm =3D &hw_dom->arch_mbm_total[rdtgrp->mon.rmid]; + } else { + abmc_cfg.split.bw_type =3D hw_dom->mbm_local_cfg; + arch_mbm =3D &hw_dom->arch_mbm_local[rdtgrp->mon.rmid]; + } + + smp_call_function_any(&d->cpu_mask, rdtgroup_abmc_msrwrite, &abmc_cfg, 1); + + /* Reset the internal counters */ + if (arch_mbm) + memset(arch_mbm, 0, sizeof(struct arch_mbm_state)); +} + +static ssize_t rdtgroup_assign_abmc(struct rdtgroup *rdtgrp, + struct rdt_resource *r, + u32 evtid, int mon_state) +{ + int counterid =3D 0, index; + struct rdt_domain *d; + + if (rdtgrp->mon.monitor_state & mon_state) { + rdt_last_cmd_puts("ABMC counter is assigned already\n"); + return 0; + } + + index =3D mon_event_config_index_get(evtid); + if (index =3D=3D INVALID_CONFIG_INDEX) { + pr_warn_once("Invalid event id %d\n", evtid); + return -EINVAL; + } + + /* + * Allocate a new counter and update domains + */ + counterid =3D abmc_counters_alloc(); + if (counterid < 0) { + rdt_last_cmd_puts("Out of ABMC counters\n"); + return -ENOSPC; + } + + rdtgrp->mon.abmc_ctr_id[index] =3D counterid; + + list_for_each_entry(d, &r->domains, list) + rdtgroup_abmc_domain(d, rdtgrp, evtid, index, 1); + + rdtgrp->mon.monitor_state |=3D mon_state; + + return 0; +} + +/** + * rdtgroup_monitor_state_write - Modify the resource group's assign + * + */ +static ssize_t rdtgroup_monitor_state_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_resource *r =3D &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + char *abmc_str, *event_str; + struct rdtgroup *rdtgrp; + int ret =3D 0, mon_state; + u32 evtid; + + rdtgrp =3D rdtgroup_kn_lock_live(of->kn); + if (!rdtgrp) { + rdtgroup_kn_unlock(of->kn); + return -ENOENT; + } + + rdt_last_cmd_clear(); + + while (buf && buf[0] !=3D '\0') { + /* Start processing the strings for each domain */ + abmc_str =3D strim(strsep(&buf, ";")); + event_str =3D strsep(&abmc_str, "=3D"); + + if (event_str && abmc_str) { + if (!strcmp(event_str, "total")) { + mon_state =3D TOTAL_ASSIGN; + evtid =3D QOS_L3_MBM_TOTAL_EVENT_ID; + } else if (!strcmp(event_str, "local")) { + mon_state =3D LOCAL_ASSIGN; + evtid =3D QOS_L3_MBM_LOCAL_EVENT_ID; + } else { + rdt_last_cmd_puts("Invalid ABMC event\n"); + ret =3D -EINVAL; + break; + } + + if (!strcmp(abmc_str, "assign")) { + ret =3D rdtgroup_assign_abmc(rdtgrp, r, evtid, mon_state); + if (ret) { + rdt_last_cmd_puts("ABMC assign failed\n"); + break; + } + } else { + rdt_last_cmd_puts("Invalid ABMC event\n"); + ret =3D -EINVAL; + break; + } + } else { + rdt_last_cmd_puts("Invalid ABMC input\n"); + ret =3D -EINVAL; + break; + } + } + + rdtgroup_kn_unlock(of->kn); + return ret ?: nbytes; +} + static void mon_event_config_read(void *info) { struct mon_config_info *mon_info =3D info; @@ -1944,9 +2093,10 @@ static struct rftype res_common_files[] =3D { }, { .name =3D "monitor_state", - .mode =3D 0444, + .mode =3D 0644, .kf_ops =3D &rdtgroup_kf_single_ops, .seq_show =3D rdtgroup_monitor_state_show, + .write =3D rdtgroup_monitor_state_write, }, { .name =3D "tasks", --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90675C10DCE for ; Fri, 1 Dec 2023 00:58:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377044AbjLAA6i (ORCPT ); Thu, 30 Nov 2023 19:58:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232464AbjLAA6R (ORCPT ); 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Thu, 30 Nov 2023 18:57:48 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 14/15] x86/resctrl: Add interface unassign a ABMC counter Date: Thu, 30 Nov 2023 18:57:19 -0600 Message-ID: <20231201005720.235639-15-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A3:EE_|MN2PR12MB4205:EE_ X-MS-Office365-Filtering-Correlation-Id: 54753559-3f1f-478b-6e24-08dbf2088abd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0YOkHGvZ+7nKV1WeXVOc+rnBYE+miy6RJ2Ve9MfyAioLcqXSK5TMWolBtZ0iSKArnAtCT5wevFBSbVSDmuZ+uKmFSSO4sN1NGzSJDowGd/qR6hMlhT6umC7vaGSKbW+wT+Db1NgjeymoKAKH5AALyelr/EH1MR9yIIlfepKy/f8Lbo7iJixf/34lX3UeiztuRl1f1KCoGrLcvY71u4vVCEj+zeGz09y3VgdWXtqKrq0CZe25fbMcQTEiJJ7liePVvyVx4DBynG7pQpcER4unV4t8vBmGBAHvHAf9W3pWOt/sn/AIgxHtHqDLBZTA5pAJbjpKvJukLyK1DN3OddipQEYf37PfjXcNnCVhJimB7QlGxS4CGkXJqKTCUHNHxX+Ch7bvtzhSJSHl0UL6M5K8+pm3DvGSf1rC/XvpaiP1b26A4ZdeUziJGEefXGGjBSachqoXRDjlBl6jbeUY5K1jFRV6UOJoQpUNA/oq39K5vSiZC8XaLbw8TpM1H1xtNEqvIFWpzgk/NbqQCbYwoOFhkI7NYkjU407fm9AJIwXilPbGuOaERkyIBxjwNJObdXQ5Xz1NDJVhwVQqHOFGC9A5ttnLhbHtmxJo5608NBbQtylFXdyl7r3VTEap7UHvMYfGAua22+EiE6JPq6NwnPnqjHtooa3aA/DADOj0bWILWYr9egOh6EOXkCYPCHhgM+sRYNDDFWubvEcQdUwHKBDFDDCJK3xH4Q0kpwn23f7BYJoZtpue4LUuFmBINeo9KBTCjNfNQULXzkoiDKjyS7gsMg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(39860400002)(346002)(136003)(376002)(230922051799003)(1800799012)(186009)(82310400011)(451199024)(64100799003)(36840700001)(40470700004)(46966006)(40480700001)(40460700003)(478600001)(2616005)(1076003)(336012)(26005)(6666004)(47076005)(7696005)(36860700001)(81166007)(356005)(82740400003)(36756003)(70206006)(5660300002)(54906003)(16526019)(44832011)(41300700001)(70586007)(426003)(7416002)(2906002)(4326008)(316002)(8676002)(110136005)(86362001)(8936002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:50.3762 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54753559-3f1f-478b-6e24-08dbf2088abd X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4205 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" With the support of ABMC (Assignable Bandwidth Monitoring Counters) feature, the user has the option to pin (or assign) or unpin (or unassign) the RMID to hardware counter and monitor the bandwidth for the longer duration. Provide the interface to unpin (or unassign) the counter. Signed-off-by: Babu Moger --- Documentation/arch/x86/resctrl.rst | 11 ++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 36 ++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/re= sctrl.rst index 65306e7d01b6..b42b59a7ba3c 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -417,6 +417,17 @@ When monitoring is enabled all MON groups will also co= ntain: # echo total=3Dassign > /sys/fs/resctrl/monitor_state # echo total=3Dassign;local=3Dassign > /sys/fs/resctrl/monitor_state =20 + The user needs to unpin (or unassign) counter to release it. + Example:: + + # echo total=3Dunassign > /sys/fs/resctrl/monitor_state + # cat /sys/fs/resctrl/monitor_state + total=3Dunassign;local=3Dassign + + # echo total=3Dunassign;local=3Dunassign > /sys/fs/resctrl/monitor_state + # cat /sys/fs/resctrl/monitor_state + total=3Dunassign;local=3Dunassign + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 671ff732992c..6eca47673344 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -192,6 +192,11 @@ static int abmc_counters_alloc(void) return counterid; } =20 +void abmc_counters_free(int counterid) +{ + abmc_free_map |=3D 1 << counterid; +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group @@ -1671,6 +1676,31 @@ static ssize_t rdtgroup_assign_abmc(struct rdtgroup = *rdtgrp, return 0; } =20 +static ssize_t rdtgroup_unassign_abmc(struct rdtgroup *rdtgrp, + struct rdt_resource *r, + u32 evtid, int mon_state) +{ + struct rdt_domain *d; + int index; + + index =3D mon_event_config_index_get(evtid); + if (index =3D=3D INVALID_CONFIG_INDEX) { + pr_warn_once("Invalid event id %d\n", evtid); + return -EINVAL; + } + + if (rdtgrp->mon.monitor_state & mon_state) { + list_for_each_entry(d, &r->domains, list) + rdtgroup_abmc_domain(d, rdtgrp, evtid, index, 0); + + abmc_counters_free(rdtgrp->mon.abmc_ctr_id[index]); + } + + rdtgrp->mon.monitor_state &=3D ~mon_state; + + return 0; +} + /** * rdtgroup_monitor_state_write - Modify the resource group's assign * @@ -1716,6 +1746,12 @@ static ssize_t rdtgroup_monitor_state_write(struct k= ernfs_open_file *of, rdt_last_cmd_puts("ABMC assign failed\n"); break; } + } else if (!strcmp(abmc_str, "unassign")) { + ret =3D rdtgroup_unassign_abmc(rdtgrp, r, evtid, mon_state); + if (ret) { + rdt_last_cmd_puts("ABMC unassign failed\n"); + break; + } } else { rdt_last_cmd_puts("Invalid ABMC event\n"); ret =3D -EINVAL; --=20 2.34.1 From nobody Mon Dec 29 04:18:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D65D1C10DCE for ; Fri, 1 Dec 2023 00:58:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232421AbjLAA6l (ORCPT ); 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Thu, 30 Nov 2023 18:57:49 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH 15/15] x86/resctrl: Update ABMC assignment on event configuration changes Date: Thu, 30 Nov 2023 18:57:20 -0600 Message-ID: <20231201005720.235639-16-babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com> References: <20231201005720.235639-1-babu.moger@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A2:EE_|DS7PR12MB6095:EE_ X-MS-Office365-Filtering-Correlation-Id: b1a08a67-e0a4-4c02-d2f8-08dbf2088b9c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: SpjN8XXetD0smoW/X5soFA+yOo9YqQFZI+jFjQsmQi/qN3X6Cz+WJ9RJRo4cItzeShwLqDUZG6j1T341wjv8mwZ5GjZgjhPssMX9Vq3wkObFyr26083E+sWrVMjwPVKtA95Ao5fJLKPFJB/C9eYGzV2N6R0UjzMhH52ChyXmh/5SgNF/mlQryj+SkxiQ7cktYETP1kxz3HiiwRq5BkE+1xWMqir3KS9ku0648P7fzHTV8fFYKd9bsGyNy5GuSQJk4WplKaGIAU0ah+sia30OxVWNBTfAo43Njjgx/5DZ5ebVgrx0Y5lioO2Mx+z+/gKKXNMZHtduQlxEysMB0v96ev5fcvj2Y9b0CR2dEY0yL+EwQiUutrR65aU3fg761U6oBXgaSnD3+W3wSj10YKzKVQBR6Af6hjBl4q98UYOwbIJP1wbfulk+gWoIMMKFoqZX3N8mYMA4XmmQ5HQiUG4SkTokSeWqe8vsbr80FABSiq9VRVeZ1u2AohTdw5HHl4EC/chpiA+UENotKS2Q68CWWAfM4EM+KxKe8YrhaRFOxn9ZZzOKzTmBJ/nFHZ39gjLq8H8NJ9QSHLltut7dz8CIcNkqjh0gUDcYAySeORrDRuQzppiZKccQs5E2+ihEbPLQDJjEY2wFTq0gsSe7b23jVnbX4FriFj/OS/So43pFselCow2iTrPxpncFI9G8H0NFgQZI/RofNsNX2HDHBly7+axVivEN6t5NX5gyiUgYfWFhvux8JsUU7rWSvZnyC7TMZJ1B1UpZmdDtJzUdG80cAA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(346002)(376002)(230922051799003)(1800799012)(186009)(64100799003)(451199024)(82310400011)(46966006)(40470700004)(36840700001)(86362001)(40460700003)(83380400001)(26005)(1076003)(6666004)(7696005)(2616005)(47076005)(426003)(36860700001)(478600001)(44832011)(7416002)(8936002)(5660300002)(8676002)(41300700001)(336012)(2906002)(110136005)(966005)(16526019)(4326008)(316002)(15650500001)(81166007)(70206006)(70586007)(54906003)(36756003)(356005)(82740400003)(40480700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2023 00:57:51.8402 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1a08a67-e0a4-4c02-d2f8-08dbf2088b9c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6095 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org When ABMC (Assignable Bandwidth Monitoring Counters) feature is enabled, bandwidth events can be read in following methods. 1. The contents of a specific counter can be read by setting the following fields in QM_EVTSEL: [ExtendedEvtID]=3D1, [EvtID]=3DL3CacheABMC and setting [RMID] to the desired counter ID. Reading QM_CTR will then return the contents of the specified counter. The E bit will be set if the counter configuration was invalid, or if an invalid counter ID was set in the QM_EVTSEL[RMID] field. Supporting this method requires changes in rmid_read interface. 2. Alternatively, the contents of a counter may be read by specifying an RMID and setting the [EvtID] to L3BWMonEvtn where n=3D {0,1}. If an assignable bandwidth counter is monitoring that RMID with a BwType bitmask that matches a QOS_EVT_CFG_n, that counter=E2=80=99s value will be returned= when reading QM_CTR. However, if multiple counters have the same configuration, QM_CTR will return the value of the counter with the lowest CtrID. Method 2 is supported in here. For the ABMC counter assignment to work, the assignment needs to be updated to match BwType to the contents of the MSR QOS_EVT_CFG_n. So, update the ABMC assignment when event configuration changes. The feature details are available in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/r= esctrl/rdtgroup.c index 6eca47673344..11890b4afb9f 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1768,6 +1768,38 @@ static ssize_t rdtgroup_monitor_state_write(struct k= ernfs_open_file *of, return ret ?: nbytes; } =20 +static void rdtgroup_update_abmc(struct rdt_resource *r, + struct rdt_domain *d, u32 evtid) +{ + struct rdtgroup *prgrp, *crgrp; + int index, mon_state; + + if (evtid =3D=3D QOS_L3_MBM_TOTAL_EVENT_ID) + mon_state =3D TOTAL_ASSIGN; + else + mon_state =3D LOCAL_ASSIGN; + + index =3D mon_event_config_index_get(evtid); + if (index =3D=3D INVALID_CONFIG_INDEX) { + pr_warn_once("Invalid event id %d\n", evtid); + return; + } + + /* + * Update the assignment for all the monitor groups if the group + * is configured with ABMC assignment. + */ + list_for_each_entry(prgrp, &rdt_all_groups, rdtgroup_list) { + if (prgrp->mon.monitor_state & mon_state) + rdtgroup_abmc_domain(d, prgrp, evtid, index, 1); + + list_for_each_entry(crgrp, &prgrp->mon.crdtgrp_list, mon.crdtgrp_list) { + if (crgrp->mon.monitor_state & mon_state) + rdtgroup_abmc_domain(d, crgrp, evtid, index, 1); + } + } +} + static void mon_event_config_read(void *info) { struct mon_config_info *mon_info =3D info; @@ -1852,6 +1884,7 @@ static void mon_event_config_write(void *info) static int mbm_config_write_domain(struct rdt_resource *r, struct rdt_domain *d, u32 evtid, u32 val) { + struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r); struct rdt_hw_domain *hw_dom =3D resctrl_to_arch_dom(d); struct mon_config_info mon_info =3D {0}; int ret =3D 0; @@ -1892,6 +1925,13 @@ static int mbm_config_write_domain(struct rdt_resour= ce *r, else goto out; =20 + /* + * Event configuration changed for the domain, so Update + * the ABMC assignment. + */ + if (hw_res->abmc_enabled) + rdtgroup_update_abmc(r, d, evtid); + /* * When an Event Configuration is changed, the bandwidth counters * for all RMIDs and Events will be cleared by the hardware. The --=20 2.34.1