From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAB40C4167B for ; Thu, 30 Nov 2023 16:18:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232063AbjK3QS3 (ORCPT ); Thu, 30 Nov 2023 11:18:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229503AbjK3QS1 (ORCPT ); Thu, 30 Nov 2023 11:18:27 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8A91196; Thu, 30 Nov 2023 08:18:33 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E5A5AC0278; Thu, 30 Nov 2023 17:18:31 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361112; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=UzuIP5S8AevrVXGMKCmE3Yuhm7j6XpmBkoAvyid/FQM=; b=TrRftCxaYKSg3bZRr9aLe0Oa3y/CuYLIgvW+TgB/+ZsCoRknhlLFiNqBc4WXHw7U8XTgj8 0E/AaWOisa7dHian+FzUnBbtyXMWP0ex4iY0mJ9pdZ3Y5vubD/nnDcBYQfv+ibpPcctdHh YUcJGD2cMMGjJFKwLg0rrH1pGPqSs4vXsc1HUf5T5AYG5AwTABzNqo0cxR46oowpJHVF6s jUaBLbq1lkf75qFeiBqC+7BA9S/amKSoyZLB8tf86AzE4lmxLjRZwO6RXdFyZ3hRMHBbkl mPyxugDIcd31YB47TAgbXy7fsLA7kWjPQogMnXA75mirTEMHoeDrmf+zqADt2A== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 01/14] arm64: dts: imx8mm-kontron: Add support for display bridges on BL i.MX8MM Date: Thu, 30 Nov 2023 17:16:01 +0100 Message-ID: <20231130161657.556483-2-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The Kontron Electronics BL i.MX8MM has oboard disply bridges for DSI->HDMI and DSI->LVDS conversion. The DSI interface is muxed by a GPIO-controlled switch to one of these two bridges. By default the HDMI bridge is enabled. The LVDS bridge can be selected by loading an additional (panel-specific) overlay. Signed-off-by: Frieder Schrempf --- Changes for v2: * Rework DSI mux GPIO logic to be compatible with overlay * Switch from 4 to 2 DSI lanes for LVDS bridge to fix non-working display --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 158 ++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm= 64/boot/dts/freescale/imx8mm-kontron-bl.dts index dcec57c20399e..0fb16b811461e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -25,6 +25,17 @@ osc_can: clock-osc-can { clock-output-names =3D "osc-can"; }; =20 + hdmi-out { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi_in_conn: endpoint { + remote-endpoint =3D <&bridge_out_conn>; + }; + }; + }; + leds { compatible =3D "gpio-leds"; pinctrl-names =3D "default"; @@ -132,6 +143,102 @@ ethphy: ethernet-phy@0 { }; }; =20 +&gpio4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio4>; + + dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog { + gpio-hog; + gpios =3D <14 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "dsi-mux-sel"; + status =3D "okay"; + }; + + dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog { + gpio-hog; + gpios =3D <14 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "dsi-mux-sel"; + status =3D "disabled"; + }; + + dsi-mux-oe-hog { + gpio-hog; + gpios =3D <15 GPIO_ACTIVE_LOW>; + output-high; + line-name =3D "dsi-mux-oe"; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + status =3D "okay"; + + hdmi: hdmi@39 { + compatible =3D "adi,adv7535"; + reg =3D <0x39>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_adv7535>; + + interrupt-parent =3D <&gpio4>; + interrupts =3D <16 IRQ_TYPE_LEVEL_LOW>; + + adi,dsi-lanes =3D <4>; + + a2vdd-supply =3D <®_vdd_1v8>; + avdd-supply =3D <®_vdd_1v8>; + dvdd-supply =3D <®_vdd_1v8>; + pvdd-supply =3D <®_vdd_1v8>; + v1p2-supply =3D <®_vdd_1v8>; + v3p3-supply =3D <®_vdd_3v3>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + bridge_in_dsi_hdmi: endpoint { + remote-endpoint =3D <&dsi_out_bridge>; + }; + }; + + port@1 { + reg =3D <1>; + bridge_out_conn: endpoint { + remote-endpoint =3D <&hdmi_in_conn>; + }; + }; + }; + }; + + lvds: bridge@2c { + compatible =3D "ti,sn65dsi84"; + reg =3D <0x2c>; + enable-gpios =3D <&gpio4 26 GPIO_ACTIVE_HIGH>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sn65dsi84>; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + bridge_in_dsi_lvds: endpoint { + remote-endpoint =3D <&dsi_out_bridge>; + data-lanes =3D <1 2>; + }; + }; + }; + }; +}; + &i2c4 { clock-frequency =3D <100000>; pinctrl-names =3D "default"; @@ -144,6 +251,30 @@ rx8900: rtc@32 { }; }; =20 +&lcdif { + status =3D "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency =3D <54000000>; + /* + * Let the driver calculate an appropriate clock rate based on the pixel + * clock instead of using the fixed value from imx8mm.dtsi. + */ + /delete-property/ samsung,pll-clock-frequency; + status =3D "okay"; + + ports { + port@1 { + reg =3D <1>; + + dsi_out_bridge: endpoint { + remote-endpoint =3D <&bridge_in_dsi_hdmi>; + }; + }; + }; +}; + &pwm2 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_pwm2>; @@ -207,6 +338,12 @@ &iomuxc { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_gpio>; =20 + pinctrl_adv7535: adv7535grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 + >; + }; + pinctrl_can: cangrp { fsl,pins =3D < MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 @@ -277,6 +414,20 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; }; =20 + pinctrl_gpio4: gpio4grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins =3D < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 @@ -290,6 +441,13 @@ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 >; }; =20 + pinctrl_sn65dsi84: sn65dsi84grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins =3D < MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0461DC10DC2 for ; Thu, 30 Nov 2023 16:18:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232246AbjK3QSj (ORCPT ); Thu, 30 Nov 2023 11:18:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232191AbjK3QSe (ORCPT ); Thu, 30 Nov 2023 11:18:34 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2EC3010DB; Thu, 30 Nov 2023 08:18:38 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id B6F63C0279; Thu, 30 Nov 2023 17:18:35 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361116; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=cVVAh3S9ca4p87QnkPZb5dIfyL7ZE1t+EZ1mNj7e8O8=; b=PlINqgQVMar90V7YnsTec9YgZEaoaAHhYmMPhijgrqyJsuZo400mI0RizngRaDTijUKJVI UOI9bQPsVwXllrfQiMpybd8RVeaPIslIwRU3rwFjOHzkjQ0tSOWZXozKvKvJ5ogYvlbp64 3mBeLCClPTGXM/5/BzS7qhBxmvqY5y4TsSjRJDx5PVc1bi8USfhLd6+MKBK0CsgVNAPjO1 kmklbnnM+UdWF4w+BxbIOI7lssmO3lueAT5lQRflr+/obPuNsEzFRX0wUluhBJXXxN6Bn2 9phwVdiIG/jY5H39UhbqPvtFETUjCiBH2U0b8m8WQmctaQNmdDqsF6plxDmOdA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Alexander Stein , Fabio Estevam , Gregor Herburger , Marcel Ziswiler , Marek Vasut , NXP Linux Team , Pengutronix Kernel Team , Philippe Schenker , Tim Harvey Subject: [PATCH v2 02/14] arm64: dts: imx8mm-kontron: Add DL (Display-Line) overlay with LVDS support Date: Thu, 30 Nov 2023 17:16:02 +0100 Message-ID: <20231130161657.556483-3-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The Kontron Electronics DL i.MX8MM consists of the BL i.MX8MM board and a 7" LVDS panel. Provide an overlay that enables the panel. Signed-off-by: Frieder Schrempf --- Changes for v2: * Rework DSI mux GPIO logic to be compatible with overlay --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../boot/dts/freescale/imx8mm-kontron-dl.dtso | 200 ++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 300049037eb0b..e08024797721a 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -166,6 +166,10 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-11x11-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-tqma9352-mba93xxla.dtb =20 +imx8mm-kontron-dl-dtbs :=3D imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo + +dtb-$(CONFIG_ARCH_MXC) +=3D imx8mm-kontron-dl.dtb + imx8mm-venice-gw72xx-0x-imx219-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-imx219.dtbo imx8mm-venice-gw72xx-0x-rpidsi-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb imx8m= m-venice-gw72xx-0x-rpidsi.dtbo imx8mm-venice-gw72xx-0x-rs232-rts-dtbs :=3D imx8mm-venice-gw72xx-0x.dtb im= x8mm-venice-gw72xx-0x-rs232-rts.dtbo diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso b/arch/ar= m64/boot/dts/freescale/imx8mm-kontron-dl.dtso new file mode 100644 index 0000000000000..c6369072577e0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Kontron Electronics GmbH + */ + +/dts-v1/; +/plugin/; + +#include +#include "imx8mm-pinfunc.h" + +&{/} { + compatible =3D "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm"; + + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm1 0 50000 0>; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <100>; + }; + + panel { + compatible =3D "panel-lvds"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel>; + backlight =3D <&backlight>; + data-mapping =3D "vesa-24"; + enable-gpios =3D <&gpio3 19 GPIO_ACTIVE_HIGH>; + height-mm =3D <86>; + width-mm =3D <154>; + + panel-timing { + clock-frequency =3D <51200000>; + hactive =3D <1024>; + vactive =3D <600>; + hsync-len =3D <1>; + hfront-porch =3D <160>; + hback-porch =3D <160>; + vsync-len =3D <1>; + vfront-porch =3D <12>; + vback-porch =3D <23>; + }; + + port { + panel_out_bridge: endpoint { + remote-endpoint =3D <&bridge_out_panel>; + }; + }; + }; +}; + +&dsi_mux_sel_hdmi { + status =3D "disabled"; +}; + +&dsi_mux_sel_lvds { + status =3D "okay"; +}; + +&dsi_out_bridge { + remote-endpoint =3D <&bridge_in_dsi_lvds>; +}; + +&gpio3 { + panel_rst { + gpio-hog; + gpios =3D <20 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "panel-reset"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel_rst>; + }; + + panel_stby { + gpio-hog; + gpios =3D <21 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "panel-standby"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel_stby>; + }; + + panel_hinv { + gpio-hog; + gpios =3D <24 GPIO_ACTIVE_HIGH>; + output-high; + line-name =3D "panel-horizontal-invert"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel_hinv>; + }; + + panel_vinv { + gpio-hog; + gpios =3D <25 GPIO_ACTIVE_HIGH>; + output-low; + line-name =3D "panel-vertical-invert"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel_vinv>; + }; +}; + +&hdmi { + status =3D "disabled"; +}; + +&i2c2 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + status =3D "okay"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + gt911@5d { + compatible =3D "goodix,gt928"; + reg =3D <0x5d>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_touch>; + interrupt-parent =3D <&gpio3>; + interrupts =3D <22 8>; + reset-gpios =3D <&gpio3 23 0>; + irq-gpios =3D <&gpio3 22 0>; + }; +}; + +&lvds { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + bridge_out_panel: endpoint { + remote-endpoint =3D <&panel_out_bridge>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm1>; + status =3D "okay"; +}; + +&iomuxc { + pinctrl_panel_rst: panelrstgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 + >; + }; + + pinctrl_panel_stby: panelstbygrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 + >; + }; + + pinctrl_panel_hinv: panelhinvgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 + >; + }; + + pinctrl_panel_vinv: panelvinvgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 + >; + }; +}; --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 884E5C4167B for ; Thu, 30 Nov 2023 16:18:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232272AbjK3QSm (ORCPT ); Thu, 30 Nov 2023 11:18:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38324 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232238AbjK3QSf (ORCPT ); Thu, 30 Nov 2023 11:18:35 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F26D1700; Thu, 30 Nov 2023 08:18:40 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 3402DC01DC; Thu, 30 Nov 2023 17:18:38 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361118; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=4wc5xlMkQVwPcIfy78SOPNz2f9X1LzOiI43PLTGlKIw=; b=HIqDSTpFOvPNcaV3anPh7zEcy3RpJpAPoJ9yc+LRE1KhwmhP2OJhltFzQgAT4/NuyJlQyv 8Tzn1nLuxp86boeemiwUqvBVWgNtRpTN8Bzgsn7P37J2YbjL9tzcHu70VRrJ8j1383+RQy zE5vih9Ohd5/tgq/dWuaSKVGGlU2ca8aXlJiHxNSJ8JjesPWw7dgPVTvMU+mR7EowhmBdl wfVUCa09RlgiTKB2XC6eKfncJ2DBXoeWbyQkmRqeWoNQosW/1b8gOG4M6Zjd27n+ITgkDr R0yUiB1HQmn07VSJxQRWlmFMJ04omLFBF9QPJvI1UaCVd2RMC4qk0nuZ+FmVUw== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 03/14] arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on OSM-S i.MX8MM Date: Thu, 30 Nov 2023 17:16:03 +0100 Message-ID: <20231130161657.556483-4-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf There are external pullup resistors on the board and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM= -S") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 8b16bd68576c0..0730c22e5b6b9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -294,8 +294,8 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 =20 pinctrl_i2c4: i2c4grp { fsl,pins =3D < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 >; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 6e75ab879bf59..3e7db968f7e64 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -252,8 +252,8 @@ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 =20 pinctrl_i2c1: i2c1grp { fsl,pins =3D < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; =20 --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0562C4167B for ; Thu, 30 Nov 2023 16:19:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235223AbjK3QSu (ORCPT ); Thu, 30 Nov 2023 11:18:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38320 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232211AbjK3QSg (ORCPT ); Thu, 30 Nov 2023 11:18:36 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6AC9D1A4; Thu, 30 Nov 2023 08:18:42 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 33284C027B; Thu, 30 Nov 2023 17:18:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361120; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=yTILABmjrRzxd4BiyZ/RTjW9onr6Z125M0Mod5/VAOE=; b=QFR1+jxR3q32TFtUE6PXMfEwsyqvEMsXfliSPq772ER3IZ+7SQclkdfDKtrtedXXlEOVq7 F5HHlO6eDDwYF9RNJLAUFYv++O6fCXbS1RXCFhBq1obs6USUHWkfrScR6vhEgKsI9NGWR6 3QPiMcjXTm3bLMYAAgz0Sj91R0MZQPhIvHLsA1O9+IntPAc+hxuRsZl4NgnxXxKFMGf7aZ mL2BIoUnZivk7aQSAquRPGA8CZ4OC3EG8lL0YMCcboVcEdTiJIJvOwgu7oW/g0CYAODMu/ v5bWDXdXeBInAkiw/sFuecLleC2wy4ogsncYOM7jbPXaxu4tY/+ltBos12yARQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 04/14] arm64: dts: imx8mm-kontron: Disable pullups for I2C signals on SL/BL i.MX8MM Date: Thu, 30 Nov 2023 17:16:04 +0100 Message-ID: <20231130161657.556483-5-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf There are external pullup resistors on the board and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and base= boards") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts | 4 ++-- arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm= 64/boot/dts/freescale/imx8mm-kontron-bl.dts index 0fb16b811461e..6d0c3d7e1d103 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -430,8 +430,8 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 =20 pinctrl_i2c4: i2c4grp { fsl,pins =3D < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 >; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi b/arch/ar= m64/boot/dts/freescale/imx8mm-kontron-sl.dtsi index 1f8326613ee9e..2076148e08627 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-sl.dtsi @@ -237,8 +237,8 @@ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 =20 pinctrl_i2c1: i2c1grp { fsl,pins =3D < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; =20 --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAC0CC4167B for ; Thu, 30 Nov 2023 16:19:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345227AbjK3QS4 (ORCPT ); Thu, 30 Nov 2023 11:18:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232161AbjK3QSh (ORCPT ); Thu, 30 Nov 2023 11:18:37 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67AB110DB; Thu, 30 Nov 2023 08:18:43 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 82E6DC0299; Thu, 30 Nov 2023 17:18:41 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361121; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=FWmRsZBPeCXE6vjeXku2odgdbDKh17lvQDeEaVqehTE=; b=Z7NP5RpaTw3MIjxwsmnte30n+WOZ2rGGmHahxck8cwPNrw08b52Rkwm5hjXPiAOeYPjTvI gh01KjutQ82a4X6+C9kv/iDqpeGApPUh6QIgTSaqg/I9SNNH8j/Vcc6kk5ii3BCpR5gd3H 67idbuqWEGB6TIinyJDNNcPQbyQoqMykezHtkwfxaCb5u60QvQC1xqMP5RAU58mx8LfxBP JypY490vgvfxyGH166OnCwPSufOp6MGj+1reSjsmYb3VUloppm6688tJNeGdHzwisCXZqM eBhXkYvT4e0bbnC9Ligf8hN6bRJvzPBG4mfCMn+2WQMuPJ+lVAejPxXB3KYvlA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 05/14] arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL OSM-S board Date: Thu, 30 Nov 2023 17:16:05 +0100 Message-ID: <20231130161657.556483-6-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf These signals are actively driven by the SoC or by the onboard transceiver. There's no need to enable the internal pull resistors and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM= -S") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 0730c22e5b6b9..1dd03ef0a7835 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -313,19 +313,19 @@ MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 =20 pinctrl_uart1: uart1grp { fsl,pins =3D < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; =20 pinctrl_uart2: uart2grp { fsl,pins =3D < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; }; =20 --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C414C4167B for ; Thu, 30 Nov 2023 16:19:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235208AbjK3QS7 (ORCPT ); Thu, 30 Nov 2023 11:18:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232285AbjK3QSr (ORCPT ); Thu, 30 Nov 2023 11:18:47 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17EC81710; Thu, 30 Nov 2023 08:18:45 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id E6EBCC029B; Thu, 30 Nov 2023 17:18:42 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361123; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=OvtlGvUIt/VIQLbFlGg/QdDFVoax280yTkdU9/Mj4W0=; b=FJp+e3jjdSXPpVHMmh6NeS8+FnNShUKA3tdv7DMYUidH+T8LuaMwAPC1HPUa7qJ8+Bryik PKVh0YD8umE3jXPDsUHM5TqaQXGnI9DAuJCf57VR1HY0nizsQoaOhQ7CWRhv8h55y9bVrL BDrpyh1YGmCv12GbShzsmyCJB//IwEOF7/PjrbETwcNkloQq9OVw61di3v0ZTXtHCMVLf0 JgAvk+YkyQO+vqIf3I+EzDbPknSG6/XPg+tACmTR8jO/dAGh2EN5uQQPweiVy44AqKjia+ W7wP8+vnM0BF+BjLEBLYhj1doQxXYAAW6Qsp19gW2a9kzBGOo/rr9sOkvn0ANQ== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 06/14] arm64: dts: imx8mm-kontron: Disable pullups for onboard UART signals on BL board Date: Thu, 30 Nov 2023 17:16:06 +0100 Message-ID: <20231130161657.556483-7-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf These signals are actively driven by the SoC or by the onboard transceiver. There's no need to enable the internal pull resistors and due to silicon errata ERR050080 let's disable the internal ones to prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and base= boards") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm= 64/boot/dts/freescale/imx8mm-kontron-bl.dts index 6d0c3d7e1d103..97562d6ed8012 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -450,19 +450,19 @@ MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19 =20 pinctrl_uart1: uart1grp { fsl,pins =3D < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 >; }; =20 pinctrl_uart2: uart2grp { fsl,pins =3D < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 >; }; =20 --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79727C4167B for ; Thu, 30 Nov 2023 16:19:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232191AbjK3QTD (ORCPT ); Thu, 30 Nov 2023 11:19:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235197AbjK3QSs (ORCPT ); Thu, 30 Nov 2023 11:18:48 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB1F41728; Thu, 30 Nov 2023 08:18:46 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9ADD2C029A; Thu, 30 Nov 2023 17:18:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361125; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=9V054hOIzH5uCgC/7YIk1LD06yAwtHZiR/WWepL9Bxo=; b=Z8hXGdl0lpLByL9oZknD3A4E21GiRq7tqCj6u1yt7fa3vk3yW/Ne0zI70zCSxTdIVgcdbr HFdF/4Mu2MatZXZJmqi6hbt4tejVNUktx4U5XbJDIpWyHWTKJULFLkQuFrntDLJDOIzUq8 Owi5dzpJneG+DrvEZKMu+hWZOu1Ky3IFqQUywvfaNyrYskCc9NXt+Uhj1ajo9290MOnrIG szZMG0WP+qoAUDWQAOXHvw3EvJHxpQv5/VXlnQhIinNnUt6CvSw4+rkXmgUUYuT6a1+hlt TyLWs1OFW+f7Pli4BnfPuwujrbrKEGQM9d/wS8T3RGbqh4ahgYBc8mxoqLJd7Q== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 07/14] arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL OSM-S board Date: Thu, 30 Nov 2023 17:16:07 +0100 Message-ID: <20231130161657.556483-8-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Some signals have external pullup resistors on the board and don't need the internal ones to be enabled. Due to silicon errata ERR050080 let's disable the internal pull resistors whererever possible and prevent any unwanted behavior in case they wear out. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM= -S") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 1dd03ef0a7835..d9fa0deea7002 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -337,40 +337,40 @@ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 =20 pinctrl_usdhc2: usdhc2grp { fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; =20 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8541C10DC2 for ; Thu, 30 Nov 2023 16:19:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235302AbjK3QTK (ORCPT ); Thu, 30 Nov 2023 11:19:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231796AbjK3QSt (ORCPT ); Thu, 30 Nov 2023 11:18:49 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 860211737; Thu, 30 Nov 2023 08:18:48 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 49D2AC029C; Thu, 30 Nov 2023 17:18:46 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361126; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=V2fZDEh0BFl3u6DpO0v0uDkHfQkJ9wm5ymovEp1eBq8=; b=pJ5MQ3H/9dkbzDIPt1H0Wfl+GC9noZnIsOLZuTog4oMvK2czaf/Al6VxtQb/IgFdPyliBH KqYXJdBAsVjbcL7D8TBNR9zah1UdQa6mmlNLmKRaCtAn+ahHvF6gUyOUtiUDBKB5kOxlQP qHn6Cwyca4YNLYjxrwYuhY4QBEvzX9OshnXLGmmghhtqI5bzapwfWkdIiiRwZQly1cU+7p V39gTkY1Oaih+vw72fxUPObUKpBHMrUSgHT3uYdxrMkvMDT/vwZljtpXRl+1rd60+07gyC 0WM13vm8cVC/+dtKFM1LldexFIcCra8+jzQhjuL0J/Yq428QkR1nkPJJe5NJbA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 08/14] arm64: dts: imx8mm-kontron: Disable pull resistors for SD card signals on BL board Date: Thu, 30 Nov 2023 17:16:08 +0100 Message-ID: <20231130161657.556483-9-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf Some signals have external pullup resistors on the board and don't need the internal ones to be enabled. Due to silicon errata ERR050080 let's disable the internal pull resistors whererever possible and prevent any unwanted behavior in case they wear out. Fixes: 8668d8b2e67f ("arm64: dts: Add the Kontron i.MX8M Mini SoMs and base= boards") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- .../boot/dts/freescale/imx8mm-kontron-bl.dts | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts b/arch/arm= 64/boot/dts/freescale/imx8mm-kontron-bl.dts index 97562d6ed8012..e07497411caea 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts @@ -474,40 +474,40 @@ MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 =20 pinctrl_usdhc2: usdhc2grp { fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; =20 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; =20 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 >; }; }; --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B049AC4167B for ; Thu, 30 Nov 2023 16:19:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235218AbjK3QTO (ORCPT ); Thu, 30 Nov 2023 11:19:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232236AbjK3QSu (ORCPT ); Thu, 30 Nov 2023 11:18:50 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DD051991; Thu, 30 Nov 2023 08:18:49 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9FB66BFC65; Thu, 30 Nov 2023 17:18:47 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361128; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ZbNPEWDbA0n9EE6XFqNkWMsNpks/uKrE8bcK14NAwUk=; b=Uwf7C9YbIPkuo+kdcidvDzibociEUVTJyDjYWu7epLuORwJCR+6sYtqKE1pcL9KnkXSX4E rMm6gvX2DYeYKHNXO7ag7B4WqmaGJZDYKJN2YRnZ+/FBYjKk3rNVB6jsaKEm+sWDTfWFJI iOackmn9e5z4HRmybGZ3ApzB4NullXAmhLKumz+NMFcAL6xNTV8uu1FE2CeUWnqUjT8kMv ToTTh9GhZgJtzs1Iertcvk6TFMT2R4FV05gMtOYsHnGCd2QvtyrXtjcJ4ZCYtmWQ+8w5KA PtBaxeL8rbQYRcWoC5pZTBfrxwrZdAuTRwWM6cYa7f5vIf52E/OSEs4s9iP+vg== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 09/14] arm64: dts: imx8mm-kontron: Fix interrupt for RTC on OSM-S i.MX8MM module Date: Thu, 30 Nov 2023 17:16:09 +0100 Message-ID: <20231130161657.556483-10-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The level of the interrupt signal is active low instead. Fix this. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM= -S") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 3e7db968f7e64..60abcb636cedf 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -210,7 +210,7 @@ rv3028: rtc@52 { reg =3D <0x52>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_rtc>; - interrupts-extended =3D <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended =3D <&gpio4 1 IRQ_TYPE_LEVEL_LOW>; trickle-diode-disable; }; }; --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78B75C4167B for ; Thu, 30 Nov 2023 16:19:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345462AbjK3QTR (ORCPT ); Thu, 30 Nov 2023 11:19:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232291AbjK3QSv (ORCPT ); Thu, 30 Nov 2023 11:18:51 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A14519A0; Thu, 30 Nov 2023 08:18:51 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id EC670C01DC; Thu, 30 Nov 2023 17:18:48 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361129; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=UxsVxgqSX3mAJ7gge4MofkQBYLKfCrBx9YKb7nWSyY0=; b=BTXj9vuz1ACq1iTnrLrE10p7IiJIVBR/4hqJa4l7SrZEYTL2VLfJ94E3vqo398nMYkG08d laY7U7U8eHtGmazT94DTf+l/jcak1mfY1FmrjGDyc71tJxadF7SYmfaesO7KoccAnrr4vw MnYJtExftV7u2Eesf50q6RIv0N1lyPV7T5tzSjdbEiiU77kOI83KGYbTuDj38r8mWLJUST 125sPf+pCNyQhxOvj2yh98lpXOlDrtefL1RWHjrjKz5Oz3Jvoaf7JseUf7XHqpFhLkFcgR EzhLyKOPJ0kIMMv2FggG6NzOEprSAdqhkLaw6JcnFpDN4sVty+KjKkvXl4sW0A== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Frieder Schrempf , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 10/14] arm64: dts: imx8mm-kontron: Fix OSM-S devicetrees to match latest hardware Date: Thu, 30 Nov 2023 17:16:10 +0100 Message-ID: <20231130161657.556483-11-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The current state of the devicetree for the i.MX8MM OSM-S and the BL baseboard reflects deprecated prototype hardware. Update the board description to match the latest hardware revision. As the old hardware is not available anymore, was only produced in very small quantities and was broken in some ways, we can safely fixup the original devicetree. Fixes: de9618e84f76 ("arm64: dts: Add support for Kontron SL/BL i.MX8MM OSM= -S") Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 64 ++++++++++++------- 1 file changed, 41 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index d9fa0deea7002..7c5586efccc59 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -30,18 +30,18 @@ leds { =20 led1 { label =3D "led1"; - gpios =3D <&gpio1 12 GPIO_ACTIVE_LOW>; + gpios =3D <&gpio1 5 GPIO_ACTIVE_LOW>; linux,default-trigger =3D "heartbeat"; }; =20 led2 { label =3D "led2"; - gpios =3D <&gpio1 13 GPIO_ACTIVE_LOW>; + gpios =3D <&gpio3 8 GPIO_ACTIVE_LOW>; }; =20 led3 { label =3D "led3"; - gpios =3D <&gpio1 14 GPIO_ACTIVE_LOW>; + gpios =3D <&gpio3 7 GPIO_ACTIVE_LOW>; }; }; =20 @@ -54,7 +54,7 @@ reg_rst_eth2: regulator-rst-eth2 { compatible =3D "regulator-fixed"; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_usb_eth2>; - gpio =3D <&gpio3 2 GPIO_ACTIVE_HIGH>; + gpio =3D <&gpio1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-name =3D "rst-usb-eth2"; @@ -91,7 +91,7 @@ can@0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_can>; clocks =3D <&osc_can>; - interrupts-extended =3D <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + interrupts-extended =3D <&gpio5 1 IRQ_TYPE_LEVEL_LOW>; /* * Limit the SPI clock to 15 MHz to prevent issues * with corrupted data due to chip errata. @@ -118,7 +118,7 @@ eeram@0 { &fec1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_enet>; - phy-connection-type =3D "rgmii-rxid"; + phy-connection-type =3D "rgmii-id"; phy-handle =3D <ðphy>; status =3D "okay"; =20 @@ -127,10 +127,11 @@ mdio { #size-cells =3D <0>; =20 ethphy: ethernet-phy@0 { + compatible =3D "ethernet-phy-id4f51.e91b", + "ethernet-phy-ieee802.3-c22"; reg =3D <0>; - reset-assert-us =3D <1>; - reset-deassert-us =3D <15000>; - reset-gpios =3D <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-gpios =3D <&gpio1 3 GPIO_ACTIVE_LOW>; }; }; }; @@ -153,11 +154,24 @@ &gpio5 { "", "", "", "", "", "", "", ""; }; =20 +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + status =3D "okay"; + + usb-hub@2c { + compatible =3D "microchip,usb2514b"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb_hub>; + reg =3D <0x2c>; + non-removable-ports =3D <0>, <3>; + reset-gpios =3D <&gpio5 2 GPIO_ACTIVE_LOW>; + }; +}; + &i2c4 { - clock-frequency =3D <100000>; pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_i2c4>; - status =3D "okay"; }; =20 &pwm2 { @@ -196,13 +210,13 @@ &usbotg2 { status =3D "okay"; =20 usb1@1 { - compatible =3D "usb424,9514"; + compatible =3D "usb424,2514"; reg =3D <1>; #address-cells =3D <1>; #size-cells =3D <0>; =20 usbnet: ethernet@1 { - compatible =3D "usb424,ec00"; + compatible =3D "usbb95,772b"; reg =3D <1>; local-mac-address =3D [ 00 00 00 00 00 00 ]; }; @@ -223,7 +237,7 @@ &usdhc2 { &iomuxc { pinctrl_can: cangrp { fsl,pins =3D < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 >; }; =20 @@ -261,27 +275,24 @@ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* PHY RST */ >; }; =20 pinctrl_gpio_led: gpioledgrp { fsl,pins =3D < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 >; }; =20 pinctrl_gpio1: gpio1grp { fsl,pins =3D < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 >; }; @@ -292,6 +303,13 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 >; }; =20 + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins =3D < MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 @@ -331,7 +349,7 @@ MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 =20 pinctrl_usb_eth2: usbeth2grp { fsl,pins =3D < - MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 >; }; =20 --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E298C4167B for ; Thu, 30 Nov 2023 16:19:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345596AbjK3QTZ (ORCPT ); Thu, 30 Nov 2023 11:19:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345286AbjK3QS5 (ORCPT ); Thu, 30 Nov 2023 11:18:57 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFBA41BC2; Thu, 30 Nov 2023 08:18:52 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 9A240C021E; Thu, 30 Nov 2023 17:18:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361131; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=hexenviRTNB2sbgn72PpAXHZwoLmh9iJeNumQtMSjS0=; b=AvWQgXtXPEG45asHKNVXjwnaTnh5I7QI9tHeDE9Nb/TZWF7Mh9syfZA8rxqR1lBgRyaOV+ 3+4vQk+JVwMaVAKFea7b2qX+Rdt2StZroMI6iGewOZilNb7JmmZLkfR3lyBlSKWJG2I9kp /lbMI18APT38mrKEuwRJQJ+n3ClTrtVzG830JbgOLszaT589Pd1JpywYEjTw+kARV91Ypf RKeURfPjApE+njbhDvZayqEmknWIg+f/QYcXi5p8HbPLUkySGK6Q11sKXi3QCw8R3mTJA5 w+jTvSQ9SFGZcu7rSEUNSrRVf1Rkpg6YAWH7fJokxOzu8r10jWrh0+G4V48WaA== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 11/14] arm64: dts: imx8mm-kontron: Disable uneffective PUE bit in SDIO IOMUX Date: Thu, 30 Nov 2023 17:16:11 +0100 Message-ID: <20231130161657.556483-12-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The PUE bit is only effective if the PE bit is also set. To avoid confusion, disable the PUE bit if it is not needed. Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 7c5586efccc59..12f786a72fbd5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -362,7 +362,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; =20 @@ -375,7 +375,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; =20 @@ -388,7 +388,7 @@ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 >; }; }; --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C6E7C4167B for ; Thu, 30 Nov 2023 16:19:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345687AbjK3QT1 (ORCPT ); Thu, 30 Nov 2023 11:19:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38426 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235204AbjK3QS6 (ORCPT ); Thu, 30 Nov 2023 11:18:58 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14B7C1BD1; Thu, 30 Nov 2023 08:18:53 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 2212CBFC65; Thu, 30 Nov 2023 17:18:52 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361132; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=vMUqDwo82qK4dTsItk3tN+6GzzDqaT54i6PZPDlfLew=; b=ycf4411dTB/jtdnehXOXPANFAxgiozAJkBTrGCMY1B/VWxgA42mTLkWC6xvQd8LxHC0HZH tnPZOF7ACXVBNg2Z9HIO3e3JJ7fvaUvoNChJEk80vOhphJDrtz2qBH/7RO9tv57dKvLK87 FGR7Pb7TKluFzY5xswgFmvPGG+K1aQQR+4imjCoI+MvJcfN3mgGULdg1/jdzAiexzLm6U6 r9hTR3nLISl3IirBBJGwfe1bQ9bmjyf0rzL2POT5EIGXLJwDA7KFopOYiGNYu0nTRZYQtQ BumWc+5KpCUXJ31xQqjx+7EOjWSEGIMMYzwjHRFg4RarcZmNhn6FGNfZRMk6og== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 12/14] arm64: dts: imx8mm-kontron: Remove useless trickle-diode-disable from RTC node Date: Thu, 30 Nov 2023 17:16:12 +0100 Message-ID: <20231130161657.556483-13-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The RV3028 driver doesn't use this property. Remove it. Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 60abcb636cedf..b161b0c85d61e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -211,7 +211,6 @@ rv3028: rtc@52 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_rtc>; interrupts-extended =3D <&gpio4 1 IRQ_TYPE_LEVEL_LOW>; - trickle-diode-disable; }; }; =20 --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD422C10DC3 for ; Thu, 30 Nov 2023 16:19:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235267AbjK3QTg (ORCPT ); Thu, 30 Nov 2023 11:19:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232241AbjK3QTH (ORCPT ); Thu, 30 Nov 2023 11:19:07 -0500 Received: from mail.fris.de (mail.fris.de [116.203.77.234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33FAA1BD8; Thu, 30 Nov 2023 08:18:55 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 70E0AC0279; Thu, 30 Nov 2023 17:18:53 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361133; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=+EIj2IjkWI3q4USWXAPtd6ozG30y+26071/4C1Hd6Fk=; b=YFDm5sv2bSEJmPoFI9kunW55Scv3DoNXXkbf6B+qKcv9PzqAIjiZjbURnSSXmEHY3r6vJX dWuXblJcSQKu8z9yAjAAe6tB8RhOIkHNJlBkYKn1bBKaDLuvkfD6pzAK55RQBZlLyhmYSz m+FmVSVz6z4dbwTSM76RzMvy5XsVuVxw2IIWp+pmurPYJqLUMbN8cwPbCXbLJ/rue8LG+Z dPpTG234NPNohhWugC9BohFk2IOMV9nJ0CADvgyp+IkWDxCuwMNMmtDXIK0yk9Mvwk16t/ gzdeZgIczFaQXQCEj0X5EckZEwQNahjRpzWQEsDTgUiAQWJ9LWXxhiXp3bpGkg== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 13/14] arm64: dts: imx8mm-kontron: Add I2C EEPROM on OSM-S Kontron i.MX8MM Date: Thu, 30 Nov 2023 17:16:13 +0100 Message-ID: <20231130161657.556483-14-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf There is an EEPROM on the SoM module. Add it to the description. Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index b161b0c85d61e..6b9058fc53332 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -205,6 +205,14 @@ reg_nvcc_sd: LDO5 { }; }; =20 + eeprom: eeprom@50 { + compatible =3D "atmel,24c64"; + reg =3D <0x50>; + address-width =3D <16>; + pagesize =3D <32>; + size =3D <8192>; + }; + rv3028: rtc@52 { compatible =3D "microcrystal,rv3028"; reg =3D <0x52>; --=20 2.43.0 From nobody Tue Dec 16 16:38:10 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F226FC4167B for ; Thu, 30 Nov 2023 16:19:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345484AbjK3QTr (ORCPT ); Thu, 30 Nov 2023 11:19:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235310AbjK3QTK (ORCPT ); Thu, 30 Nov 2023 11:19:10 -0500 Received: from mail.fris.de (unknown [IPv6:2a01:4f8:c2c:390b::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C3721712; Thu, 30 Nov 2023 08:18:58 -0800 (PST) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id AEEA7C01DC; Thu, 30 Nov 2023 17:18:55 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fris.de; s=dkim; t=1701361136; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=6TZH2G8ohjq4xDcOOAHGDp4tbdOAdVYA7hBIl0Ae9a4=; b=jzfHPhbh6XgxzEzvHnBP78KANTRqY2XHIB8B/xIAtK960PXXeXKhJ3PCHhBCMhw/WuT+Fo 9jBqPZ/9IqjSh0mnJrIMMX0+algeMYXYF87fA2ZMl98Y3pV6zXXKLClhBTZqqCQYnV1/ig jdOv+NoVGun799kXVMLklp2IDxk6VesmJMNs5OP8icph0Rd/b+AfVHzpK0/oN4bjomiaDz EZ1Sfszh7wMm3WnyoWlOGgAQ9Leu3izfxxjYzR2p+ZIBe1bpQfOyPa8QZ3JtVa5AK0sP+r PMzeUjWzoAnokd9rLscsnyPHL5INJrcYH2QENdE5kK6vGsHNOsuruXAobUVxew== From: Frieder Schrempf To: Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Rob Herring , Sascha Hauer , Shawn Guo Cc: Frieder Schrempf , Fabio Estevam , NXP Linux Team , Pengutronix Kernel Team Subject: [PATCH v2 14/14] arm64: dts: imx8mm-kontron: Refactor devicetree for OSM-S module and board Date: Thu, 30 Nov 2023 17:16:14 +0100 Message-ID: <20231130161657.556483-15-frieder@fris.de> In-Reply-To: <20231130161657.556483-1-frieder@fris.de> References: <20231130161657.556483-1-frieder@fris.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Last-TLS-Session-Version: TLSv1.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Frieder Schrempf The OSM spec defines dedicated functions for all pads of the SoM. Therefore we can assume that carrier board designs stick to these definitions and extend the SoM devicetree include with matching default nodes and pinmux settings. This way we can reduce the overhead and redundancy in the carrier board devicetrees while still sticking to the policy of separating board and module description. Even if the carrier board design deviates slightly from the spec it can define its own pinmux definitions and use them as necessary or even disable unused nodes from the SoM devicetree. Signed-off-by: Frieder Schrempf --- Changes for v2: * none --- .../dts/freescale/imx8mm-kontron-bl-osm-s.dts | 269 +++------ .../dts/freescale/imx8mm-kontron-osm-s.dtsi | 552 +++++++++++++++++- 2 files changed, 616 insertions(+), 205 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts b/ar= ch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts index 12f786a72fbd5..efadfdff00af1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-bl-osm-s.dts @@ -25,8 +25,6 @@ osc_can: clock-osc-can { =20 leds { compatible =3D "gpio-leds"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_gpio_led>; =20 led1 { label =3D "led1"; @@ -52,24 +50,12 @@ pwm-beeper { =20 reg_rst_eth2: regulator-rst-eth2 { compatible =3D "regulator-fixed"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_usb_eth2>; gpio =3D <&gpio1 1 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-always-on; regulator-name =3D "rst-usb-eth2"; }; =20 - reg_usb1_vbus: regulator-usb1-vbus { - compatible =3D "regulator-fixed"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_reg_usb1_vbus>; - gpio =3D <&gpio3 25 GPIO_ACTIVE_LOW>; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - regulator-name =3D "usb1-vbus"; - }; - reg_vdd_5v: regulator-5v { compatible =3D "regulator-fixed"; regulator-always-on; @@ -80,9 +66,6 @@ reg_vdd_5v: regulator-5v { }; =20 &ecspi2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_ecspi2>; - cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; status =3D "okay"; =20 can@0 { @@ -103,9 +86,6 @@ can@0 { }; =20 &ecspi3 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_ecspi3>; - cs-gpios =3D <&gpio5 25 GPIO_ACTIVE_LOW>; status =3D "okay"; =20 eeram@0 { @@ -117,7 +97,7 @@ eeram@0 { =20 &fec1 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_enet>; + pinctrl-0 =3D <&pinctrl_enet_rgmii>; phy-connection-type =3D "rgmii-id"; phy-handle =3D <ðphy>; status =3D "okay"; @@ -136,27 +116,59 @@ ethphy: ethernet-phy@0 { }; }; =20 +/* + * Rename SoM signals according to board usage: + * GPIO_B_0 -> DIO1_OUT + * GPIO_B_1 -> DIO2_OUT + */ &gpio1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_gpio1>; - gpio-line-names =3D "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", - "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; + gpio-line-names =3D "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "DIO1_OUT", + "DIO2_OUT", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; }; =20 -&gpio5 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_gpio5>; - gpio-line-names =3D "", "", "dio4-in", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", ""; +/* + * Rename SoM signals according to board usage: + * GPIO_B_2 -> DIO3_OUT + * GPIO_B_3 -> DIO4_OUT + */ +&gpio3 { + gpio-line-names =3D "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "DIO3_OUT", + "USB_B_EN", "DIO4_OUT", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +/* + * Rename SoM signals according to board usage: + * GPIO_B_4 -> DIO1_IN + * GPIO_B_5 -> DIO2_IN + * GPIO_B_6 -> DIO3_IN + * GPIO_B_7 -> DIO4_IN + */ +&gpio4 { + gpio-line-names =3D "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "DIO1_IN", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "DIO2_IN", "DIO3_IN", + "DIO4_IN", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; }; =20 &i2c3 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_i2c3>; status =3D "okay"; =20 usb-hub@2c { @@ -169,27 +181,28 @@ usb-hub@2c { }; }; =20 -&i2c4 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_i2c4>; -}; - &pwm2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_pwm2>; status =3D "okay"; }; =20 +®_usb2_vbus { + status =3D "disabled"; +}; + +®_usdhc2_vcc { + status =3D "disabled"; +}; + +®_usdhc3_vcc { + status =3D "disabled"; +}; + &uart1 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_uart1>; uart-has-rtscts; status =3D "okay"; }; =20 &uart2 { - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_uart2>; linux,rs485-enabled-at-boot-time; uart-has-rtscts; status =3D "okay"; @@ -197,8 +210,6 @@ &uart2 { =20 &usbotg1 { dr_mode =3D "otg"; - disable-over-current; - vbus-supply =3D <®_usb1_vbus>; status =3D "okay"; }; =20 @@ -209,6 +220,9 @@ &usbotg2 { #size-cells =3D <0>; status =3D "okay"; =20 + /* VBUS is controlled by the hub */ + /delete-property/ vbus-supply; + usb1@1 { compatible =3D "usb424,2514"; reg =3D <1>; @@ -224,171 +238,20 @@ usbnet: ethernet@1 { }; =20 &usdhc2 { - pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; - pinctrl-0 =3D <&pinctrl_usdhc2>; - pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>; - pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>; vmmc-supply =3D <®_vdd_3v3>; - vqmmc-supply =3D <®_nvcc_sd>; - cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; status =3D "okay"; }; =20 &iomuxc { pinctrl_can: cangrp { fsl,pins =3D < - MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 - >; - }; - - pinctrl_ecspi2: ecspi2grp { - fsl,pins =3D < - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 - >; - }; - - pinctrl_ecspi3: ecspi3grp { - fsl,pins =3D < - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins =3D < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* PHY RST */ - >; - }; - - pinctrl_gpio_led: gpioledgrp { - fsl,pins =3D < - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 - >; - }; - - pinctrl_gpio1: gpio1grp { - fsl,pins =3D < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 - >; - }; - - pinctrl_gpio5: gpio5grp { - fsl,pins =3D < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins =3D < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins =3D < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 - >; - }; - - pinctrl_pwm2: pwm2grp { - fsl,pins =3D < - MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 - >; - }; - - pinctrl_reg_usb1_vbus: regusb1vbusgrp { - fsl,pins =3D < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins =3D < - MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 - MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 - MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 - MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins =3D < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 - >; - }; - - pinctrl_usb_eth2: usbeth2grp { - fsl,pins =3D < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ >; }; =20 - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + pinctrl_usb_hub: usbhubgrp { fsl,pins =3D < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi b/arch= /arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi index 6b9058fc53332..1a5c29565e7fe 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-osm-s.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2022 Kontron Electronics GmbH */ =20 +#include #include #include "imx8mm.dtsi" =20 @@ -28,6 +29,73 @@ memory@40000000 { chosen { stdout-path =3D &uart3; }; + + reg_vdd_carrier: regulator-vdd-carrier { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_vdd_carrier>; + enable-active-high; + gpio =3D <&gpio3 16 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-name =3D "VDD_CARRIER"; + + regulator-state-standby { + regulator-on-in-suspend; + }; + + regulator-state-mem { + regulator-off-in-suspend; + }; + + regulator-state-disk { + regulator-off-in-suspend; + }; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb1_vbus>; + enable-active-high; + gpio =3D <&gpio3 25 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "VBUS_USB1"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usb2_vbus>; + enable-active-high; + gpio =3D <&gpio3 20 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-name =3D "VBUS_USB2"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc2_vcc>; + enable-active-high; + gpio =3D <&gpio2 19 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "VCC_SDIO_A"; + }; + + reg_usdhc3_vcc: regulator-usdhc3-vcc { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_reg_usdhc3_vcc>; + enable-active-high; + gpio =3D <&gpio5 1 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "VCC_SDIO_B"; + }; }; =20 &A53_0 { @@ -96,6 +164,79 @@ partition@1f0000 { }; }; =20 +&ecspi2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi2>, <&pinctrl_ecspi2_gpio>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; +}; + +&ecspi3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ecspi3>; + cs-gpios =3D <&gpio5 25 GPIO_ACTIVE_LOW>; +}; + +&gpio1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio1>; + gpio-line-names =3D "", "GPIO_A_0", "", "GPIO_A_1", + "", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4", + "GPIO_A_5", "GPIO_A_6", "GPIO_A_7", "GPIO_B_0", + "GPIO_B_1", "USB_A_OC#", "CAM_MCK", "USB_B_OC#", + "ETH_MDC", "ETH_MDIO", "ETH_A_(S)(R)(G)MII_TXD3", + "ETH_A_(S)(R)(G)MII_TXD2", "ETH_A_(S)(R)(G)MII_TXD1", + "ETH_A_(S)(R)(G)MII_TXD0", "ETH_A_(R)(G)MII_TX_EN(_ER)", + "ETH_A_(R)(G)MII_TX_CLK", "ETH_A_(R)(G)MII_RX_DV(_ER)", + "ETH_A_(R)(G)MII_RX_CLK", "ETH_A_(S)(R)(G)MII_RXD0", + "ETH_A_(S)(R)(G)MII_RXD1", "ETH_A_(R)(G)MII_RXD2", + "ETH_A_(R)(G)MII_RXD3"; +}; + +&gpio2 { + gpio-line-names =3D "", "", "", "", + "", "", "", "", + "", "", "", "", + "SDIO_A_CD#", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0", + "SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN", + "SDIO_A_WP"; +}; + +&gpio3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio3>; + gpio-line-names =3D "GPIO_C_5", "GPIO_C_4", "SDIO_B_CD#", "SDIO_B_D5", + "SDIO_B_D6", "SDIO_B_D7", "GPIO_C_0", "GPIO_C_1", + "GPIO_C_2", "GPIO_C_3", "SDIO_B_D0", "SDIO_B_D1", + "SDIO_B_D2", "SDIO_B_D3", "", "SDIO_B_D4", + "CARRIER_PWR_EN", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_2", + "USB_B_EN", "GPIO_B_3", "PCIe_CLKREQ#", "PCIe_A_PERST#", + "PCIe_WAKE#", "USB_A_EN"; +}; + +&gpio4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_gpio4>; + gpio-line-names =3D "GPIO_C_7", "", "I2S_A_DATA_IN", "I2S_B_DATA_IN", + "GPIO_B_4", "BOOT_SEL0#", "BOOT_SEL1#", "", + "", "", "I2S_LRCLK", "I2S_BITCLK", + "I2S_A_DATA_OUT", "I2S_B_DATA_OUT", "GPIO_B_5", "GPIO_B_6", + "GPIO_B_7", "SPI_A_/WP_(IO2)", "SPI_A_/HOLD_(IO3)", "GPIO_C_6", + "I2S_MCLK", "UART_A_TX", "UART_A_RX", "UART_A_CTS", + "UART_A_RTS", "", "", "", + "PCIe_SM_ALERT", "UART_B_RTS", "UART_B_CTS", "UART_B_RX"; +}; + +&gpio5 { + gpio-line-names =3D "UART_B_TX", "SDIO_B_PWR_EN", "SDIO_B_WP", "PWM_2", + "PWM_1", "PWM_0", "", "", + "", "", "SPI_A_SCK", "SPI_A_SDO_(IO1)", + "SPI_A_SCK", "SPI_A_CS0#", "", "", + "I2C_A_SCL", "I2C_A_SDA", "I2C_B_SCL", "I2C_B_SDA", + "PCIe_SMCLK", "PCIe_SMDAT", "SPI_B_SCK", "SPI_B_SDO", + "SPI_B_SDI", "SPI_B_CS0#", "UART_CON_RX", "UART_CON_TX", + "UART_C_RX", "UART_C_TX"; +}; + &i2c1 { clock-frequency =3D <400000>; pinctrl-names =3D "default"; @@ -222,12 +363,69 @@ rv3028: rtc@52 { }; }; =20 +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; +}; + +&i2c4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c4>; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm1>; +}; + +&pwm2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm2>; +}; + +&pwm3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pwm3>; +}; + +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart1>; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; +}; + &uart3 { /* console */ pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_uart3>; status =3D "okay"; }; =20 +&uart4 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart4>; +}; + +&usbotg1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1>; + vbus-supply =3D <®_usb1_vbus>; +}; + +&usbotg2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb2>; + vbus-supply =3D <®_usb2_vbus>; +}; + &usdhc1 { pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; pinctrl-0 =3D <&pinctrl_usdhc1>; @@ -240,6 +438,26 @@ &usdhc1 { status =3D "okay"; }; =20 +&usdhc2 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply =3D <®_usdhc2_vcc>; + vqmmc-supply =3D <®_nvcc_sd>; + cd-gpios =3D <&gpio2 12 GPIO_ACTIVE_LOW>; +}; + +&usdhc3 { + pinctrl-names =3D "default", "state_100mhz", "state_200mhz"; + pinctrl-0 =3D <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 =3D <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 =3D <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + vmmc-supply =3D <®_usdhc3_vcc>; + vqmmc-supply =3D <®_nvcc_sd>; + cd-gpios =3D <&gpio3 2 GPIO_ACTIVE_LOW>; +}; + &wdog1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_wdog>; @@ -248,6 +466,12 @@ &wdog1 { }; =20 &iomuxc { + pinctrl_csi_mck: csimckgrp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 /* CAM_MCK */ + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins =3D < MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 @@ -257,6 +481,106 @@ MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 >; }; =20 + pinctrl_ecspi2: ecspi2grp { + fsl,pins =3D < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 /* SPI_A_SDI_(IO0) */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 /* SPI_A_SDO_(IO1) */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 /* SPI_A_SCK */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 /* SPI_A_CS0# */ + >; + }; + + pinctrl_ecspi2_gpio: ecspi2gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* SPI_A_/WP_(IO2) */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* SPI_A_/HOLD_(IO3) */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 /* SPI_B_SDI */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 /* SPI_B_SDO */ + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 /* SPI_B_SCK */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 /* SPI_B_CS0# */ + >; + }; + + pinctrl_enet_rgmii: enetrgmiigrp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 = */ + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 = */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 = */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 = */ + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */ + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 = */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 = */ + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_= DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_= EN(_ER) */ + >; + }; + + pinctrl_enet_rmii: enetrmiigrp { + fsl,pins =3D < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x03 /* ETH_MDC */ + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x03 /* ETH_MDIO */ + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f /* ETH_A_(S)(R)(G)MII_TX= D2 */ + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 /* ETH_A_(S)(R)(G)MII_TXD1 = */ + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 /* ETH_A_(S)(R)(G)MII_TXD0 = */ + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 /* ETH_A_(S)(R)(G)MII_RXD1 = */ + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 /* ETH_A_(S)(R)(G)MII_RXD0 = */ + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 /* ETH_A_(R)(G)MII_RX_CLK */ + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 /* ETH_A_(R)(G)MII_RX_= DV(_ER) */ + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 /* ETH_A_(R)(G)MII_TX_= EN(_ER) */ + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* GPIO_A_0 */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* GPIO_A_1 */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* GPIO_A_2 */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* GPIO_A_3 */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 /* GPIO_A_4 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 /* GPIO_A_5 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* GPIO_A_6 */ + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* GPIO_A_7 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* GPIO_B_0 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* GPIO_B_1 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* GPIO_C_5 */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* GPIO_C_4 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* GPIO_C_0 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* GPIO_C_1 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* GPIO_C_2 */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* GPIO_C_3 */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* GPIO_B_2 */ + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* GPIO_B_3 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* GPIO_C_7 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* GPIO_B_4 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* BOOT_SEL0# */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* BOOT_SEL1# */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* GPIO_B_5 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* GPIO_B_6 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* GPIO_B_7 */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* GPIO_C_6 */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins =3D < MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000083 @@ -264,22 +588,149 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000083 >; }; =20 + pinctrl_i2c2: i2c2grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083 /* I2C_A_SCL */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083 /* I2C_A_SDA */ + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083 /* I2C_B_SCL */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083 /* I2C_B_SDA */ + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins =3D < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083 /* PCIe_SMCLK and I2C_CAM_S= CL/CSI_TX_P */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000083 /* PCIe_SMDAT and I2C_CAM_S= DA/CSI_TX_N */ + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* PCIe_CLKREQ# */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* PCIe_A_PERST# */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* PCIe_WAKE# */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* PCIe_SM_ALERT */ + >; + }; + pinctrl_pmic: pmicgrp { fsl,pins =3D < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 >; }; =20 + pinctrl_pwm1: pwm1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x19 /* PWM_0 */ + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 /* PWM_1 */ + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins =3D < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x19 /* PWM_2 */ + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* USB_A_EN */ + >; + }; + + pinctrl_reg_usb2_vbus: regusb2vbusgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* USB_B_EN */ + >; + }; + + pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */ + >; + }; + + pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19 /* SDIO_B_PWR_EN */ + >; + }; + + pinctrl_reg_vdd_carrier: regvddcarriergrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* CARRIER_PWR_EN */ + >; + }; + pinctrl_rtc: rtcgrp { fsl,pins =3D < MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 >; }; =20 + pinctrl_sai1: sai1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6 /* I2S_A_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 /* I2S_A_DATA_OUT */ + MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6 /* I2S_B_DATA_IN */ + MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 /* I2S_B_DATA_OUT */ + MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 /* I2S_MCLK */ + MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 /* I2S_LRCLK */ + MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 /* I2S_BITCLK */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0 /* UART_A_RX */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x0 /* UART_A_TX */ + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x0 /* UART_A_CTS */ + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x0 /* UART_A_RTS */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x0 /* UART_B_RX */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x0 /* UART_B_TX */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x0 /* UART_B_CTS */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x0 /* UART_B_RTS */ + >; + }; + pinctrl_uart3: uart3grp { fsl,pins =3D < - MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 - MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 /* UART_CON_RX */ + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 /* UART_CON_TX */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins =3D < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x0 /* UART_C_RX */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x0 /* UART_C_TX */ + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x19 /* USB_A_OC# */ + >; + }; + + pinctrl_usb2: usb2grp { + fsl,pins =3D < + MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC 0x19 /* USB_B_OC# */ >; }; =20 @@ -334,6 +785,103 @@ MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 >; }; =20 + pinctrl_usdhc2: usdhc2grp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 /* SDIO_A_CLK */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 /* SDIO_A_CMD */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 /* SDIO_A_CD# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x90 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x90 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x90 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x90 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x90 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x90 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x90 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x90 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x90 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x90 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x94 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x94 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x94 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x94 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x94 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x94 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x94 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x94 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x94 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x94 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x96 /* SDIO_B_CLK */ + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x96 /* SDIO_B_CMD */ + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x96 /* SDIO_B_D0 */ + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x96 /* SDIO_B_D1 */ + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x96 /* SDIO_B_D2 */ + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x96 /* SDIO_B_D3 */ + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x96 /* SDIO_B_D4 */ + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x96 /* SDIO_B_D5 */ + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x96 /* SDIO_B_D6 */ + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x96 /* SDIO_B_D7 */ + >; + }; + + pinctrl_usdhc3_gpio: usdhc3gpiogrp { + fsl,pins =3D < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 /* SDIO_B_CD# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 /* SDIO_B_WP */ + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins =3D < MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 --=20 2.43.0