From nobody Wed Dec 17 00:12:47 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF603C4167B for ; Thu, 30 Nov 2023 12:24:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345421AbjK3MYM (ORCPT ); Thu, 30 Nov 2023 07:24:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345413AbjK3MYJ (ORCPT ); Thu, 30 Nov 2023 07:24:09 -0500 Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.220]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EF7A2D50; Thu, 30 Nov 2023 04:24:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=163.com; s=s110527; h=From:Subject:Date:Message-Id:MIME-Version; bh=CidyQ kcUSbONLGLqzG4G3Rj/C0GIJ8owu1w28R+5hkg=; b=gcmVx4gBcr5urmN8Ub31R FGl507aEjl6z0nnX/cvJkv4Og8mUzcq+NGQeH5JsEbiNaTqfbTkY/ieZjnhNtJWZ iD6N/8MpTcAYbRC5ebu9XGnyDt1xaPNf1isJs8NISjams4TeJnGPMb9P2nlj7QCh r0RuPKFO6k6TcOTgBFkecA= Received: from ProDesk.. (unknown [58.22.7.114]) by zwqz-smtp-mta-g1-3 (Coremail) with SMTP id _____wD3PxjQfmhlDnD1BA--.61445S2; Thu, 30 Nov 2023 20:23:47 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, Andy Yan Subject: [PATCH v3 06/14] drm/rockchip: vop2: Set YUV/RGB overlay mode Date: Thu, 30 Nov 2023 20:23:42 +0800 Message-Id: <20231130122342.13072-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231130122001.12474-1-andyshrk@163.com> References: <20231130122001.12474-1-andyshrk@163.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3PxjQfmhlDnD1BA--.61445S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxXr18XrWkAFyrWFW3Ww47XFb_yoWrAw1kpw n7ZryYqrWDKF4qqw1kAF98ZF4Skw4Iyay7GFn7Gasxua4vgryDWwnxuas8AFnrXF17urWj yrZrCrW5AF4Ivr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jo5lbUUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiqBU4XmVOAquTBAAAsO Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Andy Yan Set overlay mode register according to the output mode is yuv or rgb. Signed-off-by: Andy Yan --- Changes in v3: - put bool variable yuv_overlay next to other bool variable - define macro for RK3568_OVL_CTRL__YUV_MODE - just write RK3568_OVL_CTRL register once in function vop2_setup_layer_mixer drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 18 +++++++++++++++--- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 1 + 3 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/= rockchip/rockchip_drm_drv.h index 3d8ab2defa1b..bbb9e0bf6804 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -48,6 +48,7 @@ struct rockchip_crtc_state { int output_bpc; int output_flags; bool enable_afbc; + bool yuv_overlay; u32 bus_format; u32 bus_flags; int color_space; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 25c1f33c5622..40b5c5ca4864 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1623,6 +1623,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, =20 vop2->enable_count++; =20 + vcstate->yuv_overlay =3D is_yuv_output(vcstate->bus_format); + vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); =20 polflags =3D 0; @@ -1650,7 +1652,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *= crtc, if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) dsp_ctrl |=3D RK3568_VP_DSP_CTRL__DSP_RB_SWAP; =20 - if (is_yuv_output(vcstate->bus_format)) + if (vcstate->yuv_overlay) dsp_ctrl |=3D RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; =20 vop2_dither_setup(crtc, &dsp_ctrl); @@ -1959,10 +1961,12 @@ static void vop2_setup_layer_mixer(struct vop2_vide= o_port *vp) u16 hdisplay; u32 bg_dly; u32 pre_scan_dly; + u32 ovl_ctrl; int i; struct vop2_video_port *vp0 =3D &vop2->vps[0]; struct vop2_video_port *vp1 =3D &vop2->vps[1]; struct vop2_video_port *vp2 =3D &vop2->vps[2]; + struct rockchip_crtc_state *vcstate =3D to_rockchip_crtc_state(vp->crtc.s= tate); =20 adjusted_mode =3D &vp->crtc.state->adjusted_mode; hsync_len =3D adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_s= tart; @@ -1975,7 +1979,15 @@ static void vop2_setup_layer_mixer(struct vop2_video= _port *vp) pre_scan_dly =3D ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); =20 - vop2_writel(vop2, RK3568_OVL_CTRL, 0); + ovl_ctrl =3D vop2_readl(vop2, RK3568_OVL_CTRL); + ovl_ctrl |=3D RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD; + if (vcstate->yuv_overlay) + ovl_ctrl |=3D RK3568_OVL_CTRL__YUV_MODE(vp->id); + else + ovl_ctrl &=3D ~RK3568_OVL_CTRL__YUV_MODE(vp->id); + + vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl); + port_sel =3D vop2_readl(vop2, RK3568_OVL_PORT_SEL); port_sel &=3D RK3568_OVL_PORT_SEL__SEL_PORT; =20 @@ -2047,9 +2059,9 @@ static void vop2_setup_layer_mixer(struct vop2_video_= port *vp) layer_sel |=3D RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); } =20 + vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); - vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD); } =20 static void vop2_setup_dly_for_windows(struct vop2 *vop2) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.h index 7175f46a2014..8d7ff52523fb 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -401,6 +401,7 @@ enum dst_factor_mode { #define VOP2_COLOR_KEY_MASK BIT(31) =20 #define RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD BIT(28) +#define RK3568_OVL_CTRL__YUV_MODE(vp) BIT(vp) =20 #define RK3568_VP_BG_MIX_CTRL__BG_DLY GENMASK(31, 24) =20 --=20 2.34.1