From nobody Tue Dec 16 19:53:43 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE7C8C4167B for ; Wed, 29 Nov 2023 22:22:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343683AbjK2WV5 (ORCPT ); Wed, 29 Nov 2023 17:21:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234881AbjK2WVf (ORCPT ); Wed, 29 Nov 2023 17:21:35 -0500 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 879BFD1; Wed, 29 Nov 2023 14:21:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1701296501; x=1732832501; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hucH4KP50LXX2Kh5Iz88BOSFqM6zBFgUJz7knousSUg=; b=PL6uyjrY0XAW8WTTHb5NlPKacI2RLv+nNPap4IsudQFlGqkanyfnDUHp zkRZvnhvfRRZQr3KcOGV5zV0cdkmdjIJoP/+OO7ENEgRGN6oE0y/X5QG8 WMcXbpBfLaJd10zUlRy/iD7qF1lg9FazSGshx2AWTBajDVjJVVOjVmBFl RXkBU1Qlvn4/KbkDoq+aJYpfdfrQFgLoMBX1OXNEDjnfg6MCpiINRoFjI ec1A+g7lLYvGY3XyeCQcBdFhEnwYHp63Ebhz9wPHkmMxppUJXbzTXSSdZ HouWaDMeT3Vmmo+egb9cnAj3vn2pTTwexAmc9XRgfJKyIfuGIoRlLHxG9 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="11937004" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="11937004" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10909"; a="798070422" X-IronPort-AV: E=Sophos;i="6.04,237,1695711600"; d="scan'208";a="798070422" Received: from linux.intel.com ([10.54.29.200]) by orsmga008.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Nov 2023 14:21:33 -0800 Received: from debox1-desk4.lan (unknown [10.209.108.167]) by linux.intel.com (Postfix) with ESMTP id A094C5807E2; Wed, 29 Nov 2023 14:21:33 -0800 (PST) From: "David E. Box" To: linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, ilpo.jarvinen@linux.intel.com, rajvi.jingar@linux.intel.com Subject: [PATCH V6 08/20] platform/x86/intel/vsec: Add base address field Date: Wed, 29 Nov 2023 14:21:20 -0800 Message-Id: <20231129222132.2331261-9-david.e.box@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231129222132.2331261-1-david.e.box@linux.intel.com> References: <20231129222132.2331261-1-david.e.box@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some devices may emulate PCI VSEC capabilities in MMIO. In such cases the BAR is not readable from a config space. Provide a field for drivers to indicate the base address to be used. Signed-off-by: David E. Box Reviewed-by: Ilpo J=C3=A4rvinen --- V6 - No change V5 - No change V4 - No change V3 - No change V2 - No change drivers/platform/x86/intel/pmt/class.c | 14 +++++++++++--- drivers/platform/x86/intel/vsec.c | 10 ++++++++-- drivers/platform/x86/intel/vsec.h | 2 ++ 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/platform/x86/intel/pmt/class.c b/drivers/platform/x86/= intel/pmt/class.c index 2ad91d2fd954..32608baaa56c 100644 --- a/drivers/platform/x86/intel/pmt/class.c +++ b/drivers/platform/x86/intel/pmt/class.c @@ -160,10 +160,11 @@ static struct class intel_pmt_class =3D { =20 static int intel_pmt_populate_entry(struct intel_pmt_entry *entry, struct intel_pmt_header *header, - struct device *dev, + struct intel_vsec_device *ivdev, struct resource *disc_res) { - struct pci_dev *pci_dev =3D to_pci_dev(dev->parent); + struct pci_dev *pci_dev =3D ivdev->pcidev; + struct device *dev =3D &ivdev->auxdev.dev; u8 bir; =20 /* @@ -215,6 +216,13 @@ static int intel_pmt_populate_entry(struct intel_pmt_e= ntry *entry, =20 break; case ACCESS_BARID: + /* Use the provided base address if it exists */ + if (ivdev->base_addr) { + entry->base_addr =3D ivdev->base_addr + + GET_ADDRESS(header->base_offset); + break; + } + /* * If another BAR was specified then the base offset * represents the offset within that BAR. SO retrieve the @@ -319,7 +327,7 @@ int intel_pmt_dev_create(struct intel_pmt_entry *entry,= struct intel_pmt_namespa if (ret) return ret; =20 - ret =3D intel_pmt_populate_entry(entry, &header, dev, disc_res); + ret =3D intel_pmt_populate_entry(entry, &header, intel_vsec_dev, disc_res= ); if (ret) return ret; =20 diff --git a/drivers/platform/x86/intel/vsec.c b/drivers/platform/x86/intel= /vsec.c index 2978d4e95bb0..648ee842d413 100644 --- a/drivers/platform/x86/intel/vsec.c +++ b/drivers/platform/x86/intel/vsec.c @@ -153,6 +153,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, str= uct intel_vsec_header *he struct resource *tmp; struct device *parent; unsigned long quirks =3D info->quirks; + u64 base_addr; int i; =20 if (info->parent) @@ -184,14 +185,18 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, s= truct intel_vsec_header *he if (quirks & VSEC_QUIRK_TABLE_SHIFT) header->offset >>=3D TABLE_OFFSET_SHIFT; =20 + if (info->base_addr) + base_addr =3D info->base_addr; + else + base_addr =3D pdev->resource[header->tbir].start; + /* * The DVSEC/VSEC contains the starting offset and count for a block of * discovery tables. Create a resource array of these tables to the * auxiliary device driver. */ for (i =3D 0, tmp =3D res; i < header->num_entries; i++, tmp++) { - tmp->start =3D pdev->resource[header->tbir].start + - header->offset + i * (header->entry_size * sizeof(u32)); + tmp->start =3D base_addr + header->offset + i * (header->entry_size * si= zeof(u32)); tmp->end =3D tmp->start + (header->entry_size * sizeof(u32)) - 1; tmp->flags =3D IORESOURCE_MEM; =20 @@ -206,6 +211,7 @@ static int intel_vsec_add_dev(struct pci_dev *pdev, str= uct intel_vsec_header *he intel_vsec_dev->resource =3D no_free_ptr(res); intel_vsec_dev->num_resources =3D header->num_entries; intel_vsec_dev->quirks =3D info->quirks; + intel_vsec_dev->base_addr =3D info->base_addr; =20 if (header->id =3D=3D VSEC_ID_SDSI) intel_vsec_dev->ida =3D &intel_vsec_sdsi_ida; diff --git a/drivers/platform/x86/intel/vsec.h b/drivers/platform/x86/intel= /vsec.h index bb8b6452df70..e23e76129691 100644 --- a/drivers/platform/x86/intel/vsec.h +++ b/drivers/platform/x86/intel/vsec.h @@ -73,6 +73,7 @@ struct intel_vsec_platform_info { struct intel_vsec_header **headers; unsigned long caps; unsigned long quirks; + u64 base_addr; }; =20 struct intel_vsec_device { @@ -85,6 +86,7 @@ struct intel_vsec_device { void *priv_data; size_t priv_data_size; unsigned long quirks; + u64 base_addr; }; =20 int intel_vsec_add_aux(struct pci_dev *pdev, struct device *parent, --=20 2.34.1