From nobody Wed Dec 17 07:31:00 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3592CC4167B for ; Wed, 29 Nov 2023 13:58:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234310AbjK2Nkn (ORCPT ); Wed, 29 Nov 2023 08:40:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234096AbjK2Nk3 (ORCPT ); Wed, 29 Nov 2023 08:40:29 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77EE2C1 for ; Wed, 29 Nov 2023 05:40:35 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-40b538d5c4eso4440215e9.1 for ; Wed, 29 Nov 2023 05:40:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1701265234; x=1701870034; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xVKCchg4ZSZgpZLnFcgq1r1U/HQTY8Hn5xE1KnUJS9E=; b=cmL4Cw75zKTdxsFFyEb/zV6FhBTkegNyIi4nqcMjgbawC2A8fb9sKrYtvVGrZXYz/r 16RvvAOagQxvRugOIIyZQu21MuD48xvkO1tdkSF4TC+WX/2Wu9/U3z0pdf+0dOOszCdu 5IUkfMav4spdRpFDshwAlTJGvifUi/yec9+CkUQVHoPbThnbcZ///Lwv/6vpB0/X87fJ pg0C9ljN+zCK4QGrNl+fL5GNSZZEAlh8/khx16H6YUD2E/H1N3SnBWaC1ZKNtTl4FNZ0 16yEaA0H+3lijdKyvGyFGzCurlBz9k40FuGR2bKyBLg4KrSVjlZxB1CA8b5w+ho1hw1L HNrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701265234; x=1701870034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xVKCchg4ZSZgpZLnFcgq1r1U/HQTY8Hn5xE1KnUJS9E=; b=MnEBnTqo1rVGOxwJsu6elLA7xYk2RT7HJXVi8uir6iGqVSAUKYEURhM1o15Ui9/cIE +3djqopZWIBkyw/G/GdclgMe1Sdx8QZE9fI3O94m2S3qTkK4NSQh7AfdryeDXtx9EpTn cGuy9BTihaSDpafTvXDf/MtEK9S8TsAalmCM4HSWqVPfOHzCT1lnQaFZUWE3pfQU0oZQ fl4xhueWBkgjuHwzen/uxerlcWjIQFoZZolj4+HiGOUqjAg6uGRjPvo26gN0+bbK+s9O X4fKcPgENk0/B7lz8RTXWS2KrvR/n1AYLAxkFeMv8zPgujM+6Wi9l8dLPUdm0d82z/M1 bVlQ== X-Gm-Message-State: AOJu0Yx4+EFJUEVnLbGX/KAnWGwmlpGxZ74u/hT++M+fCH1Q5DlFwqvp V9ld9Tb/WzytWPFNzRhVAx+myA== X-Google-Smtp-Source: AGHT+IHm0KALrSqk206CpxoCAMZGSyTzUrx2fa+hLgKKqO8w4D4vGEOPDLk/yITyoQcEKc8XiS3h7w== X-Received: by 2002:a05:600c:a0b:b0:406:52f1:7e6f with SMTP id z11-20020a05600c0a0b00b0040652f17e6fmr15256657wmp.12.1701265233844; Wed, 29 Nov 2023 05:40:33 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:6101:5529:fe2d:d7eb]) by smtp.googlemail.com with ESMTPSA id w17-20020a05600c475100b004080f0376a0sm2285860wmo.42.2023.11.29.05.40.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Nov 2023 05:40:33 -0800 (PST) From: Jerome Brunet To: Thierry Reding , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Subject: [PATCH v3 4/4] pwm: meson: add generic compatible for meson8 to sm1 Date: Wed, 29 Nov 2023 14:40:00 +0100 Message-ID: <20231129134004.3642121-5-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231129134004.3642121-1-jbrunet@baylibre.com> References: <20231129134004.3642121-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce a new compatible support in the Amlogic PWM driver. The PWM HW is actually the same for all SoCs supported so far. A specific compatible is needed only because the clock sources of the PWMs are hard-coded in the driver. It is better to have the clock source described in DT but this changes the bindings so a new compatible must be introduced. When all supported platform have migrated to the new compatible, support for the legacy ones may be removed from the driver. Adding a callback to setup the clock will also make it easier to add support for the new PWM HW found in a1, s4, c3 and t7 SoC families. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 224 ++++++++++++++++++++++++---------------- 1 file changed, 133 insertions(+), 91 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 5cbd65cae28a..d5d745a651d3 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -95,6 +95,7 @@ struct meson_pwm_channel { =20 struct meson_pwm_data { const char * const *parent_names; + int (*channels_init)(struct device *dev); }; =20 struct meson_pwm { @@ -333,95 +334,6 @@ static const struct pwm_ops meson_pwm_ops =3D { .get_state =3D meson_pwm_get_state, }; =20 -static const char * const pwm_meson8b_parent_names[] =3D { - "xtal", NULL, "fclk_div4", "fclk_div3" -}; - -static const struct meson_pwm_data pwm_meson8b_data =3D { - .parent_names =3D pwm_meson8b_parent_names, -}; - -/* - * Only the 2 first inputs of the GXBB AO PWMs are valid - * The last 2 are grounded - */ -static const char * const pwm_gxbb_ao_parent_names[] =3D { - "xtal", "clk81", NULL, NULL, -}; - -static const struct meson_pwm_data pwm_gxbb_ao_data =3D { - .parent_names =3D pwm_gxbb_ao_parent_names, -}; - -static const char * const pwm_axg_ee_parent_names[] =3D { - "xtal", "fclk_div5", "fclk_div4", "fclk_div3" -}; - -static const struct meson_pwm_data pwm_axg_ee_data =3D { - .parent_names =3D pwm_axg_ee_parent_names, -}; - -static const char * const pwm_axg_ao_parent_names[] =3D { - "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" -}; - -static const struct meson_pwm_data pwm_axg_ao_data =3D { - .parent_names =3D pwm_axg_ao_parent_names, -}; - -static const char * const pwm_g12a_ao_ab_parent_names[] =3D { - "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" -}; - -static const struct meson_pwm_data pwm_g12a_ao_ab_data =3D { - .parent_names =3D pwm_g12a_ao_ab_parent_names, -}; - -static const char * const pwm_g12a_ao_cd_parent_names[] =3D { - "xtal", "g12a_ao_clk81", NULL, NULL, -}; - -static const struct meson_pwm_data pwm_g12a_ao_cd_data =3D { - .parent_names =3D pwm_g12a_ao_cd_parent_names, -}; - -static const struct of_device_id meson_pwm_matches[] =3D { - { - .compatible =3D "amlogic,meson8b-pwm", - .data =3D &pwm_meson8b_data - }, - { - .compatible =3D "amlogic,meson-gxbb-pwm", - .data =3D &pwm_meson8b_data - }, - { - .compatible =3D "amlogic,meson-gxbb-ao-pwm", - .data =3D &pwm_gxbb_ao_data - }, - { - .compatible =3D "amlogic,meson-axg-ee-pwm", - .data =3D &pwm_axg_ee_data - }, - { - .compatible =3D "amlogic,meson-axg-ao-pwm", - .data =3D &pwm_axg_ao_data - }, - { - .compatible =3D "amlogic,meson-g12a-ee-pwm", - .data =3D &pwm_meson8b_data - }, - { - .compatible =3D "amlogic,meson-g12a-ao-pwm-ab", - .data =3D &pwm_g12a_ao_ab_data - }, - { - .compatible =3D "amlogic,meson-g12a-ao-pwm-cd", - .data =3D &pwm_g12a_ao_cd_data - }, - {}, -}; -MODULE_DEVICE_TABLE(of, meson_pwm_matches); - static int meson_pwm_init_clocks_legacy(struct device *dev, struct clk_parent_data *mux_parent_data) { @@ -528,12 +440,15 @@ static int meson_pwm_init_clocks_legacy(struct device= *dev, return 0; } =20 -static int meson_pwm_init_channels(struct device *dev) +static int meson_pwm_init_channels_legacy(struct device *dev) { struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] =3D {}; struct meson_pwm *meson =3D dev_get_drvdata(dev); int i; =20 + dev_info(dev, "using obsolete compatible, please consider updating dt\n"); + + for (i =3D 0; i < MESON_NUM_MUX_PARENTS; i++) { mux_parent_data[i].index =3D -1; mux_parent_data[i].name =3D meson->data->parent_names[i]; @@ -542,6 +457,133 @@ static int meson_pwm_init_channels(struct device *dev) return meson_pwm_init_clocks_legacy(dev, mux_parent_data); } =20 +static int meson_pwm_init_channels_meson8b_v2(struct device *dev) +{ + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] =3D {}; + int i; + + /* + * NOTE: Instead of relying on the hard coded names in the driver + * as the legacy version, this relies on DT to provide the list of + * clocks. + * For once, using input numbers actually makes more sense than names. + * Also DT requires clock-names to be explicitly ordered, so there is + * no point bothering with clock names in this case. + */ + for (i =3D 0; i < MESON_NUM_MUX_PARENTS; i++) + mux_parent_data[i].index =3D i; + + return meson_pwm_init_clocks_legacy(dev, mux_parent_data); +} + +static const char * const pwm_meson8b_parent_names[] =3D { + "xtal", NULL, "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_meson8b_data =3D { + .parent_names =3D pwm_meson8b_parent_names, + .channels_init =3D meson_pwm_init_channels_legacy, +}; + +/* + * Only the 2 first inputs of the GXBB AO PWMs are valid + * The last 2 are grounded + */ +static const char * const pwm_gxbb_ao_parent_names[] =3D { + "xtal", "clk81", NULL, NULL, +}; + +static const struct meson_pwm_data pwm_gxbb_ao_data =3D { + .parent_names =3D pwm_gxbb_ao_parent_names, + .channels_init =3D meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_axg_ee_parent_names[] =3D { + "xtal", "fclk_div5", "fclk_div4", "fclk_div3" +}; + +static const struct meson_pwm_data pwm_axg_ee_data =3D { + .parent_names =3D pwm_axg_ee_parent_names, + .channels_init =3D meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_axg_ao_parent_names[] =3D { + "xtal", "axg_ao_clk81", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_axg_ao_data =3D { + .parent_names =3D pwm_axg_ao_parent_names, + .channels_init =3D meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_g12a_ao_ab_parent_names[] =3D { + "xtal", "g12a_ao_clk81", "fclk_div4", "fclk_div5" +}; + +static const struct meson_pwm_data pwm_g12a_ao_ab_data =3D { + .parent_names =3D pwm_g12a_ao_ab_parent_names, + .channels_init =3D meson_pwm_init_channels_legacy, +}; + +static const char * const pwm_g12a_ao_cd_parent_names[] =3D { + "xtal", "g12a_ao_clk81", NULL, NULL, +}; + +static const struct meson_pwm_data pwm_g12a_ao_cd_data =3D { + .parent_names =3D pwm_g12a_ao_cd_parent_names, + .channels_init =3D meson_pwm_init_channels_legacy, +}; + +static const struct meson_pwm_data pwm_meson8_v2_data =3D { + .channels_init =3D meson_pwm_init_channels_meson8b_v2, +}; + +static const struct of_device_id meson_pwm_matches[] =3D { + { + .compatible =3D "amlogic,meson8-pwm-v2", + .data =3D &pwm_meson8_v2_data + }, + /* + * The following compatibles are obsolete. + * Support for these may be removed once the related + * platforms have been updated + */ + { + .compatible =3D "amlogic,meson8b-pwm", + .data =3D &pwm_meson8b_data + }, + { + .compatible =3D "amlogic,meson-gxbb-pwm", + .data =3D &pwm_meson8b_data + }, + { + .compatible =3D "amlogic,meson-gxbb-ao-pwm", + .data =3D &pwm_gxbb_ao_data + }, + { + .compatible =3D "amlogic,meson-axg-ee-pwm", + .data =3D &pwm_axg_ee_data + }, + { + .compatible =3D "amlogic,meson-axg-ao-pwm", + .data =3D &pwm_axg_ao_data + }, + { + .compatible =3D "amlogic,meson-g12a-ee-pwm", + .data =3D &pwm_meson8b_data + }, + { + .compatible =3D "amlogic,meson-g12a-ao-pwm-ab", + .data =3D &pwm_g12a_ao_ab_data + }, + { + .compatible =3D "amlogic,meson-g12a-ao-pwm-cd", + .data =3D &pwm_g12a_ao_cd_data + }, + {}, +}; +MODULE_DEVICE_TABLE(of, meson_pwm_matches); + static int meson_pwm_probe(struct platform_device *pdev) { struct meson_pwm *meson; @@ -573,7 +615,7 @@ static int meson_pwm_probe(struct platform_device *pdev) return -ENODEV; } =20 - err =3D meson_pwm_init_channels(&pdev->dev); + err =3D meson->data->channels_init(&pdev->dev); if (err < 0) return err; =20 --=20 2.42.0