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Wed, 29 Nov 2023 05:29:34 -0600 From: Jay Buddhabhatti To: , , , CC: , , , Jay Buddhabhatti Subject: [PATCH RESEND v2 2/2] drivers: clk: zynqmp: update divider round rate logic Date: Wed, 29 Nov 2023 03:29:16 -0800 Message-ID: <20231129112916.23125-3-jay.buddhabhatti@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231129112916.23125-1-jay.buddhabhatti@amd.com> References: <20231129112916.23125-1-jay.buddhabhatti@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0001A0FD:EE_|MN0PR12MB6127:EE_ X-MS-Office365-Filtering-Correlation-Id: a921c8ee-9181-4c7f-70bf-08dbf0ce774d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: WdGbi4LrfsobwDAL0yOjjRnfnsZBMNVRbWv5BXI2Q7CnZ/8Ua6mky705RfWsgGAVZdzWuhZdNX0B4/oaeWsOTam8B9qLPzsjJQpovxqAm2aU6ckP0N+Z6oRl8+E89LA9Uc0C1rSqY6CsGWcP9tRnjVMwefeSxeLuGJAOcLAyOVKaSEMrANQZyN4UD/pBPlSiktChUir4YqN4PqfjW/0NFXv7GPhMuJFrrfHpFKbDENkoTTr/seSbHIdr0Oq83ZtDWZopEPuZoz3jyjg6AqHO0i/sCAWv6HlyjwcBbaMEpY/KiQfQWB0HI4wSe8SGpMivvIrAk6f0oj7/sEGudOAnQjnhCxUi+OjPYzWwj1jRAyIuXwiRI1ehvIuz5+c3J8WCgxwrLSLKCL6U2zR/Ukc+YZITkss25Pw6XBHEUqv7QL3OCCLo6JBox3xhR6Gl4rsQvr4sApv3/sqUe8aws3osEqWEW1oAsa/VSO6Z+RPYv0KIhfd3n9tf4SgOUOPNxbmmX5rOqXg3NhloRLuxlQJ17Yw5h6bFWkVxiqK/54wegIV7Sa8HmAFW0Q/BSXKgn9U7fAWlFiCJX6erguqyDvMAHn1Lf3Gmn1Ed0XFafqDj8+38X45WydUIVH5OjN46U45m0GmDvra6PaxIlphJ5eU2SroDHsSrHO1zVbiAUstJ5DWQJx+YFmzHAh78ho2d1WL8TUAgMGv3v1JrT9diKfrhjIZXV93dG/ausLKIDDRLSW5EUyHI9CgqgD5/p2TASCsvIkh34E2CIO8d/d2rJ8O5zA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(376002)(346002)(136003)(396003)(39860400002)(230922051799003)(82310400011)(186009)(1800799012)(64100799003)(451199024)(46966006)(40470700004)(36840700001)(47076005)(356005)(41300700001)(44832011)(2616005)(86362001)(1076003)(8676002)(6666004)(8936002)(5660300002)(4326008)(40480700001)(2906002)(26005)(110136005)(81166007)(478600001)(316002)(70206006)(70586007)(40460700003)(426003)(54906003)(336012)(36860700001)(83380400001)(36756003)(82740400003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 11:29:35.8237 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a921c8ee-9181-4c7f-70bf-08dbf0ce774d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0001A0FD.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6127 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently zynqmp divider round rate is considering single parent and calculating rate and parent rate accordingly. But if divider clock flag is set to SET_RATE_PARENT then its not trying to traverse through all parent rate and not selecting best parent rate from that. So use common divider_round_rate() which is traversing through all clock parents and its rate and calculating proper parent rate. Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver") Signed-off-by: Jay Buddhabhatti --- drivers/clk/zynqmp/divider.c | 66 +++--------------------------------- 1 file changed, 5 insertions(+), 61 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 33a3b2a22659..5a00487ae408 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -110,52 +110,6 @@ static unsigned long zynqmp_clk_divider_recalc_rate(st= ruct clk_hw *hw, return DIV_ROUND_UP_ULL(parent_rate, value); } =20 -static void zynqmp_get_divider2_val(struct clk_hw *hw, - unsigned long rate, - struct zynqmp_clk_divider *divider, - u32 *bestdiv) -{ - int div1; - int div2; - long error =3D LONG_MAX; - unsigned long div1_prate; - struct clk_hw *div1_parent_hw; - struct zynqmp_clk_divider *pdivider; - struct clk_hw *div2_parent_hw =3D clk_hw_get_parent(hw); - - if (!div2_parent_hw) - return; - - pdivider =3D to_zynqmp_clk_divider(div2_parent_hw); - if (!pdivider) - return; - - div1_parent_hw =3D clk_hw_get_parent(div2_parent_hw); - if (!div1_parent_hw) - return; - - div1_prate =3D clk_hw_get_rate(div1_parent_hw); - *bestdiv =3D 1; - for (div1 =3D 1; div1 <=3D pdivider->max_div;) { - for (div2 =3D 1; div2 <=3D divider->max_div;) { - long new_error =3D ((div1_prate / div1) / div2) - rate; - - if (abs(new_error) < abs(error)) { - *bestdiv =3D div2; - error =3D new_error; - } - if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) - div2 =3D div2 << 1; - else - div2++; - } - if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) - div1 =3D div1 << 1; - else - div1++; - } -} - /** * zynqmp_clk_divider_round_rate() - Round rate of divider clock * @hw: handle between common and hardware-specific interfaces @@ -174,6 +128,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw= *hw, u32 div_type =3D divider->div_type; u32 bestdiv; int ret; + u8 width; =20 /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { @@ -193,23 +148,12 @@ static long zynqmp_clk_divider_round_rate(struct clk_= hw *hw, return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } =20 - bestdiv =3D zynqmp_divider_get_val(*prate, rate, divider->flags); - - /* - * In case of two divisors, compute best divider values and return - * divider2 value based on compute value. div1 will be automatically - * set to optimum based on required total divider value. - */ - if (div_type =3D=3D TYPE_DIV2 && - (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { - zynqmp_get_divider2_val(hw, rate, divider, &bestdiv); - } + width =3D fls(divider->max_div); =20 - if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) - bestdiv =3D rate % *prate ? 1 : bestdiv; + rate =3D divider_round_rate(hw, rate, prate, NULL, width, divider->flags); =20 - bestdiv =3D min_t(u32, bestdiv, divider->max_div); - *prate =3D rate * bestdiv; + if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (= rate % *prate)) + *prate =3D rate; =20 return rate; } --=20 2.17.1