From nobody Wed Dec 17 09:21:55 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1082BC4167B for ; Wed, 29 Nov 2023 10:35:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230044AbjK2Kfg (ORCPT ); Wed, 29 Nov 2023 05:35:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230043AbjK2KfS (ORCPT ); Wed, 29 Nov 2023 05:35:18 -0500 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D8511FEF; Wed, 29 Nov 2023 02:34:55 -0800 (PST) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3AT40FYN013390; Wed, 29 Nov 2023 10:34:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=fMtWRTMAFXeAjy1ryWjc1MTDxKybHBog/v5ERU3eT3E=; b=VNUDt3pg3OjbPqaW25CPvjAF6C7+yd8svR+LZg/Zh1ZzcOpLqUA4cOdwVYKl5SONivnn 9ljMkF3SZbphkHEtdAB+JqrD4ijMAq0Z89ZuFlEyXLQNq6GIgcXrEisjXLyKQFBDlFgX gl6nF3W9ikbdXlv0d8Cat+tCdxLzWLjoiKHootN+wfxnVj4iTfhacIIt5g8sgNDevf9T Fw4iofoklsrU+BcqlMQKIHw6+X7pxi3HkWWU6G39Cf0e/iy8CwtSiiYbFLfOJANq1hvG T++xqmhQ7gfUFWlwNz83SYTnxTEPA6xv4dRrpSDpyuWYCxp4UUIHULo/jx7aHYlNh4cy tA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3unnpesyv9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Nov 2023 10:34:52 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3ATAYobn023977 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 29 Nov 2023 10:34:50 GMT Received: from tengfan2-gv.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 29 Nov 2023 02:34:45 -0800 From: Tengfei Fan To: , , , , , CC: , , , , Tengfei Fan Subject: [PATCH v7 6/6] arm64: defconfig: enable clock controller and pinctrl Date: Wed, 29 Nov 2023 18:33:25 +0800 Message-ID: <20231129103325.24854-7-quic_tengfan@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231129103325.24854-1-quic_tengfan@quicinc.com> References: <20231129103325.24854-1-quic_tengfan@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Pexywgp-pTKWLuxG2wHM51RPVuTWbOo9 X-Proofpoint-ORIG-GUID: Pexywgp-pTKWLuxG2wHM51RPVuTWbOo9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-29_07,2023-11-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxscore=0 phishscore=0 mlxlogscore=532 priorityscore=1501 adultscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311290078 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable global clock controller and pinctrl for support the Qualcomm SM4450 platform to boot to UART console. The serial engine depends on some global clock controller and pinctrl, but as the serial console driver is only available as built-in, so the global clock controller and pinctrl also needs be built-in for the UART device to probe and register the console. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Tengfei Fan --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5ad2b841aafc..a8cf31b62e19 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -599,6 +599,7 @@ CONFIG_PINCTRL_SC8280XP=3Dy CONFIG_PINCTRL_SDM660=3Dy CONFIG_PINCTRL_SDM670=3Dy CONFIG_PINCTRL_SDM845=3Dy +CONFIG_PINCTRL_SM4450=3Dy CONFIG_PINCTRL_SM6115=3Dy CONFIG_PINCTRL_SM6115_LPASS_LPI=3Dm CONFIG_PINCTRL_SM6125=3Dy @@ -1258,6 +1259,7 @@ CONFIG_SM_DISPCC_6115=3Dm CONFIG_SM_DISPCC_8250=3Dy CONFIG_SM_DISPCC_8450=3Dm CONFIG_SM_DISPCC_8550=3Dm +CONFIG_SM_GCC_4450=3Dy CONFIG_SM_GCC_6115=3Dy CONFIG_SM_GCC_8350=3Dy CONFIG_SM_GCC_8450=3Dy --=20 2.17.1