From nobody Mon Dec 29 09:31:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5468C4167B for ; Wed, 29 Nov 2023 05:44:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376963AbjK2Foj (ORCPT ); Wed, 29 Nov 2023 00:44:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41654 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234682AbjK2Fog (ORCPT ); Wed, 29 Nov 2023 00:44:36 -0500 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D398D19B7; Tue, 28 Nov 2023 21:44:41 -0800 (PST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 3AT5iOiX52554686, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 3AT5iOiX52554686 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Nov 2023 13:44:24 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Wed, 29 Nov 2023 13:44:24 +0800 Received: from james-bs01.realtek.com.tw (172.21.190.247) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Wed, 29 Nov 2023 13:44:23 +0800 From: James Tai To: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , James Tai CC: , , "kernel test robot" Subject: [PATCH v3 1/6] dt-bindings: interrupt-controller: Add support for Realtek DHC SoCs Date: Wed, 29 Nov 2023 13:43:34 +0800 Message-ID: <20231129054339.3054202-2-james.tai@realtek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231129054339.3054202-1-james.tai@realtek.com> References: <20231129054339.3054202-1-james.tai@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.21.190.247] X-ClientProxiedBy: RTEXH36506.realtek.com.tw (172.21.6.27) To RTEXMBS03.realtek.com.tw (172.21.6.96) X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the YAML documentation for Realtek DHC (Digital Home Center) SoCs. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202311180921.ayKhiFHL-lkp@int= el.com/ CC: Thomas Gleixner CC: Marc Zyngier CC: Rob Herring CC: Krzysztof Kozlowski CC: Conor Dooley CC: linux-kernel@vger.kernel.org CC: devicetree@vger.kernel.org Signed-off-by: James Tai --- v2 to v3 change: - Retested the bindings using the new version of the dtschema - Fixed the order of property items - Removed redundant files and replaced them with 'realtek,intc.yaml' - Replaced 'interrupts-extended' with 'interrupts' - Added a description for 'interrupts' - Reduced the example code v1 to v2 change: - Tested the bindings using 'make dt_binding_check' - Fixed code style issues .../interrupt-controller/realtek,intc.yaml | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= realtek,intc.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/realtek= ,intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/realtek= ,intc.yaml new file mode 100644 index 000000000000..3aa863b1549d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/realtek,intc.y= aml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/realtek,intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek DHC SoCs Interrupt Controller + +maintainers: + - James Tai + +description: + This interrupt controller is a component of Realtek DHC (Digital Home Ce= nter) + SoCs and is designed to receive interrupts from peripheral devices. + + Each DHC SoC has two sets of interrupt controllers, each capable of + handling up to 32 interrupts. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + enum: + - realtek,rtd1319-intc-iso + - realtek,rtd1319-intc-misc + - realtek,rtd1319d-intc-iso + - realtek,rtd1319d-intc-misc + - realtek,rtd1325-intc-iso + - realtek,rtd1325-intc-misc + - realtek,rtd1619b-intc-iso + - realtek,rtd1619b-intc-misc + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + + '#address-cells': + const: 0 + + interrupts: + description: | + Contains the GIC SPI IRQs mapped to the external interrupt lines. + minItems: 2 + maxItems: 4 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - '#address-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + realtek_iso_intc: interrupt-controller@40 { + compatible =3D "realtek,rtd1319-intc-iso"; + reg =3D <0x00 0x40>; + interrupt-parent =3D <&gic>; + interrupts =3D , + ; + interrupt-controller; + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + }; +... --=20 2.25.1 From nobody Mon Dec 29 09:31:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC7F3C4167B for ; Wed, 29 Nov 2023 05:44:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376978AbjK2For (ORCPT ); Wed, 29 Nov 2023 00:44:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55750 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376967AbjK2Fon (ORCPT ); Wed, 29 Nov 2023 00:44:43 -0500 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D04D41AE; Tue, 28 Nov 2023 21:44:47 -0800 (PST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 3AT5iVKT12554695, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36505.realtek.com.tw[172.21.6.25]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 3AT5iVKT12554695 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Nov 2023 13:44:31 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.32; Wed, 29 Nov 2023 13:44:31 +0800 Received: from james-bs01.realtek.com.tw (172.21.190.247) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Wed, 29 Nov 2023 13:44:31 +0800 From: James Tai To: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , James Tai CC: , , "kernel test robot" , Dan Carpenter Subject: [PATCH v3 2/6] irqchip: Add interrupt controller support for Realtek DHC SoCs Date: Wed, 29 Nov 2023 13:43:35 +0800 Message-ID: <20231129054339.3054202-3-james.tai@realtek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231129054339.3054202-1-james.tai@realtek.com> References: <20231129054339.3054202-1-james.tai@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.21.190.247] X-ClientProxiedBy: RTEXH36506.realtek.com.tw (172.21.6.27) To RTEXMBS03.realtek.com.tw (172.21.6.96) X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-ServerInfo: RTEXH36505.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Realtek DHC (Digital Home Center) SoCs share a common interrupt controller design. This universal interrupt controller driver provides support for various variants within the Realtek DHC SoC family. Each DHC SoC features two sets of extended interrupt controllers, each capable of handling up to 32 interrupts. These expansion controllers are connected to the GIC (Generic Interrupt Controller). Reported-by: kernel test robot Reported-by: Dan Carpenter Closes: https://lore.kernel.org/r/202311201929.2FpvMRlg-lkp@intel.com/ CC: Thomas Gleixner CC: Marc Zyngier CC: linux-kernel@vger.kernel.org Signed-off-by: James Tai --- v2 to v3 change: - Resolved kernel test robot build warnings https://lore.kernel.org/r/202311201929.2FpvMRlg-lkp@intel.com/ v1 to v2 change: - Fixed code style issues - Removed the realtek_intc_set_affinity funcation - Replaced spin_lock_irqsave with raw_spin_lock drivers/irqchip/Kconfig | 4 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-realtek-intc-common.c | 208 ++++++++++++++++++++++ drivers/irqchip/irq-realtek-intc-common.h | 77 ++++++++ 4 files changed, 290 insertions(+) create mode 100644 drivers/irqchip/irq-realtek-intc-common.c create mode 100644 drivers/irqchip/irq-realtek-intc-common.h diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index f7149d0f3d45..267c3429b48d 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -218,6 +218,10 @@ config RDA_INTC bool select IRQ_DOMAIN =20 +config REALTEK_DHC_INTC + tristate + select IRQ_DOMAIN + config RENESAS_INTC_IRQPIN bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index ffd945fe71aa..f6774af7fde2 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -47,6 +47,7 @@ obj-$(CONFIG_IRQ_MIPS_CPU) +=3D irq-mips-cpu.o obj-$(CONFIG_IXP4XX_IRQ) +=3D irq-ixp4xx.o obj-$(CONFIG_JCORE_AIC) +=3D irq-jcore-aic.o obj-$(CONFIG_RDA_INTC) +=3D irq-rda-intc.o +obj-$(CONFIG_REALTEK_DHC_INTC) +=3D irq-realtek-intc-common.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) +=3D irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) +=3D irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) +=3D irq-renesas-rza1.o diff --git a/drivers/irqchip/irq-realtek-intc-common.c b/drivers/irqchip/ir= q-realtek-intc-common.c new file mode 100644 index 000000000000..64d656e5a015 --- /dev/null +++ b/drivers/irqchip/irq-realtek-intc-common.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek DHC SoCs interrupt controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include + +#include "irq-realtek-intc-common.h" + +struct realtek_intc_data; + +static inline unsigned int realtek_intc_get_ints(struct realtek_intc_data = *data) +{ + return readl(data->base + data->info->isr_offset); +} + +static inline void realtek_intc_clear_ints_bit(struct realtek_intc_data *d= ata, int bit) +{ + writel(BIT(bit) & ~1, data->base + data->info->isr_offset); +} + +static inline unsigned int realtek_intc_get_inte(struct realtek_intc_data = *data) +{ + unsigned int val; + + raw_spin_lock(&data->lock); + val =3D readl(data->base + data->info->scpu_int_en_offset); + raw_spin_unlock(&data->lock); + + return val; +} + +static void realtek_intc_handler(struct irq_desc *desc) +{ + struct realtek_intc_subset_data *subset_data =3D irq_desc_get_handler_dat= a(desc); + struct realtek_intc_data *data =3D subset_data->common; + struct irq_chip *chip =3D irq_desc_get_chip(desc); + u32 ints, inte, mask; + int irq; + + chained_irq_enter(chip, desc); + + ints =3D realtek_intc_get_ints(data) & subset_data->cfg->ints_mask; + inte =3D realtek_intc_get_inte(data); + + while (ints) { + irq =3D __ffs(ints); + ints &=3D ~BIT(irq); + + mask =3D data->info->isr_to_scpu_int_en_mask[irq]; + if (mask !=3D IRQ_ALWAYS_ENABLED && !(inte & mask)) + continue; + + generic_handle_irq(irq_find_mapping(data->domain, irq)); + realtek_intc_clear_ints_bit(data, irq); + } + + chained_irq_exit(chip, desc); +} + +static void realtek_intc_mask_irq(struct irq_data *data) +{ + struct realtek_intc_data *intc_data =3D irq_data_get_irq_chip_data(data); + + writel(BIT(data->hwirq), intc_data->base + intc_data->info->isr_offset); +} + +static void realtek_intc_unmask_irq(struct irq_data *data) +{ + struct realtek_intc_data *intc_data =3D irq_data_get_irq_chip_data(data); + + writel(BIT(data->hwirq), intc_data->base + intc_data->info->umsk_isr_offs= et); +} + +static void realtek_intc_enable_irq(struct irq_data *data) +{ + struct realtek_intc_data *intc_data =3D irq_data_get_irq_chip_data(data); + u32 scpu_int_en, mask; + + mask =3D intc_data->info->isr_to_scpu_int_en_mask[data->hwirq]; + if (!mask) + return; + + raw_spin_lock(&intc_data->lock); + scpu_int_en =3D readl(intc_data->base + intc_data->info->scpu_int_en_offs= et); + scpu_int_en |=3D mask; + writel(scpu_int_en, intc_data->base + intc_data->info->umsk_isr_offset); + raw_spin_unlock(&intc_data->lock); +} + +static void realtek_intc_disable_irq(struct irq_data *data) +{ + struct realtek_intc_data *intc_data =3D irq_data_get_irq_chip_data(data); + u32 scpu_int_en, mask; + + mask =3D intc_data->info->isr_to_scpu_int_en_mask[data->hwirq]; + if (!mask) + return; + + raw_spin_lock(&intc_data->lock); + scpu_int_en =3D readl(intc_data->base + intc_data->info->scpu_int_en_offs= et); + scpu_int_en &=3D ~mask; + writel(scpu_int_en, intc_data->base + intc_data->info->umsk_isr_offset); + raw_spin_unlock(&intc_data->lock); +} + +static struct irq_chip realtek_intc_chip =3D { + .name =3D "realtek-intc", + .irq_mask =3D realtek_intc_mask_irq, + .irq_unmask =3D realtek_intc_unmask_irq, + .irq_enable =3D realtek_intc_enable_irq, + .irq_disable =3D realtek_intc_disable_irq, +}; + +static int realtek_intc_domain_map(struct irq_domain *d, unsigned int irq,= irq_hw_number_t hw) +{ + struct realtek_intc_data *data =3D d->host_data; + + irq_set_chip_and_handler(irq, &realtek_intc_chip, handle_level_irq); + irq_set_chip_data(irq, data); + irq_set_probe(irq); + + return 0; +} + +static const struct irq_domain_ops realtek_intc_domain_ops =3D { + .xlate =3D irq_domain_xlate_onecell, + .map =3D realtek_intc_domain_map, +}; + +static int realtek_intc_subset(struct device_node *node, struct realtek_in= tc_data *data, int index) +{ + struct realtek_intc_subset_data *subset_data =3D &data->subset_data[index= ]; + const struct realtek_intc_subset_cfg *cfg =3D &data->info->cfg[index]; + int irq; + + irq =3D irq_of_parse_and_map(node, index); + if (irq <=3D 0) + return irq; + + subset_data->common =3D data; + subset_data->cfg =3D cfg; + subset_data->parent_irq =3D irq; + irq_set_chained_handler_and_data(irq, realtek_intc_handler, subset_data); + + return 0; +} + +int realtek_intc_probe(struct platform_device *pdev, const struct realtek_= intc_info *info) +{ + struct realtek_intc_data *data; + struct device *dev =3D &pdev->dev; + struct device_node *node =3D dev->of_node; + int ret, i; + + data =3D devm_kzalloc(dev, struct_size(data, subset_data, info->cfg_num),= GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->base =3D of_iomap(node, 0); + if (!data->base) { + ret =3D -ENOMEM; + goto out_cleanup; + } + + data->info =3D info; + + raw_spin_lock_init(&data->lock); + + data->domain =3D irq_domain_add_linear(node, 32, &realtek_intc_domain_ops= , data); + if (!data->domain) { + ret =3D -ENOMEM; + goto out_cleanup; + } + + data->subset_data_num =3D info->cfg_num; + for (i =3D 0; i < info->cfg_num; i++) { + ret =3D realtek_intc_subset(node, data, i); + if (ret) { + WARN(ret, "failed to init subset %d: %d", i, ret); + ret =3D -ENOMEM; + goto out_cleanup; + } + } + + platform_set_drvdata(pdev, data); + + return 0; + +out_cleanup: + + if (data->base) + iounmap(data->base); + + devm_kfree(dev, data); + + return ret; +} +EXPORT_SYMBOL(realtek_intc_probe); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek DHC SoC Interrupt Controller Driver"); diff --git a/drivers/irqchip/irq-realtek-intc-common.h b/drivers/irqchip/ir= q-realtek-intc-common.h new file mode 100644 index 000000000000..38be116dba60 --- /dev/null +++ b/drivers/irqchip/irq-realtek-intc-common.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ +/* + * Copyright (c) 2023 Realtek Semiconductor Corporation + */ + +#ifndef _IRQ_REALTEK_COMMON_H +#define _IRQ_REALTEK_COMMON_H + +#include +#include +#include + +/** + * realtek_intc_subset_cfg - subset interrupt mask + * @ints_mask: inetrrupt mask + */ +struct realtek_intc_subset_cfg { + unsigned int ints_mask; +}; + +/** + * realtek_intc_info - interrupt controller data. + * @isr_offset: interrupt status register offset. + * @umsk_isr_offset: unmask interrupt status register offset. + * @scpu_int_en_offset: interrupt enable register offset. + * @cfg: cfg of the subset. + * @cfg_num: number of cfg. + */ +struct realtek_intc_info { + const struct realtek_intc_subset_cfg *cfg; + unsigned int isr_offset; + unsigned int umsk_isr_offset; + unsigned int scpu_int_en_offset; + const u32 *isr_to_scpu_int_en_mask; + int cfg_num; +}; + +/** + * realtek_intc_subset_data - handler of a interrupt source only handles i= nts + * bits in the mask. + * @cfg: cfg of the subset. + * @common: common data. + * @parent_irq: interrupt source. + */ +struct realtek_intc_subset_data { + const struct realtek_intc_subset_cfg *cfg; + struct realtek_intc_data *common; + int parent_irq; +}; + +/** + * realtek_intc_data - configuration data for realtek interrupt controller= driver. + * @base: base of interrupt register + * @info: info of intc + * @domain: interrupt domain + * @lock: lock + * @saved_en: status of interrupt enable + * @subset_data_num: number of subset data + * @subset_data: subset data + */ +struct realtek_intc_data { + void __iomem *base; + const struct realtek_intc_info *info; + struct irq_domain *domain; + struct raw_spinlock lock; + unsigned int saved_en; + int subset_data_num; + struct realtek_intc_subset_data subset_data[]; +}; + +#define IRQ_ALWAYS_ENABLED U32_MAX +#define DISABLE_INTC (0) +#define CLEAN_INTC_STATUS GENMASK(31, 1) + +int realtek_intc_probe(struct platform_device *pdev, const struct realtek_= intc_info *info); + +#endif /* _IRQ_REALTEK_COMMON_H */ --=20 2.25.1 From nobody Mon Dec 29 09:31:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25FBFC07CB1 for ; Wed, 29 Nov 2023 05:44:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376961AbjK2Fou (ORCPT ); Wed, 29 Nov 2023 00:44:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376969AbjK2Foo (ORCPT ); Wed, 29 Nov 2023 00:44:44 -0500 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E82019AB; Tue, 28 Nov 2023 21:44:49 -0800 (PST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 3AT5iYvsD2554701, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 3AT5iYvsD2554701 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Nov 2023 13:44:34 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Wed, 29 Nov 2023 13:44:35 +0800 Received: from james-bs01.realtek.com.tw (172.21.190.247) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Wed, 29 Nov 2023 13:44:34 +0800 From: James Tai To: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , James Tai CC: , , "kernel test robot" Subject: [PATCH v3 3/6] irqchip: Introduce RTD1319 support using the Realtek common interrupt controller driver Date: Wed, 29 Nov 2023 13:43:36 +0800 Message-ID: <20231129054339.3054202-4-james.tai@realtek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231129054339.3054202-1-james.tai@realtek.com> References: <20231129054339.3054202-1-james.tai@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.21.190.247] X-ClientProxiedBy: RTEXH36506.realtek.com.tw (172.21.6.27) To RTEXMBS03.realtek.com.tw (172.21.6.96) X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the RTD1319 platform. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202311061208.hJmxGqym-lkp@int= el.com/ CC: Thomas Gleixner CC: Marc Zyngier CC: linux-kernel@vger.kernel.org Signed-off-by: James Tai --- v2 to v3 change: - Unchanged v1 to v2 change: - Resolved kernel test robot build warnings - Replaced magic number with macro - Fixed code style issues drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-realtek-rtd1319.c | 218 ++++++++++++++++++++++++++ 3 files changed, 225 insertions(+) create mode 100644 drivers/irqchip/irq-realtek-rtd1319.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 267c3429b48d..05856ce885fa 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -222,6 +222,12 @@ config REALTEK_DHC_INTC tristate select IRQ_DOMAIN =20 +config REALTEK_RTD1319_INTC + tristate "Realtek RTD1319 interrupt controller" + select REALTEK_DHC_INTC + help + Support for Realtek RTD1319 Interrupt Controller. + config RENESAS_INTC_IRQPIN bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index f6774af7fde2..6a2650b0a924 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_IXP4XX_IRQ) +=3D irq-ixp4xx.o obj-$(CONFIG_JCORE_AIC) +=3D irq-jcore-aic.o obj-$(CONFIG_RDA_INTC) +=3D irq-rda-intc.o obj-$(CONFIG_REALTEK_DHC_INTC) +=3D irq-realtek-intc-common.o +obj-$(CONFIG_REALTEK_RTD1319_INTC) +=3D irq-realtek-rtd1319.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) +=3D irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) +=3D irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) +=3D irq-renesas-rza1.o diff --git a/drivers/irqchip/irq-realtek-rtd1319.c b/drivers/irqchip/irq-re= altek-rtd1319.c new file mode 100644 index 000000000000..23c13c218b04 --- /dev/null +++ b/drivers/irqchip/irq-realtek-rtd1319.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1319 interrupt controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include + +#include "irq-realtek-intc-common.h" + +#define ISO_NORMAL_MASK 0xffffcffe +#define ISO_RTC_MASK 0x00003001 +#define MISC_NMI_WDT_MASK 0x00000004 +#define MISC_NORMAL_MASK 0xffffc0d2 +#define MISC_UART1_MASK 0x00000028 +#define MISC_UART2_MASK 0x00002100 + +#define ISO_ISR_EN_OFFSET 0x40 +#define ISO_ISR_OFFSET 0 +#define ISO_ISR_UMSK_OFFSET 0x4 +#define MISC_ISR_EN_OFFSET 0x80 +#define MISC_ISR_OFFSET 0xc +#define MISC_ISR_UMSK_OFFSET 0x8 + +enum rtd1319_iso_isr_bits { + RTD1319_ISO_ISR_TC3_SHIFT =3D 1, + RTD1319_ISO_ISR_UR0_SHIFT =3D 2, + RTD1319_ISO_ISR_LSADC0_SHIFT =3D 3, + RTD1319_ISO_ISR_IRDA_SHIFT =3D 5, + RTD1319_ISO_ISR_SPI1_SHIFT =3D 6, + RTD1319_ISO_ISR_WDOG_NMI_SHIFT =3D 7, + RTD1319_ISO_ISR_I2C0_SHIFT =3D 8, + RTD1319_ISO_ISR_TC4_SHIFT =3D 9, + RTD1319_ISO_ISR_TC7_SHIFT =3D 10, + RTD1319_ISO_ISR_I2C1_SHIFT =3D 11, + RTD1319_ISO_ISR_RTC_HSEC_SHIFT =3D 12, + RTD1319_ISO_ISR_RTC_ALARM_SHIFT =3D 13, + RTD1319_ISO_ISR_GPIOA_SHIFT =3D 19, + RTD1319_ISO_ISR_GPIODA_SHIFT =3D 20, + RTD1319_ISO_ISR_ISO_MISC_SHIFT =3D 21, + RTD1319_ISO_ISR_CBUS_SHIFT =3D 22, + RTD1319_ISO_ISR_ETN_SHIFT =3D 23, + RTD1319_ISO_ISR_USB_HOST_SHIFT =3D 24, + RTD1319_ISO_ISR_USB_U3_DRD_SHIFT =3D 25, + RTD1319_ISO_ISR_USB_U2_DRD_SHIFT =3D 26, + RTD1319_ISO_ISR_PORB_HV_SHIFT =3D 28, + RTD1319_ISO_ISR_PORB_DV_SHIFT =3D 29, + RTD1319_ISO_ISR_PORB_AV_SHIFT =3D 30, + RTD1319_ISO_ISR_I2C1_REQ_SHIFT =3D 31, +}; + +static const u32 rtd1319_iso_isr_to_scpu_int_en_mask[32] =3D { + [RTD1319_ISO_ISR_SPI1_SHIFT] =3D BIT(1), + [RTD1319_ISO_ISR_UR0_SHIFT] =3D BIT(2), + [RTD1319_ISO_ISR_LSADC0_SHIFT] =3D BIT(3), + [RTD1319_ISO_ISR_IRDA_SHIFT] =3D BIT(5), + [RTD1319_ISO_ISR_I2C0_SHIFT] =3D BIT(8), + [RTD1319_ISO_ISR_I2C1_SHIFT] =3D BIT(11), + [RTD1319_ISO_ISR_RTC_HSEC_SHIFT] =3D BIT(12), + [RTD1319_ISO_ISR_RTC_ALARM_SHIFT] =3D BIT(13), + [RTD1319_ISO_ISR_GPIOA_SHIFT] =3D BIT(19), + [RTD1319_ISO_ISR_GPIODA_SHIFT] =3D BIT(20), + [RTD1319_ISO_ISR_PORB_HV_SHIFT] =3D BIT(28), + [RTD1319_ISO_ISR_PORB_DV_SHIFT] =3D BIT(29), + [RTD1319_ISO_ISR_PORB_AV_SHIFT] =3D BIT(30), + [RTD1319_ISO_ISR_I2C1_REQ_SHIFT] =3D BIT(31), +}; + +enum rtd1319_misc_isr_bits { + RTD1319_ISR_WDOG_NMI_SHIFT =3D 2, + RTD1319_ISR_UR1_SHIFT =3D 3, + RTD1319_ISR_TC5_SHIFT =3D 4, + RTD1319_ISR_UR1_TO_SHIFT =3D 5, + RTD1319_ISR_TC0_SHIFT =3D 6, + RTD1319_ISR_TC1_SHIFT =3D 7, + RTD1319_ISR_UR2_SHIFT =3D 8, + RTD1319_ISR_RTC_HSEC_SHIFT =3D 9, + RTD1319_ISR_RTC_MIN_SHIFT =3D 10, + RTD1319_ISR_RTC_HOUR_SHIFT =3D 11, + RTD1319_ISR_RTC_DATE_SHIFT =3D 12, + RTD1319_ISR_UR2_TO_SHIFT =3D 13, + RTD1319_ISR_I2C5_SHIFT =3D 14, + RTD1319_ISR_I2C3_SHIFT =3D 23, + RTD1319_ISR_SC0_SHIFT =3D 24, + RTD1319_ISR_SC1_SHIFT =3D 25, + RTD1319_ISR_SPI_SHIFT =3D 27, + RTD1319_ISR_FAN_SHIFT =3D 29, +}; + +static const u32 rtd1319_misc_isr_to_scpu_int_en_mask[32] =3D { + [RTD1319_ISR_UR1_SHIFT] =3D BIT(3), + [RTD1319_ISR_UR1_TO_SHIFT] =3D BIT(5), + [RTD1319_ISR_UR2_TO_SHIFT] =3D BIT(6), + [RTD1319_ISR_UR2_SHIFT] =3D BIT(7), + [RTD1319_ISR_RTC_MIN_SHIFT] =3D BIT(10), + [RTD1319_ISR_RTC_HOUR_SHIFT] =3D BIT(11), + [RTD1319_ISR_RTC_DATE_SHIFT] =3D BIT(12), + [RTD1319_ISR_I2C5_SHIFT] =3D BIT(14), + [RTD1319_ISR_SC0_SHIFT] =3D BIT(24), + [RTD1319_ISR_SC1_SHIFT] =3D BIT(25), + [RTD1319_ISR_SPI_SHIFT] =3D BIT(27), + [RTD1319_ISR_I2C3_SHIFT] =3D BIT(28), + [RTD1319_ISR_FAN_SHIFT] =3D BIT(29), + [RTD1319_ISR_WDOG_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, +}; + +static struct realtek_intc_subset_cfg rtd1319_intc_iso_cfgs[] =3D { + { ISO_NORMAL_MASK, }, + { ISO_RTC_MASK, }, +}; + +static const struct realtek_intc_info rtd1319_intc_iso_info =3D { + .isr_offset =3D ISO_ISR_OFFSET, + .umsk_isr_offset =3D ISO_ISR_UMSK_OFFSET, + .scpu_int_en_offset =3D ISO_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask =3D rtd1319_iso_isr_to_scpu_int_en_mask, + .cfg =3D rtd1319_intc_iso_cfgs, + .cfg_num =3D ARRAY_SIZE(rtd1319_intc_iso_cfgs), +}; + +static struct realtek_intc_subset_cfg rtd1319_intc_misc_cfgs[] =3D { + { MISC_NORMAL_MASK, }, + { MISC_NMI_WDT_MASK, }, + { MISC_UART1_MASK, }, + { MISC_UART2_MASK, }, +}; + +static const struct realtek_intc_info rtd1319_intc_misc_info =3D { + .isr_offset =3D MISC_ISR_OFFSET, + .umsk_isr_offset =3D MISC_ISR_UMSK_OFFSET, + .scpu_int_en_offset =3D MISC_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask =3D rtd1319_misc_isr_to_scpu_int_en_mask, + .cfg =3D rtd1319_intc_misc_cfgs, + .cfg_num =3D ARRAY_SIZE(rtd1319_intc_misc_cfgs), +}; + +static const struct of_device_id realtek_intc_rtd1319_dt_matches[] =3D { + { + .compatible =3D "realtek,rtd1319-intc-iso", + .data =3D &rtd1319_intc_iso_info, + }, { + .compatible =3D "realtek,rtd1319-intc-misc", + .data =3D &rtd1319_intc_misc_info, + }, + { /* sentinel */ } +}; + +static int realtek_intc_rtd1319_suspend(struct device *dev) +{ + struct realtek_intc_data *data =3D dev_get_drvdata(dev); + const struct realtek_intc_info *info =3D data->info; + + data->saved_en =3D readl(data->base + info->scpu_int_en_offset); + + writel(DISABLE_INTC, data->base + info->scpu_int_en_offset); + writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset); + writel(CLEAN_INTC_STATUS, data->base + info->isr_offset); + + return 0; +} + +static int realtek_intc_rtd1319_resume(struct device *dev) +{ + struct realtek_intc_data *data =3D dev_get_drvdata(dev); + const struct realtek_intc_info *info =3D data->info; + + writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset); + writel(CLEAN_INTC_STATUS, data->base + info->isr_offset); + writel(data->saved_en, data->base + info->scpu_int_en_offset); + + return 0; +} + +static const struct dev_pm_ops realtek_intc_rtd1319_pm_ops =3D { + .suspend_noirq =3D realtek_intc_rtd1319_suspend, + .resume_noirq =3D realtek_intc_rtd1319_resume, +}; + +static int rtd1319_intc_probe(struct platform_device *pdev) +{ + const struct realtek_intc_info *info; + + info =3D of_device_get_match_data(&pdev->dev); + if (!info) + return -EINVAL; + + return realtek_intc_probe(pdev, info); +} + +static struct platform_driver realtek_intc_rtd1319_driver =3D { + .probe =3D rtd1319_intc_probe, + .driver =3D { + .name =3D "realtek_intc_rtd1319", + .of_match_table =3D realtek_intc_rtd1319_dt_matches, + .suppress_bind_attrs =3D true, + .pm =3D &realtek_intc_rtd1319_pm_ops, + }, +}; + +static int __init realtek_intc_rtd1319_init(void) +{ + return platform_driver_register(&realtek_intc_rtd1319_driver); +} +core_initcall(realtek_intc_rtd1319_init); + +static void __exit realtek_intc_rtd1319_exit(void) +{ + platform_driver_unregister(&realtek_intc_rtd1319_driver); +} +module_exit(realtek_intc_rtd1319_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek RTD1319 Interrupt Controller Driver"); --=20 2.25.1 From nobody Mon Dec 29 09:31:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFEF9C4167B for ; Wed, 29 Nov 2023 05:45:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234871AbjK2Foy (ORCPT ); Wed, 29 Nov 2023 00:44:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376976AbjK2Fop (ORCPT ); Wed, 29 Nov 2023 00:44:45 -0500 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E683C1BC2; Tue, 28 Nov 2023 21:44:50 -0800 (PST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 3AT5ibAK32554704, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36505.realtek.com.tw[172.21.6.25]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 3AT5ibAK32554704 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Nov 2023 13:44:37 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.32; Wed, 29 Nov 2023 13:44:37 +0800 Received: from james-bs01.realtek.com.tw (172.21.190.247) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Wed, 29 Nov 2023 13:44:36 +0800 From: James Tai To: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , James Tai CC: , , "kernel test robot" Subject: [PATCH v3 4/6] irqchip: Introduce RTD1319D support using the Realtek common interrupt controller driver Date: Wed, 29 Nov 2023 13:43:37 +0800 Message-ID: <20231129054339.3054202-5-james.tai@realtek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231129054339.3054202-1-james.tai@realtek.com> References: <20231129054339.3054202-1-james.tai@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.21.190.247] X-ClientProxiedBy: RTEXH36506.realtek.com.tw (172.21.6.27) To RTEXMBS03.realtek.com.tw (172.21.6.96) X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-ServerInfo: RTEXH36505.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the RTD1319D platform. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202311061137.FRpoKwcm-lkp@int= el.com/ CC: Thomas Gleixner CC: Marc Zyngier CC: linux-kernel@vger.kernel.org Signed-off-by: James Tai --- v2 to v3 change: - Unchanged v1 to v2 change: - Resolved kernel test robot build warnings - Replaced magic number with macro - Fixed code style issues drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-realtek-rtd1319d.c | 227 +++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 drivers/irqchip/irq-realtek-rtd1319d.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 05856ce885fa..c6552c513442 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -228,6 +228,12 @@ config REALTEK_RTD1319_INTC help Support for Realtek RTD1319 Interrupt Controller. =20 +config REALTEK_RTD1319D_INTC + tristate "Realtek RTD1319D interrupt controller" + select REALTEK_DHC_INTC + help + Support for Realtek RTD1319D Interrupt Controller. + config RENESAS_INTC_IRQPIN bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 6a2650b0a924..c8adaed4c1b2 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -49,6 +49,7 @@ obj-$(CONFIG_JCORE_AIC) +=3D irq-jcore-aic.o obj-$(CONFIG_RDA_INTC) +=3D irq-rda-intc.o obj-$(CONFIG_REALTEK_DHC_INTC) +=3D irq-realtek-intc-common.o obj-$(CONFIG_REALTEK_RTD1319_INTC) +=3D irq-realtek-rtd1319.o +obj-$(CONFIG_REALTEK_RTD1319D_INTC) +=3D irq-realtek-rtd1319d.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) +=3D irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) +=3D irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) +=3D irq-renesas-rza1.o diff --git a/drivers/irqchip/irq-realtek-rtd1319d.c b/drivers/irqchip/irq-r= ealtek-rtd1319d.c new file mode 100644 index 000000000000..2d4bd6230e17 --- /dev/null +++ b/drivers/irqchip/irq-realtek-rtd1319d.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1319D interrupt controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include + +#include "irq-realtek-intc-common.h" + +#define ISO_NMI_WDT_MASK 0x08008090 +#define ISO_NORMAL_MASK 0xf7ff7f6e +#define MISC_NORMAL_MASK 0xffe0ded6 +#define MISC_UART1_MASK 0x00000028 +#define MISC_UART2_MASK 0x00002100 + +#define ISO_ISR_EN_OFFSET 0x40 +#define ISO_ISR_OFFSET 0 +#define ISO_ISR_UMSK_OFFSET 0x4 +#define MISC_ISR_EN_OFFSET 0x80 +#define MISC_ISR_OFFSET 0xc +#define MISC_ISR_UMSK_OFFSET 0x8 + +enum rtd1319d_iso_isr_bits { + RTD1319D_ISO_ISR_TC3_SHIFT =3D 1, + RTD1319D_ISO_ISR_UR0_SHIFT =3D 2, + RTD1319D_ISO_ISR_LSADC0_SHIFT =3D 3, + RTD1319D_ISO_ISR_WDOG1_NMI_SHIFT =3D 4, + RTD1319D_ISO_ISR_IRDA_SHIFT =3D 5, + RTD1319D_ISO_ISR_SPI1_SHIFT =3D 6, + RTD1319D_ISO_ISR_WDOG2_NMI_SHIFT =3D 7, + RTD1319D_ISO_ISR_I2C0_SHIFT =3D 8, + RTD1319D_ISO_ISR_TC4_SHIFT =3D 9, + RTD1319D_ISO_ISR_TC7_SHIFT =3D 10, + RTD1319D_ISO_ISR_I2C1_SHIFT =3D 11, + RTD1319D_ISO_ISR_HIFI_WAKEUP_SHIFT =3D 14, + RTD1319D_ISO_ISR_WDOG4_NMI_SHIFT =3D 15, + RTD1319D_ISO_ISR_TC8_SHIFT =3D 16, + RTD1319D_ISO_ISR_VFD_SHIFT =3D 17, + RTD1319D_ISO_ISR_VTC_SHIFT =3D 18, + RTD1319D_ISO_ISR_GPIOA_SHIFT =3D 19, + RTD1319D_ISO_ISR_GPIODA_SHIFT =3D 20, + RTD1319D_ISO_ISR_ISO_MISC_SHIFT =3D 21, + RTD1319D_ISO_ISR_CBUS_SHIFT =3D 22, + RTD1319D_ISO_ISR_ETN_SHIFT =3D 23, + RTD1319D_ISO_ISR_USB_HOST_SHIFT =3D 24, + RTD1319D_ISO_ISR_USB_U3_DRD_SHIFT =3D 25, + RTD1319D_ISO_ISR_USB_U2_DRD_SHIFT =3D 26, + RTD1319D_ISO_ISR_WDOG3_NMI_SHIFT =3D 27, + RTD1319D_ISO_ISR_PORB_HV_CEN_SHIFT =3D 28, + RTD1319D_ISO_ISR_PORB_DV_CEN_SHIFT =3D 29, + RTD1319D_ISO_ISR_PORB_AV_CEN_SHIFT =3D 30, + RTD1319D_ISO_ISR_I2C1_REQ_SHIFT =3D 31, +}; + +static const u32 rtd1319d_iso_isr_to_scpu_int_en_mask[32] =3D { + [RTD1319D_ISO_ISR_SPI1_SHIFT] =3D BIT(1), + [RTD1319D_ISO_ISR_UR0_SHIFT] =3D BIT(2), + [RTD1319D_ISO_ISR_LSADC0_SHIFT] =3D BIT(3), + [RTD1319D_ISO_ISR_IRDA_SHIFT] =3D BIT(5), + [RTD1319D_ISO_ISR_I2C0_SHIFT] =3D BIT(8), + [RTD1319D_ISO_ISR_I2C1_SHIFT] =3D BIT(11), + [RTD1319D_ISO_ISR_VFD_SHIFT] =3D BIT(17), + [RTD1319D_ISO_ISR_GPIOA_SHIFT] =3D BIT(19), + [RTD1319D_ISO_ISR_GPIODA_SHIFT] =3D BIT(20), + [RTD1319D_ISO_ISR_PORB_HV_CEN_SHIFT] =3D BIT(28), + [RTD1319D_ISO_ISR_PORB_DV_CEN_SHIFT] =3D BIT(29), + [RTD1319D_ISO_ISR_PORB_AV_CEN_SHIFT] =3D BIT(30), + [RTD1319D_ISO_ISR_I2C1_REQ_SHIFT] =3D BIT(31), + [RTD1319D_ISO_ISR_WDOG1_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1319D_ISO_ISR_WDOG2_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1319D_ISO_ISR_WDOG3_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1319D_ISO_ISR_WDOG4_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, +}; + +enum rtd1319d_misc_isr_bits { + RTD1319D_ISR_UR1_SHIFT =3D 3, + RTD1319D_ISR_TC5_SHIFT =3D 4, + RTD1319D_ISR_UR1_TO_SHIFT =3D 5, + RTD1319D_ISR_TC0_SHIFT =3D 6, + RTD1319D_ISR_TC1_SHIFT =3D 7, + RTD1319D_ISR_UR2_SHIFT =3D 8, + RTD1319D_ISR_UR2_TO_SHIFT =3D 13, + RTD1319D_ISR_I2C5_SHIFT =3D 14, + RTD1319D_ISR_I2C4_SHIFT =3D 15, + RTD1319D_ISR_DRTC_HSEC_SHIFT =3D 16, + RTD1319D_ISR_DRTC_MIN_SHIFT =3D 17, + RTD1319D_ISR_DRTC_HOUR_SHIFT =3D 18, + RTD1319D_ISR_DRTC_DATE_SHIFT =3D 19, + RTD1319D_ISR_DRTC_ALARM_SHIFT =3D 20, + RTD1319D_ISR_I2C3_SHIFT =3D 23, + RTD1319D_ISR_SC0_SHIFT =3D 24, + RTD1319D_ISR_SC1_SHIFT =3D 25, + RTD1319D_ISR_SPI_SHIFT =3D 27, + RTD1319D_ISR_FAN_SHIFT =3D 29, +}; + +static const u32 rtd1319d_misc_isr_to_scpu_int_en_mask[32] =3D { + [RTD1319D_ISR_UR1_SHIFT] =3D BIT(3), + [RTD1319D_ISR_UR1_TO_SHIFT] =3D BIT(5), + [RTD1319D_ISR_UR2_TO_SHIFT] =3D BIT(6), + [RTD1319D_ISR_UR2_SHIFT] =3D BIT(7), + [RTD1319D_ISR_I2C5_SHIFT] =3D BIT(14), + [RTD1319D_ISR_I2C4_SHIFT] =3D BIT(15), + [RTD1319D_ISR_DRTC_HSEC_SHIFT] =3D BIT(16), + [RTD1319D_ISR_DRTC_MIN_SHIFT] =3D BIT(17), + [RTD1319D_ISR_DRTC_HOUR_SHIFT] =3D BIT(18), + [RTD1319D_ISR_DRTC_DATE_SHIFT] =3D BIT(19), + [RTD1319D_ISR_DRTC_ALARM_SHIFT] =3D BIT(20), + [RTD1319D_ISR_SC0_SHIFT] =3D BIT(24), + [RTD1319D_ISR_SC1_SHIFT] =3D BIT(25), + [RTD1319D_ISR_SPI_SHIFT] =3D BIT(27), + [RTD1319D_ISR_I2C3_SHIFT] =3D BIT(28), + [RTD1319D_ISR_FAN_SHIFT] =3D BIT(29), +}; + +static struct realtek_intc_subset_cfg rtd1319d_intc_iso_cfgs[] =3D { + { ISO_NORMAL_MASK, }, + { ISO_NMI_WDT_MASK, }, +}; + +static const struct realtek_intc_info rtd1319d_intc_iso_info =3D { + .isr_offset =3D ISO_ISR_OFFSET, + .umsk_isr_offset =3D ISO_ISR_UMSK_OFFSET, + .scpu_int_en_offset =3D ISO_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask =3D rtd1319d_iso_isr_to_scpu_int_en_mask, + .cfg =3D rtd1319d_intc_iso_cfgs, + .cfg_num =3D ARRAY_SIZE(rtd1319d_intc_iso_cfgs), +}; + +static struct realtek_intc_subset_cfg rtd1319d_intc_misc_cfgs[] =3D { + { MISC_NORMAL_MASK, }, + { MISC_UART1_MASK, }, + { MISC_UART2_MASK, }, +}; + +static const struct realtek_intc_info rtd1319d_intc_misc_info =3D { + .isr_offset =3D MISC_ISR_OFFSET, + .umsk_isr_offset =3D MISC_ISR_UMSK_OFFSET, + .scpu_int_en_offset =3D MISC_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask =3D rtd1319d_misc_isr_to_scpu_int_en_mask, + .cfg =3D rtd1319d_intc_misc_cfgs, + .cfg_num =3D ARRAY_SIZE(rtd1319d_intc_misc_cfgs), +}; + +static const struct of_device_id realtek_intc_rtd1319d_dt_matches[] =3D { + { + .compatible =3D "realtek,rtd1319d-intc-iso", + .data =3D &rtd1319d_intc_iso_info, + }, { + .compatible =3D "realtek,rtd1319d-intc-misc", + .data =3D &rtd1319d_intc_misc_info, + }, + { /* sentinel */ } +}; + +static int realtek_intc_rtd1319d_suspend(struct device *dev) +{ + struct realtek_intc_data *data =3D dev_get_drvdata(dev); + const struct realtek_intc_info *info =3D data->info; + + data->saved_en =3D readl(data->base + info->scpu_int_en_offset); + + writel(DISABLE_INTC, data->base + info->scpu_int_en_offset); + writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset); + writel(CLEAN_INTC_STATUS, data->base + info->isr_offset); + + return 0; +} + +static int realtek_intc_rtd1319d_resume(struct device *dev) +{ + struct realtek_intc_data *data =3D dev_get_drvdata(dev); + const struct realtek_intc_info *info =3D data->info; + + writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset); + writel(CLEAN_INTC_STATUS, data->base + info->isr_offset); + writel(data->saved_en, data->base + info->scpu_int_en_offset); + + return 0; +} + +static const struct dev_pm_ops realtek_intc_rtd1319d_pm_ops =3D { + .suspend_noirq =3D realtek_intc_rtd1319d_suspend, + .resume_noirq =3D realtek_intc_rtd1319d_resume, +}; + +static int rtd1319d_intc_probe(struct platform_device *pdev) +{ + const struct realtek_intc_info *info; + + info =3D of_device_get_match_data(&pdev->dev); + if (!info) + return -EINVAL; + + return realtek_intc_probe(pdev, info); +} + +static struct platform_driver realtek_intc_rtd1319d_driver =3D { + .probe =3D rtd1319d_intc_probe, + .driver =3D { + .name =3D "realtek_intc_rtd1319d", + .of_match_table =3D realtek_intc_rtd1319d_dt_matches, + .suppress_bind_attrs =3D true, + .pm =3D &realtek_intc_rtd1319d_pm_ops, + }, +}; + +static int __init realtek_intc_rtd1319d_init(void) +{ + return platform_driver_register(&realtek_intc_rtd1319d_driver); +} +core_initcall(realtek_intc_rtd1319d_init); + +static void __exit realtek_intc_rtd1319d_exit(void) +{ + platform_driver_unregister(&realtek_intc_rtd1319d_driver); +} +module_exit(realtek_intc_rtd1319d_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek RTD1319D Interrupt Controller Driver"); --=20 2.25.1 From nobody Mon Dec 29 09:31:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F411C4167B for ; Wed, 29 Nov 2023 05:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376979AbjK2Fo5 (ORCPT ); Wed, 29 Nov 2023 00:44:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376968AbjK2Foq (ORCPT ); Wed, 29 Nov 2023 00:44:46 -0500 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F3A31BCE; Tue, 28 Nov 2023 21:44:51 -0800 (PST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 3AT5icP432554707, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36506.realtek.com.tw[172.21.6.27]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 3AT5icP432554707 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Nov 2023 13:44:38 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36506.realtek.com.tw (172.21.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Wed, 29 Nov 2023 13:44:39 +0800 Received: from james-bs01.realtek.com.tw (172.21.190.247) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Wed, 29 Nov 2023 13:44:38 +0800 From: James Tai To: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , James Tai CC: , , "kernel test robot" Subject: [PATCH v3 5/6] irqchip: Introduce RTD1325 support using the Realtek common interrupt controller driver Date: Wed, 29 Nov 2023 13:43:38 +0800 Message-ID: <20231129054339.3054202-6-james.tai@realtek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231129054339.3054202-1-james.tai@realtek.com> References: <20231129054339.3054202-1-james.tai@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.21.190.247] X-ClientProxiedBy: RTEXH36506.realtek.com.tw (172.21.6.27) To RTEXMBS03.realtek.com.tw (172.21.6.96) X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the RTD1325 platform. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202311061408.qjl1jfVl-lkp@int= el.com/ CC: Thomas Gleixner CC: Marc Zyngier CC: linux-kernel@vger.kernel.org Signed-off-by: James Tai --- v2 to v3 change: - Unchanged v1 to v2 change: - Resolved kernel test robot build warnings - Replaced magic number with macro - Fixed code style issues drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-realtek-rtd1325.c | 227 ++++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 drivers/irqchip/irq-realtek-rtd1325.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index c6552c513442..65e2d67d1505 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -234,6 +234,12 @@ config REALTEK_RTD1319D_INTC help Support for Realtek RTD1319D Interrupt Controller. =20 +config REALTEK_RTD1325_INTC + tristate "Realtek RTD1325 interrupt controller" + select REALTEK_DHC_INTC + help + Support for Realtek RTD1325 Interrupt Controller. + config RENESAS_INTC_IRQPIN bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index c8adaed4c1b2..eaa12928d60b 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -50,6 +50,7 @@ obj-$(CONFIG_RDA_INTC) +=3D irq-rda-intc.o obj-$(CONFIG_REALTEK_DHC_INTC) +=3D irq-realtek-intc-common.o obj-$(CONFIG_REALTEK_RTD1319_INTC) +=3D irq-realtek-rtd1319.o obj-$(CONFIG_REALTEK_RTD1319D_INTC) +=3D irq-realtek-rtd1319d.o +obj-$(CONFIG_REALTEK_RTD1325_INTC) +=3D irq-realtek-rtd1325.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) +=3D irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) +=3D irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) +=3D irq-renesas-rza1.o diff --git a/drivers/irqchip/irq-realtek-rtd1325.c b/drivers/irqchip/irq-re= altek-rtd1325.c new file mode 100644 index 000000000000..7ff164795634 --- /dev/null +++ b/drivers/irqchip/irq-realtek-rtd1325.c @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1325 interrupt controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include + +#include "irq-realtek-intc-common.h" + +#define ISO_NMI_WDT_MASK 0x08008090 +#define ISO_NORMAL_MASK 0xf7ff7f6e +#define MISC_NORMAL_MASK 0xffe0ded6 +#define MISC_UART1_MASK 0x00000028 +#define MISC_UART2_MASK 0x00002100 + +#define ISO_ISR_EN_OFFSET 0x40 +#define ISO_ISR_OFFSET 0 +#define ISO_ISR_UMSK_OFFSET 0x4 +#define MISC_ISR_EN_OFFSET 0x80 +#define MISC_ISR_OFFSET 0xc +#define MISC_ISR_UMSK_OFFSET 0x8 + +enum rtd1325_iso_isr_bits { + RTD1325_ISO_ISR_TC3_SHIFT =3D 1, + RTD1325_ISO_ISR_UR0_SHIFT =3D 2, + RTD1325_ISO_ISR_LSADC0_SHIFT =3D 3, + RTD1325_ISO_ISR_WDOG1_NMI_SHIFT =3D 4, + RTD1325_ISO_ISR_IRDA_SHIFT =3D 5, + RTD1325_ISO_ISR_SPI1_SHIFT =3D 6, + RTD1325_ISO_ISR_WDOG2_NMI_SHIFT =3D 7, + RTD1325_ISO_ISR_I2C0_SHIFT =3D 8, + RTD1325_ISO_ISR_TC4_SHIFT =3D 9, + RTD1325_ISO_ISR_TC7_SHIFT =3D 10, + RTD1325_ISO_ISR_I2C1_SHIFT =3D 11, + RTD1325_ISO_ISR_HIFI_WAKEUP_SHIFT =3D 14, + RTD1325_ISO_ISR_WDOG4_NMI_SHIFT =3D 15, + RTD1325_ISO_ISR_TC8_SHIFT =3D 16, + RTD1325_ISO_ISR_VFD_SHIFT =3D 17, + RTD1325_ISO_ISR_VTC_SHIFT =3D 18, + RTD1325_ISO_ISR_GPIOA_SHIFT =3D 19, + RTD1325_ISO_ISR_GPIODA_SHIFT =3D 20, + RTD1325_ISO_ISR_ISO_MISC_SHIFT =3D 21, + RTD1325_ISO_ISR_CBUS_SHIFT =3D 22, + RTD1325_ISO_ISR_ETN_SHIFT =3D 23, + RTD1325_ISO_ISR_USB_HOST_SHIFT =3D 24, + RTD1325_ISO_ISR_USB_U3_DRD_SHIFT =3D 25, + RTD1325_ISO_ISR_USB_U2_DRD_SHIFT =3D 26, + RTD1325_ISO_ISR_WDOG3_NMI_SHIFT =3D 27, + RTD1325_ISO_ISR_PORB_HV_CEN_SHIFT =3D 28, + RTD1325_ISO_ISR_PORB_DV_CEN_SHIFT =3D 29, + RTD1325_ISO_ISR_PORB_AV_CEN_SHIFT =3D 30, + RTD1325_ISO_ISR_I2C1_REQ_SHIFT =3D 31, +}; + +static const u32 rtd1325_iso_isr_to_scpu_int_en_mask[32] =3D { + [RTD1325_ISO_ISR_SPI1_SHIFT] =3D BIT(1), + [RTD1325_ISO_ISR_UR0_SHIFT] =3D BIT(2), + [RTD1325_ISO_ISR_LSADC0_SHIFT] =3D BIT(3), + [RTD1325_ISO_ISR_IRDA_SHIFT] =3D BIT(5), + [RTD1325_ISO_ISR_I2C0_SHIFT] =3D BIT(8), + [RTD1325_ISO_ISR_I2C1_SHIFT] =3D BIT(11), + [RTD1325_ISO_ISR_VFD_SHIFT] =3D BIT(17), + [RTD1325_ISO_ISR_GPIOA_SHIFT] =3D BIT(19), + [RTD1325_ISO_ISR_GPIODA_SHIFT] =3D BIT(20), + [RTD1325_ISO_ISR_PORB_HV_CEN_SHIFT] =3D BIT(28), + [RTD1325_ISO_ISR_PORB_DV_CEN_SHIFT] =3D BIT(29), + [RTD1325_ISO_ISR_PORB_AV_CEN_SHIFT] =3D BIT(30), + [RTD1325_ISO_ISR_I2C1_REQ_SHIFT] =3D BIT(31), + [RTD1325_ISO_ISR_WDOG1_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1325_ISO_ISR_WDOG2_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1325_ISO_ISR_WDOG3_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1325_ISO_ISR_WDOG4_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, +}; + +enum rtd1325_misc_isr_bits { + RTD1325_ISR_UR1_SHIFT =3D 3, + RTD1325_ISR_TC5_SHIFT =3D 4, + RTD1325_ISR_UR1_TO_SHIFT =3D 5, + RTD1325_ISR_TC0_SHIFT =3D 6, + RTD1325_ISR_TC1_SHIFT =3D 7, + RTD1325_ISR_UR2_SHIFT =3D 8, + RTD1325_ISR_UR2_TO_SHIFT =3D 13, + RTD1325_ISR_I2C5_SHIFT =3D 14, + RTD1325_ISR_I2C4_SHIFT =3D 15, + RTD1325_ISR_DRTC_HSEC_SHIFT =3D 16, + RTD1325_ISR_DRTC_MIN_SHIFT =3D 17, + RTD1325_ISR_DRTC_HOUR_SHIFT =3D 18, + RTD1325_ISR_DRTC_DATE_SHIFT =3D 19, + RTD1325_ISR_DRTC_ALARM_SHIFT =3D 20, + RTD1325_ISR_I2C3_SHIFT =3D 23, + RTD1325_ISR_SC0_SHIFT =3D 24, + RTD1325_ISR_SC1_SHIFT =3D 25, + RTD1325_ISR_SPI_SHIFT =3D 27, + RTD1325_ISR_FAN_SHIFT =3D 29, +}; + +static const u32 rtd1325_misc_isr_to_scpu_int_en_mask[32] =3D { + [RTD1325_ISR_UR1_SHIFT] =3D BIT(3), + [RTD1325_ISR_UR1_TO_SHIFT] =3D BIT(5), + [RTD1325_ISR_UR2_TO_SHIFT] =3D BIT(6), + [RTD1325_ISR_UR2_SHIFT] =3D BIT(7), + [RTD1325_ISR_I2C5_SHIFT] =3D BIT(14), + [RTD1325_ISR_I2C4_SHIFT] =3D BIT(15), + [RTD1325_ISR_DRTC_HSEC_SHIFT] =3D BIT(16), + [RTD1325_ISR_DRTC_MIN_SHIFT] =3D BIT(17), + [RTD1325_ISR_DRTC_HOUR_SHIFT] =3D BIT(18), + [RTD1325_ISR_DRTC_DATE_SHIFT] =3D BIT(19), + [RTD1325_ISR_DRTC_ALARM_SHIFT] =3D BIT(20), + [RTD1325_ISR_SC0_SHIFT] =3D BIT(24), + [RTD1325_ISR_SC1_SHIFT] =3D BIT(25), + [RTD1325_ISR_SPI_SHIFT] =3D BIT(27), + [RTD1325_ISR_I2C3_SHIFT] =3D BIT(28), + [RTD1325_ISR_FAN_SHIFT] =3D BIT(29), +}; + +static struct realtek_intc_subset_cfg rtd1325_intc_iso_cfgs[] =3D { + { ISO_NORMAL_MASK, }, + { ISO_NMI_WDT_MASK, }, +}; + +static const struct realtek_intc_info rtd1325_intc_iso_info =3D { + .isr_offset =3D ISO_ISR_OFFSET, + .umsk_isr_offset =3D ISO_ISR_UMSK_OFFSET, + .scpu_int_en_offset =3D ISO_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask =3D rtd1325_iso_isr_to_scpu_int_en_mask, + .cfg =3D rtd1325_intc_iso_cfgs, + .cfg_num =3D ARRAY_SIZE(rtd1325_intc_iso_cfgs), +}; + +static struct realtek_intc_subset_cfg rtd1325_intc_misc_cfgs[] =3D { + { MISC_NORMAL_MASK, }, + { MISC_UART1_MASK, }, + { MISC_UART2_MASK, }, +}; + +static const struct realtek_intc_info rtd1325_intc_misc_info =3D { + .isr_offset =3D MISC_ISR_OFFSET, + .umsk_isr_offset =3D MISC_ISR_UMSK_OFFSET, + .scpu_int_en_offset =3D MISC_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask =3D rtd1325_misc_isr_to_scpu_int_en_mask, + .cfg =3D rtd1325_intc_misc_cfgs, + .cfg_num =3D ARRAY_SIZE(rtd1325_intc_misc_cfgs), +}; + +static const struct of_device_id realtek_intc_rtd1325_dt_matches[] =3D { + { + .compatible =3D "realtek,rtd1325-intc-iso", + .data =3D &rtd1325_intc_iso_info, + }, { + .compatible =3D "realtek,rtd1325-intc-misc", + .data =3D &rtd1325_intc_misc_info, + }, + { /* sentinel */ } +}; + +static int realtek_intc_rtd1325_suspend(struct device *dev) +{ + struct realtek_intc_data *data =3D dev_get_drvdata(dev); + const struct realtek_intc_info *info =3D data->info; + + data->saved_en =3D readl(data->base + info->scpu_int_en_offset); + + writel(DISABLE_INTC, data->base + info->scpu_int_en_offset); + writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset); + writel(CLEAN_INTC_STATUS, data->base + info->isr_offset); + + return 0; +} + +static int realtek_intc_rtd1325_resume(struct device *dev) +{ + struct realtek_intc_data *data =3D dev_get_drvdata(dev); + const struct realtek_intc_info *info =3D data->info; + + writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset); + writel(CLEAN_INTC_STATUS, data->base + info->isr_offset); + writel(data->saved_en, data->base + info->scpu_int_en_offset); + + return 0; +} + +static const struct dev_pm_ops realtek_intc_rtd1325_pm_ops =3D { + .suspend_noirq =3D realtek_intc_rtd1325_suspend, + .resume_noirq =3D realtek_intc_rtd1325_resume, +}; + +static int rtd1325_intc_probe(struct platform_device *pdev) +{ + const struct realtek_intc_info *info; + + info =3D of_device_get_match_data(&pdev->dev); + if (!info) + return -EINVAL; + + return realtek_intc_probe(pdev, info); +} + +static struct platform_driver realtek_intc_rtd1325_driver =3D { + .probe =3D rtd1325_intc_probe, + .driver =3D { + .name =3D "realtek_intc_rtd1325", + .of_match_table =3D realtek_intc_rtd1325_dt_matches, + .suppress_bind_attrs =3D true, + .pm =3D &realtek_intc_rtd1325_pm_ops, + }, +}; + +static int __init realtek_intc_rtd1325_init(void) +{ + return platform_driver_register(&realtek_intc_rtd1325_driver); +} +core_initcall(realtek_intc_rtd1325_init); + +static void __exit realtek_intc_rtd1325_exit(void) +{ + platform_driver_unregister(&realtek_intc_rtd1325_driver); +} +module_exit(realtek_intc_rtd1325_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek RTD1325 Interrupt Controller Driver"); --=20 2.25.1 From nobody Mon Dec 29 09:31:56 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 432DAC4167B for ; Wed, 29 Nov 2023 05:45:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376990AbjK2FpA (ORCPT ); Wed, 29 Nov 2023 00:45:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376982AbjK2Fos (ORCPT ); Wed, 29 Nov 2023 00:44:48 -0500 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AD6619B1; Tue, 28 Nov 2023 21:44:53 -0800 (PST) X-SpamFilter-By: ArmorX SpamTrap 5.78 with qID 3AT5ieCT32554713, This message is accepted by code: ctloc85258 Received: from mail.realtek.com (rtexh36505.realtek.com.tw[172.21.6.25]) by rtits2.realtek.com.tw (8.15.2/2.95/5.92) with ESMTPS id 3AT5ieCT32554713 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 29 Nov 2023 13:44:40 +0800 Received: from RTEXMBS03.realtek.com.tw (172.21.6.96) by RTEXH36505.realtek.com.tw (172.21.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.32; Wed, 29 Nov 2023 13:44:40 +0800 Received: from james-bs01.realtek.com.tw (172.21.190.247) by RTEXMBS03.realtek.com.tw (172.21.6.96) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.7; Wed, 29 Nov 2023 13:44:40 +0800 From: James Tai To: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Conor Dooley , James Tai CC: , , "kernel test robot" Subject: [PATCH v3 6/6] irqchip: Introduce RTD1619B support using the Realtek common interrupt controller driver Date: Wed, 29 Nov 2023 13:43:39 +0800 Message-ID: <20231129054339.3054202-7-james.tai@realtek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231129054339.3054202-1-james.tai@realtek.com> References: <20231129054339.3054202-1-james.tai@realtek.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [172.21.190.247] X-ClientProxiedBy: RTEXH36506.realtek.com.tw (172.21.6.27) To RTEXMBS03.realtek.com.tw (172.21.6.96) X-KSE-ServerInfo: RTEXMBS03.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-ServerInfo: RTEXH36505.realtek.com.tw, 9 X-KSE-AntiSpam-Interceptor-Info: fallback X-KSE-Antivirus-Interceptor-Info: fallback X-KSE-AntiSpam-Interceptor-Info: fallback Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the RTD1619B platform. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202311061822.551ieaoI-lkp@int= el.com/ CC: Thomas Gleixner CC: Marc Zyngier CC: linux-kernel@vger.kernel.org Signed-off-by: James Tai --- v2 to v3 change: - Unchanged v1 to v2 change: - Resolved kernel test robot build warnings - Replaced magic number with macro - Fixed code style issues drivers/irqchip/Kconfig | 6 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-realtek-rtd1619b.c | 217 +++++++++++++++++++++++++ 3 files changed, 224 insertions(+) create mode 100644 drivers/irqchip/irq-realtek-rtd1619b.c diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 65e2d67d1505..c5b2762df420 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -240,6 +240,12 @@ config REALTEK_RTD1325_INTC help Support for Realtek RTD1325 Interrupt Controller. =20 +config REALTEK_RTD1619B_INTC + tristate "Realtek RTD1619B interrupt controller" + select REALTEK_DHC_INTC + help + Support for Realtek RTD1619B Interrupt Controller. + config RENESAS_INTC_IRQPIN bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST select IRQ_DOMAIN diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index eaa12928d60b..da308aefcb87 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_REALTEK_DHC_INTC) +=3D irq-realtek-intc-com= mon.o obj-$(CONFIG_REALTEK_RTD1319_INTC) +=3D irq-realtek-rtd1319.o obj-$(CONFIG_REALTEK_RTD1319D_INTC) +=3D irq-realtek-rtd1319d.o obj-$(CONFIG_REALTEK_RTD1325_INTC) +=3D irq-realtek-rtd1325.o +obj-$(CONFIG_REALTEK_RTD1619B_INTC) +=3D irq-realtek-rtd1619b.o obj-$(CONFIG_RENESAS_INTC_IRQPIN) +=3D irq-renesas-intc-irqpin.o obj-$(CONFIG_RENESAS_IRQC) +=3D irq-renesas-irqc.o obj-$(CONFIG_RENESAS_RZA1_IRQC) +=3D irq-renesas-rza1.o diff --git a/drivers/irqchip/irq-realtek-rtd1619b.c b/drivers/irqchip/irq-r= ealtek-rtd1619b.c new file mode 100644 index 000000000000..27bc4f9ef3bf --- /dev/null +++ b/drivers/irqchip/irq-realtek-rtd1619b.c @@ -0,0 +1,217 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) +/* + * Realtek RTD1619B interrupt controller driver + * + * Copyright (c) 2023 Realtek Semiconductor Corporation + */ + +#include +#include +#include +#include +#include + +#include "irq-realtek-intc-common.h" + +#define ISO_NMI_WDT_MASK 0x08008090 +#define ISO_NORMAL_MASK 0xf7ff7f6e +#define MISC_NORMAL_MASK 0xffffded6 +#define MISC_UART1_MASK 0x00000028 +#define MISC_UART2_MASK 0x00002100 + +#define ISO_ISR_EN_OFFSET 0x40 +#define ISO_ISR_OFFSET 0 +#define ISO_ISR_UMSK_OFFSET 0x4 +#define MISC_ISR_EN_OFFSET 0x80 +#define MISC_ISR_OFFSET 0xc +#define MISC_ISR_UMSK_OFFSET 0x8 + +enum rtd1619b_iso_isr_bits { + RTD1619B_ISO_ISR_TC3_SHIFT =3D 1, + RTD1619B_ISO_ISR_UR0_SHIFT =3D 2, + RTD1619B_ISO_ISR_LSADC0_SHIFT =3D 3, + RTD1619B_ISO_ISR_WDOG1_NMI_SHIFT =3D 4, + RTD1619B_ISO_ISR_IRDA_SHIFT =3D 5, + RTD1619B_ISO_ISR_SPI1_SHIFT =3D 6, + RTD1619B_ISO_ISR_WDOG2_NMI_SHIFT =3D 7, + RTD1619B_ISO_ISR_I2C0_SHIFT =3D 8, + RTD1619B_ISO_ISR_TC4_SHIFT =3D 9, + RTD1619B_ISO_ISR_TC7_SHIFT =3D 10, + RTD1619B_ISO_ISR_I2C1_SHIFT =3D 11, + RTD1619B_ISO_ISR_HIFI_WAKEUP_SHIFT =3D 14, + RTD1619B_ISO_ISR_WDOG4_NMI_SHIFT =3D 15, + RTD1619B_ISO_ISR_TC8_SHIFT =3D 16, + RTD1619B_ISO_ISR_VFD_SHIFT =3D 17, + RTD1619B_ISO_ISR_VTC_SHIFT =3D 18, + RTD1619B_ISO_ISR_GPIOA_SHIFT =3D 19, + RTD1619B_ISO_ISR_GPIODA_SHIFT =3D 20, + RTD1619B_ISO_ISR_ISO_MISC_SHIFT =3D 21, + RTD1619B_ISO_ISR_CBUS_SHIFT =3D 22, + RTD1619B_ISO_ISR_ETN_SHIFT =3D 23, + RTD1619B_ISO_ISR_USB_HOST_SHIFT =3D 24, + RTD1619B_ISO_ISR_USB_U3_DRD_SHIFT =3D 25, + RTD1619B_ISO_ISR_USB_U2_DRD_SHIFT =3D 26, + RTD1619B_ISO_ISR_WDOG3_NMI_SHIFT =3D 27, + RTD1619B_ISO_ISR_PORB_HV_CEN_SHIFT =3D 28, + RTD1619B_ISO_ISR_PORB_DV_CEN_SHIFT =3D 29, + RTD1619B_ISO_ISR_PORB_AV_CEN_SHIFT =3D 30, + RTD1619B_ISO_ISR_I2C1_REQ_SHIFT =3D 31, +}; + +static const u32 rtd1619b_iso_isr_to_scpu_int_en_mask[32] =3D { + [RTD1619B_ISO_ISR_SPI1_SHIFT] =3D BIT(1), + [RTD1619B_ISO_ISR_UR0_SHIFT] =3D BIT(2), + [RTD1619B_ISO_ISR_LSADC0_SHIFT] =3D BIT(3), + [RTD1619B_ISO_ISR_IRDA_SHIFT] =3D BIT(5), + [RTD1619B_ISO_ISR_I2C0_SHIFT] =3D BIT(8), + [RTD1619B_ISO_ISR_I2C1_SHIFT] =3D BIT(11), + [RTD1619B_ISO_ISR_VFD_SHIFT] =3D BIT(17), + [RTD1619B_ISO_ISR_GPIOA_SHIFT] =3D BIT(19), + [RTD1619B_ISO_ISR_GPIODA_SHIFT] =3D BIT(20), + [RTD1619B_ISO_ISR_PORB_HV_CEN_SHIFT] =3D BIT(28), + [RTD1619B_ISO_ISR_PORB_DV_CEN_SHIFT] =3D BIT(29), + [RTD1619B_ISO_ISR_PORB_AV_CEN_SHIFT] =3D BIT(30), + [RTD1619B_ISO_ISR_I2C1_REQ_SHIFT] =3D BIT(31), + [RTD1619B_ISO_ISR_WDOG1_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1619B_ISO_ISR_WDOG2_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1619B_ISO_ISR_WDOG3_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, + [RTD1619B_ISO_ISR_WDOG4_NMI_SHIFT] =3D IRQ_ALWAYS_ENABLED, +}; + +enum rtd1619b_misc_isr_bits { + RTD1619B_ISR_UR1_SHIFT =3D 3, + RTD1619B_ISR_TC5_SHIFT =3D 4, + RTD1619B_ISR_UR1_TO_SHIFT =3D 5, + RTD1619B_ISR_TC0_SHIFT =3D 6, + RTD1619B_ISR_TC1_SHIFT =3D 7, + RTD1619B_ISR_UR2_SHIFT =3D 8, + RTD1619B_ISR_UR2_TO_SHIFT =3D 13, + RTD1619B_ISR_I2C5_SHIFT =3D 14, + RTD1619B_ISR_I2C4_SHIFT =3D 15, + RTD1619B_ISR_I2C3_SHIFT =3D 23, + RTD1619B_ISR_SC0_SHIFT =3D 24, + RTD1619B_ISR_SC1_SHIFT =3D 25, + RTD1619B_ISR_SPI_SHIFT =3D 27, + RTD1619B_ISR_FAN_SHIFT =3D 29, +}; + +static const u32 rtd1619b_misc_isr_to_scpu_int_en_mask[32] =3D { + [RTD1619B_ISR_UR1_SHIFT] =3D BIT(3), + [RTD1619B_ISR_UR1_TO_SHIFT] =3D BIT(5), + [RTD1619B_ISR_UR2_TO_SHIFT] =3D BIT(6), + [RTD1619B_ISR_UR2_SHIFT] =3D BIT(7), + [RTD1619B_ISR_I2C5_SHIFT] =3D BIT(14), + [RTD1619B_ISR_I2C4_SHIFT] =3D BIT(15), + [RTD1619B_ISR_SC0_SHIFT] =3D BIT(24), + [RTD1619B_ISR_SC1_SHIFT] =3D BIT(25), + [RTD1619B_ISR_SPI_SHIFT] =3D BIT(27), + [RTD1619B_ISR_I2C3_SHIFT] =3D BIT(28), + [RTD1619B_ISR_FAN_SHIFT] =3D BIT(29), +}; + +static struct realtek_intc_subset_cfg rtd1619b_intc_iso_cfgs[] =3D { + { ISO_NORMAL_MASK, }, + { ISO_NMI_WDT_MASK, }, +}; + +static const struct realtek_intc_info rtd1619b_intc_iso_info =3D { + .isr_offset =3D ISO_ISR_OFFSET, + .umsk_isr_offset =3D ISO_ISR_UMSK_OFFSET, + .scpu_int_en_offset =3D ISO_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask =3D rtd1619b_iso_isr_to_scpu_int_en_mask, + .cfg =3D rtd1619b_intc_iso_cfgs, + .cfg_num =3D ARRAY_SIZE(rtd1619b_intc_iso_cfgs), +}; + +static struct realtek_intc_subset_cfg rtd1619b_intc_misc_cfgs[] =3D { + { MISC_NORMAL_MASK, }, + { MISC_UART1_MASK, }, + { MISC_UART2_MASK, }, +}; + +static const struct realtek_intc_info rtd1619b_intc_misc_info =3D { + .isr_offset =3D MISC_ISR_OFFSET, + .umsk_isr_offset =3D MISC_ISR_UMSK_OFFSET, + .scpu_int_en_offset =3D MISC_ISR_EN_OFFSET, + .isr_to_scpu_int_en_mask =3D rtd1619b_misc_isr_to_scpu_int_en_mask, + .cfg =3D rtd1619b_intc_misc_cfgs, + .cfg_num =3D ARRAY_SIZE(rtd1619b_intc_misc_cfgs), +}; + +static const struct of_device_id realtek_intc_rtd1619b_dt_matches[] =3D { + { + .compatible =3D "realtek,rtd1619b-intc-iso", + .data =3D &rtd1619b_intc_iso_info, + }, { + .compatible =3D "realtek,rtd1619b-intc-misc", + .data =3D &rtd1619b_intc_misc_info, + }, + { /* sentinel */ } +}; + +static int realtek_intc_rtd1619b_suspend(struct device *dev) +{ + struct realtek_intc_data *data =3D dev_get_drvdata(dev); + const struct realtek_intc_info *info =3D data->info; + + data->saved_en =3D readl(data->base + info->scpu_int_en_offset); + + writel(DISABLE_INTC, data->base + info->scpu_int_en_offset); + writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset); + writel(CLEAN_INTC_STATUS, data->base + info->isr_offset); + + return 0; +} + +static int realtek_intc_rtd1619b_resume(struct device *dev) +{ + struct realtek_intc_data *data =3D dev_get_drvdata(dev); + const struct realtek_intc_info *info =3D data->info; + + writel(CLEAN_INTC_STATUS, data->base + info->umsk_isr_offset); + writel(CLEAN_INTC_STATUS, data->base + info->isr_offset); + writel(data->saved_en, data->base + info->scpu_int_en_offset); + + return 0; +} + +static const struct dev_pm_ops realtek_intc_rtd1619b_pm_ops =3D { + .suspend_noirq =3D realtek_intc_rtd1619b_suspend, + .resume_noirq =3D realtek_intc_rtd1619b_resume, +}; + +static int rtd1619b_intc_probe(struct platform_device *pdev) +{ + const struct realtek_intc_info *info; + + info =3D of_device_get_match_data(&pdev->dev); + if (!info) + return -EINVAL; + + return realtek_intc_probe(pdev, info); +} + +static struct platform_driver realtek_intc_rtd1619b_driver =3D { + .probe =3D rtd1619b_intc_probe, + .driver =3D { + .name =3D "realtek_intc_rtd1619b", + .of_match_table =3D realtek_intc_rtd1619b_dt_matches, + .suppress_bind_attrs =3D true, + .pm =3D &realtek_intc_rtd1619b_pm_ops, + }, +}; + +static int __init realtek_intc_rtd1619b_init(void) +{ + return platform_driver_register(&realtek_intc_rtd1619b_driver); +} +core_initcall(realtek_intc_rtd1619b_init); + +static void __exit realtek_intc_rtd1619b_exit(void) +{ + platform_driver_unregister(&realtek_intc_rtd1619b_driver); +} +module_exit(realtek_intc_rtd1619b_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Realtek RTD1619B Interrupt Controller Driver"); --=20 2.25.1