From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF60C4167B for ; Tue, 28 Nov 2023 14:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345578AbjK1OIX (ORCPT ); Tue, 28 Nov 2023 09:08:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345543AbjK1OIU (ORCPT ); Tue, 28 Nov 2023 09:08:20 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC92410D2 for ; Tue, 28 Nov 2023 06:08:25 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 43C576000B; Tue, 28 Nov 2023 14:08:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180504; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=W+NuN2c3yCbJwvuCQZryV4FanZJ9M0VW1pSDKoZMKUY=; b=VrveIm2X+T9gvKBjigZ0zDr4kXiXwJYibQDd4vI+H7DS2xf2o2sD7I446+59Hr5e7cAotp GKBP0+CiZQGwPsR3qZ1N4i7eUTd8aNo2eMp0Kl3PqskNUJ7i9H+91M2lHOxsD1vr+DJD+w XoajG6QlgEv0DPQlbe4GguvNL29atkvPicytID6hui0klEAeXdmxMp1rmxH274aLackXZV tw+kuTkmHuH8iG9/1Qu+2GYy2EHSJdI0ZYP983CYfC6TeYjrSXcbpyaKaL7y4xDxb8BlP4 y+oh5SoZvkq2V8kycJJsmSkQwdeymsToY7L0YM5xU95NLfHQj0TgWU0xi2oOKg== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 01/17] soc: fsl: cpm1: tsa: Fix __iomem addresses declaration Date: Tue, 28 Nov 2023 15:08:00 +0100 Message-ID: <20231128140818.261541-2-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Running sparse (make C=3D1) on tsa.c raises a lot of warning such as: --- 8< --- warning: incorrect type in assignment (different address spaces) expected void *[noderef] si_regs got void [noderef] __iomem * --- 8< --- Indeed, some variable were declared 'type *__iomem var' instead of 'type __iomem *var'. Use the correct declaration to remove these warnings. Fixes: 1d4ba0b81c1c ("soc: fsl: cpm1: Add support for TSA") Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/tsa.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/soc/fsl/qe/tsa.c b/drivers/soc/fsl/qe/tsa.c index 3f9981335590..6c5741cf5e9d 100644 --- a/drivers/soc/fsl/qe/tsa.c +++ b/drivers/soc/fsl/qe/tsa.c @@ -98,9 +98,9 @@ #define TSA_SIRP 0x10 =20 struct tsa_entries_area { - void *__iomem entries_start; - void *__iomem entries_next; - void *__iomem last_entry; + void __iomem *entries_start; + void __iomem *entries_next; + void __iomem *last_entry; }; =20 struct tsa_tdm { @@ -117,8 +117,8 @@ struct tsa_tdm { =20 struct tsa { struct device *dev; - void *__iomem si_regs; - void *__iomem si_ram; + void __iomem *si_regs; + void __iomem *si_ram; resource_size_t si_ram_sz; spinlock_t lock; int tdms; /* TSA_TDMx ORed */ @@ -135,27 +135,27 @@ static inline struct tsa *tsa_serial_get_tsa(struct t= sa_serial *tsa_serial) return container_of(tsa_serial, struct tsa, serials[tsa_serial->id]); } =20 -static inline void tsa_write32(void *__iomem addr, u32 val) +static inline void tsa_write32(void __iomem *addr, u32 val) { iowrite32be(val, addr); } =20 -static inline void tsa_write8(void *__iomem addr, u32 val) +static inline void tsa_write8(void __iomem *addr, u32 val) { iowrite8(val, addr); } =20 -static inline u32 tsa_read32(void *__iomem addr) +static inline u32 tsa_read32(void __iomem *addr) { return ioread32be(addr); } =20 -static inline void tsa_clrbits32(void *__iomem addr, u32 clr) +static inline void tsa_clrbits32(void __iomem *addr, u32 clr) { tsa_write32(addr, tsa_read32(addr) & ~clr); } =20 -static inline void tsa_clrsetbits32(void *__iomem addr, u32 clr, u32 set) +static inline void tsa_clrsetbits32(void __iomem *addr, u32 clr, u32 set) { tsa_write32(addr, (tsa_read32(addr) & ~clr) | set); } @@ -313,7 +313,7 @@ static u32 tsa_serial_id2csel(struct tsa *tsa, u32 seri= al_id) static int tsa_add_entry(struct tsa *tsa, struct tsa_entries_area *area, u32 count, u32 serial_id) { - void *__iomem addr; + void __iomem *addr; u32 left; u32 val; u32 cnt; --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8FF1C4167B for ; Tue, 28 Nov 2023 14:08:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345619AbjK1OIZ (ORCPT ); Tue, 28 Nov 2023 09:08:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35766 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345570AbjK1OIU (ORCPT ); Tue, 28 Nov 2023 09:08:20 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9AF5C1BE for ; Tue, 28 Nov 2023 06:08:26 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 487EF6000E; Tue, 28 Nov 2023 14:08:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180505; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0wvI1tFhKePXdW/LM4A6s3+Ocv0iUTHrjsQSlsDC2Ew=; b=iof4yAQvnhIgigz0o8FNaedVX+mM3Gl853qCtaOEZfqnl3C8ygCo8yOWR2ac60CBFvS3uS 9SqXZM2k/ww6UkQWUzKjF5LVcdG0F410ZYR/eDfA6CSbELAKW+XAT6DMt2t+wX7LAAbpoa 3LVQ1t0pP5h1qeEGNT7xsP1YMKk92xDDWjVD83/0ly1n2rFZN2jXIqiL8p6oEQn7lNxVkk PurC7BoW699mvYmwE3OcYdQHDp2tLv9IsHDTfbXUD4xpNWtXReqnENJPMxLJACruYM6HHM Wo+uB6fAmtsfS+0bc5hpbvEfeSyv4nO/wKJ1lsGY9rALSmfXGsiN2/O6s8Q9+A== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 02/17] soc: fsl: cpm1: qmc: Fix __iomem addresses declaration Date: Tue, 28 Nov 2023 15:08:01 +0100 Message-ID: <20231128140818.261541-3-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Running sparse (make C=3D1) on qmc.c raises a lot of warning such as: ... warning: incorrect type in assignment (different address spaces) expected struct cpm_buf_desc [usertype] *[noderef] __iomem bd got struct cpm_buf_desc [noderef] [usertype] __iomem *txbd_free ... Indeed, some variable were declared 'type *__iomem var' instead of 'type __iomem *var'. Use the correct declaration to remove these warnings. Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC") Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 92ec76c03965..3f3de1351c96 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -175,7 +175,7 @@ struct qmc_chan { struct list_head list; unsigned int id; struct qmc *qmc; - void *__iomem s_param; + void __iomem *s_param; enum qmc_mode mode; u64 tx_ts_mask; u64 rx_ts_mask; @@ -203,9 +203,9 @@ struct qmc_chan { struct qmc { struct device *dev; struct tsa_serial *tsa_serial; - void *__iomem scc_regs; - void *__iomem scc_pram; - void *__iomem dpram; + void __iomem *scc_regs; + void __iomem *scc_pram; + void __iomem *dpram; u16 scc_pram_offset; cbd_t __iomem *bd_table; dma_addr_t bd_dma_addr; @@ -218,37 +218,37 @@ struct qmc { struct qmc_chan *chans[64]; }; =20 -static inline void qmc_write16(void *__iomem addr, u16 val) +static inline void qmc_write16(void __iomem *addr, u16 val) { iowrite16be(val, addr); } =20 -static inline u16 qmc_read16(void *__iomem addr) +static inline u16 qmc_read16(void __iomem *addr) { return ioread16be(addr); } =20 -static inline void qmc_setbits16(void *__iomem addr, u16 set) +static inline void qmc_setbits16(void __iomem *addr, u16 set) { qmc_write16(addr, qmc_read16(addr) | set); } =20 -static inline void qmc_clrbits16(void *__iomem addr, u16 clr) +static inline void qmc_clrbits16(void __iomem *addr, u16 clr) { qmc_write16(addr, qmc_read16(addr) & ~clr); } =20 -static inline void qmc_write32(void *__iomem addr, u32 val) +static inline void qmc_write32(void __iomem *addr, u32 val) { iowrite32be(val, addr); } =20 -static inline u32 qmc_read32(void *__iomem addr) +static inline u32 qmc_read32(void __iomem *addr) { return ioread32be(addr); } =20 -static inline void qmc_setbits32(void *__iomem addr, u32 set) +static inline void qmc_setbits32(void __iomem *addr, u32 set) { qmc_write32(addr, qmc_read32(addr) | set); } @@ -318,7 +318,7 @@ int qmc_chan_write_submit(struct qmc_chan *chan, dma_ad= dr_t addr, size_t length, { struct qmc_xfer_desc *xfer_desc; unsigned long flags; - cbd_t *__iomem bd; + cbd_t __iomem *bd; u16 ctrl; int ret; =20 @@ -374,7 +374,7 @@ static void qmc_chan_write_done(struct qmc_chan *chan) void (*complete)(void *context); unsigned long flags; void *context; - cbd_t *__iomem bd; + cbd_t __iomem *bd; u16 ctrl; =20 /* @@ -425,7 +425,7 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_add= r_t addr, size_t length, { struct qmc_xfer_desc *xfer_desc; unsigned long flags; - cbd_t *__iomem bd; + cbd_t __iomem *bd; u16 ctrl; int ret; =20 @@ -488,7 +488,7 @@ static void qmc_chan_read_done(struct qmc_chan *chan) void (*complete)(void *context, size_t size); struct qmc_xfer_desc *xfer_desc; unsigned long flags; - cbd_t *__iomem bd; + cbd_t __iomem *bd; void *context; u16 datalen; u16 ctrl; @@ -663,7 +663,7 @@ static void qmc_chan_reset_rx(struct qmc_chan *chan) { struct qmc_xfer_desc *xfer_desc; unsigned long flags; - cbd_t *__iomem bd; + cbd_t __iomem *bd; u16 ctrl; =20 spin_lock_irqsave(&chan->rx_lock, flags); @@ -694,7 +694,7 @@ static void qmc_chan_reset_tx(struct qmc_chan *chan) { struct qmc_xfer_desc *xfer_desc; unsigned long flags; - cbd_t *__iomem bd; + cbd_t __iomem *bd; u16 ctrl; =20 spin_lock_irqsave(&chan->tx_lock, flags); --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE3D6C07E97 for ; Tue, 28 Nov 2023 14:08:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345638AbjK1OI2 (ORCPT ); Tue, 28 Nov 2023 09:08:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345576AbjK1OIV (ORCPT ); Tue, 28 Nov 2023 09:08:21 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBAEAD6D for ; Tue, 28 Nov 2023 06:08:27 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 4563C60013; Tue, 28 Nov 2023 14:08:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180506; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qto69Sz/uzj7vWp+LbsEsH5JgUyWqrsMlRYbgKO+Ta4=; b=Ww25g59sPr1Wg8G2/+eo82WrZ6uxax9bU8yVHybpwtNwfTLCgJLf5wbu3NNaKdloqct4SN JOl71UmaiYH9SqoWEm99UYUjls414OjRBZgwcCCRyxgXM+DgHiE6WiGInOx5WCGdzHXc1F 5JutCdvL8M33BnD43l0Zh8DE7gfb/B2Jp/wei1EUp9HzqSHivwORgT3bCB+K83Yp157Knc IbPzw6Vd0r23914xtvob7oGilQ5CO/WiYAf5X4kE+y7MGAFcDlUHUdbT8gHvAQJfWnlUY7 K2lj3jmvc2L8Tb/VERzqS6pCaUHIe1CiReLbXjwgpUkt/bAlxy1311tX1O4q7g== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 03/17] soc: fsl: cpm1: qmc: Fix rx channel reset Date: Tue, 28 Nov 2023 15:08:02 +0100 Message-ID: <20231128140818.261541-4-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The qmc_chan_reset_rx() set the is_rx_stopped flag. This leads to an inconsistent state in the following sequence. qmc_chan_stop() qmc_chan_reset() Indeed, after the qmc_chan_reset() call, the channel must still be stopped. Only a qmc_chan_start() call can move the channel from stopped state to started state. Fix the issue removing the is_rx_stopped flag setting from qmc_chan_reset() Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC") Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 3f3de1351c96..2312152a44b3 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -685,7 +685,6 @@ static void qmc_chan_reset_rx(struct qmc_chan *chan) qmc_read16(chan->s_param + QMC_SPE_RBASE)); =20 chan->rx_pending =3D 0; - chan->is_rx_stopped =3D false; =20 spin_unlock_irqrestore(&chan->rx_lock, flags); } --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 491F7C4167B for ; Tue, 28 Nov 2023 14:08:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346132AbjK1OIi (ORCPT ); Tue, 28 Nov 2023 09:08:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49534 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345599AbjK1OIX (ORCPT ); Tue, 28 Nov 2023 09:08:23 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AB7FB5 for ; Tue, 28 Nov 2023 06:08:28 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 5579560003; Tue, 28 Nov 2023 14:08:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180507; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1gGnXAZGnIVxoZRxeuFx4MpzbHqCUh3ZPY6HLb7Vr4A=; b=WsD6Lzz9B55DltY1NVcvIJHBz75EtRr4zx04pkaaFf9tQGy2egh1PagI5ejZhJCtJh03Ys FP7ts99+e0dnnURyHG60hLXnavk7loT00WYOWHlBD4HPoZBuoVH5DXjj9i3mbhQdVe/fuE LEQaplcVPGzceciRdjppOsiLT7vJH8U6RkY8ejj8TBkZ66BYsI2bsS5LVfY7ODHvA9B2JV vt1sZGNxRRd8MzXObX+GQd2VWbd+VYtRTrd5dhJUNf1oeo1L7y9sVWxC/Pi2aIRztQ4IZt kopOP/72HHVVXhvex2yLb0Fs4/hpvHBcXxmxrbs26vcVc5NoeOGQJFsVWDaJNQ== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 04/17] soc: fsl: cpm1: qmc: Extend the API to provide Rx status Date: Tue, 28 Nov 2023 15:08:03 +0100 Message-ID: <20231128140818.261541-5-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In HDLC mode, some status flags related to the data read transfer can be set by the hardware and need to be known by a QMC consumer for further analysis. Extend the API in order to provide these transfer status flags at the read complete() call. In TRANSPARENT mode, these flags have no meaning. Keep only one read complete() API and update the consumers working in transparent mode. In this case, the newly introduced flags parameter is simply unused. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 29 +++++++++++++++++++++++++---- include/soc/fsl/qe/qmc.h | 15 ++++++++++++++- sound/soc/fsl/fsl_qmc_audio.c | 2 +- 3 files changed, 40 insertions(+), 6 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 2312152a44b3..4b4832d93c9b 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -166,7 +166,7 @@ struct qmc_xfer_desc { union { void (*tx_complete)(void *context); - void (*rx_complete)(void *context, size_t length); + void (*rx_complete)(void *context, size_t length, unsigned int flags); }; void *context; }; @@ -421,7 +421,8 @@ static void qmc_chan_write_done(struct qmc_chan *chan) } =20 int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t le= ngth, - void (*complete)(void *context, size_t length), void *context) + void (*complete)(void *context, size_t length, unsigned int flags), + void *context) { struct qmc_xfer_desc *xfer_desc; unsigned long flags; @@ -454,6 +455,10 @@ int qmc_chan_read_submit(struct qmc_chan *chan, dma_ad= dr_t addr, size_t length, xfer_desc->rx_complete =3D complete; xfer_desc->context =3D context; =20 + /* Clear previous status flags */ + ctrl &=3D ~(QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | QMC_BD_RX_NO | + QMC_BD_RX_AB | QMC_BD_RX_CR); + /* Activate the descriptor */ ctrl |=3D (QMC_BD_RX_E | QMC_BD_RX_UB); wmb(); /* Be sure to flush data before descriptor activation */ @@ -485,7 +490,7 @@ EXPORT_SYMBOL(qmc_chan_read_submit); =20 static void qmc_chan_read_done(struct qmc_chan *chan) { - void (*complete)(void *context, size_t size); + void (*complete)(void *context, size_t size, unsigned int flags); struct qmc_xfer_desc *xfer_desc; unsigned long flags; cbd_t __iomem *bd; @@ -527,7 +532,23 @@ static void qmc_chan_read_done(struct qmc_chan *chan) =20 if (complete) { spin_unlock_irqrestore(&chan->rx_lock, flags); - complete(context, datalen); + + /* + * Avoid conversion between internal hardware flags and + * the software API flags. + * -> Be sure that the software API flags are consistent + * with the hardware flags + */ + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_LAST !=3D QMC_BD_RX_L); + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_FIRST !=3D QMC_BD_RX_F); + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_OVF !=3D QMC_BD_RX_LG); + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_UNA !=3D QMC_BD_RX_NO); + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_ABORT !=3D QMC_BD_RX_AB); + BUILD_BUG_ON(QMC_RX_FLAG_HDLC_CRC !=3D QMC_BD_RX_CR); + + complete(context, datalen, + ctrl & (QMC_BD_RX_L | QMC_BD_RX_F | QMC_BD_RX_LG | + QMC_BD_RX_NO | QMC_BD_RX_AB | QMC_BD_RX_CR)); spin_lock_irqsave(&chan->rx_lock, flags); } =20 diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h index 3c61a50d2ae2..6f1d6cebc9fe 100644 --- a/include/soc/fsl/qe/qmc.h +++ b/include/soc/fsl/qe/qmc.h @@ -9,6 +9,7 @@ #ifndef __SOC_FSL_QMC_H__ #define __SOC_FSL_QMC_H__ =20 +#include #include =20 struct device_node; @@ -56,8 +57,20 @@ int qmc_chan_set_param(struct qmc_chan *chan, const stru= ct qmc_chan_param *param int qmc_chan_write_submit(struct qmc_chan *chan, dma_addr_t addr, size_t l= ength, void (*complete)(void *context), void *context); =20 +/* Flags available (ORed) for read complete() flags parameter in HDLC mode. + * No flags are available in transparent mode and the read complete() flags + * parameter has no meaning in transparent mode. + */ +#define QMC_RX_FLAG_HDLC_LAST BIT(11) /* Last in frame */ +#define QMC_RX_FLAG_HDLC_FIRST BIT(10) /* First in frame */ +#define QMC_RX_FLAG_HDLC_OVF BIT(5) /* Data overflow */ +#define QMC_RX_FLAG_HDLC_UNA BIT(4) /* Unaligned (ie. bits received not m= ultiple of 8) */ +#define QMC_RX_FLAG_HDLC_ABORT BIT(3) /* Received an abort sequence (seve= n consecutive ones) */ +#define QMC_RX_FLAG_HDLC_CRC BIT(2) /* CRC error */ + int qmc_chan_read_submit(struct qmc_chan *chan, dma_addr_t addr, size_t le= ngth, - void (*complete)(void *context, size_t length), + void (*complete)(void *context, size_t length, + unsigned int flags), void *context); =20 #define QMC_CHAN_READ (1<<0) diff --git a/sound/soc/fsl/fsl_qmc_audio.c b/sound/soc/fsl/fsl_qmc_audio.c index 56d6b0b039a2..bfaaa451735b 100644 --- a/sound/soc/fsl/fsl_qmc_audio.c +++ b/sound/soc/fsl/fsl_qmc_audio.c @@ -99,7 +99,7 @@ static void qmc_audio_pcm_write_complete(void *context) snd_pcm_period_elapsed(prtd->substream); } =20 -static void qmc_audio_pcm_read_complete(void *context, size_t length) +static void qmc_audio_pcm_read_complete(void *context, size_t length, unsi= gned int flags) { struct qmc_dai_prtd *prtd =3D context; int ret; --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAE24C4167B for ; Tue, 28 Nov 2023 14:08:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345525AbjK1OIm (ORCPT ); Tue, 28 Nov 2023 09:08:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345601AbjK1OIX (ORCPT ); Tue, 28 Nov 2023 09:08:23 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79D46D6D for ; Tue, 28 Nov 2023 06:08:29 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 4701A60004; Tue, 28 Nov 2023 14:08:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180508; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pfBJnitpzrGKndByRrnchYp3RVKMpoAglxZImjH5Vlc=; b=WisnC6DmGBJEdW2QianjEi+teiBnTMAz8qT2WWm5xb8WBIt+SB/Lo5G/M+uR48g0UU6/vL qpG12APlw0HfwpB/YSINf7HMEMQ7Q6OtZCMnJVBN4JADHonJPNNPgwRG/IvA706/qURFyZ Q0iLW4bkcvOBxupUHgDg7HFifihs9WJdWCSFRoRESmvh8z+VYGn1CUEcFksbwxfQkTxIxF rKM9QaAOcEbV1WkzhxBtvJ7kGPz0zjiafLAvBbm5RKhKmX1HFj1mDTjXAN9OdSo/E3uWl5 XMo3oYaYjX/7FvaWWXfxpb4W/h0Lk5wJZ0qRPh2gISjiDzVeMKnkQQvcmVaIag== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni , Andrew Lunn Subject: [PATCH 05/17] soc: fsl: cpm1: qmc: Remove inline function specifiers Date: Tue, 28 Nov 2023 15:08:04 +0100 Message-ID: <20231128140818.261541-6-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The inline function specifier is present on some functions but it is better to let the compiler decide inlining or not these functions. Remove inline specifiers. Fixes: 3178d58e0b97 ("soc: fsl: cpm1: Add support for QMC") Signed-off-by: Herve Codina Suggested-by: Andrew Lunn Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 4b4832d93c9b..27f2f16deac9 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -218,37 +218,37 @@ struct qmc { struct qmc_chan *chans[64]; }; =20 -static inline void qmc_write16(void __iomem *addr, u16 val) +static void qmc_write16(void __iomem *addr, u16 val) { iowrite16be(val, addr); } =20 -static inline u16 qmc_read16(void __iomem *addr) +static u16 qmc_read16(void __iomem *addr) { return ioread16be(addr); } =20 -static inline void qmc_setbits16(void __iomem *addr, u16 set) +static void qmc_setbits16(void __iomem *addr, u16 set) { qmc_write16(addr, qmc_read16(addr) | set); } =20 -static inline void qmc_clrbits16(void __iomem *addr, u16 clr) +static void qmc_clrbits16(void __iomem *addr, u16 clr) { qmc_write16(addr, qmc_read16(addr) & ~clr); } =20 -static inline void qmc_write32(void __iomem *addr, u32 val) +static void qmc_write32(void __iomem *addr, u32 val) { iowrite32be(val, addr); } =20 -static inline u32 qmc_read32(void __iomem *addr) +static u32 qmc_read32(void __iomem *addr) { return ioread32be(addr); } =20 -static inline void qmc_setbits32(void __iomem *addr, u32 set) +static void qmc_setbits32(void __iomem *addr, u32 set) { qmc_write32(addr, qmc_read32(addr) | set); } --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DDB2C4167B for ; Tue, 28 Nov 2023 14:08:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345654AbjK1OIo (ORCPT ); Tue, 28 Nov 2023 09:08:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345651AbjK1OId (ORCPT ); Tue, 28 Nov 2023 09:08:33 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E082D72 for ; Tue, 28 Nov 2023 06:08:30 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 37C2A6000F; Tue, 28 Nov 2023 14:08:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180509; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+2B6YUVBlU8nP98Gi7Yh575FhYxDZUhvB/s29okN5tk=; b=KPyUdJ0xO7QWgygD02j0RNLseVzKNmRyniX4pOsSzvLlzuUuMQRqgowuUQuXn8r9WrlEWq Wen3h3xoZwcrt6FBc8214Lbfy0X/PMyqfE/aQtW+vtLzJfqgafT0kf2FMafIcp4PB1f/PP GS+BOTEXJTXv4fsL+D9IAaR6m4Og6xtpjrOch/FfToMGIg3ECBsnFXIE3bE38L+WqPpClm E2zk6rVYgJI48bUQGCXFH+/Xjf+ooEs/kjpAwKzY345On6Ct8GuwwLWscfQlyd9ZhLBA3W NeZxWVFfNBn2DUmbghqIfoKK9dkUZVWR1UuW1azKzn80VDk7XxB3Ni37NzDerA== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 06/17] soc: fsl: cpm1: qmc: Add support for child devices Date: Tue, 28 Nov 2023 15:08:05 +0100 Message-ID: <20231128140818.261541-7-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" QMC child devices support is needed to avoid orphan DT nodes that use a simple DT phandle to reference a QMC channel. Allow to instantiate child devices and also extend the API to get the qmc_chan using a child device. Signed-off-by: Herve Codina --- drivers/soc/fsl/qe/qmc.c | 91 +++++++++++++++++++++++++++++++--------- include/soc/fsl/qe/qmc.h | 2 + 2 files changed, 73 insertions(+), 20 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 27f2f16deac9..e716f13669a0 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -1425,8 +1425,16 @@ static int qmc_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, qmc); =20 + /* Populate channel related devices */ + ret =3D devm_of_platform_populate(qmc->dev); + if (ret) + goto err_disable_txrx; + return 0; =20 +err_disable_txrx: + qmc_setbits32(qmc->scc_regs + SCC_GSMRL, 0); + err_disable_intr: qmc_write16(qmc->scc_regs + SCC_SCCM, 0); =20 @@ -1465,26 +1473,16 @@ static struct platform_driver qmc_driver =3D { }; module_platform_driver(qmc_driver); =20 -struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char= *phandle_name) +static struct qmc_chan *qmc_chan_get_from_qmc(struct device_node *qmc_np, = unsigned int chan_index) { - struct of_phandle_args out_args; struct platform_device *pdev; struct qmc_chan *qmc_chan; struct qmc *qmc; - int ret; =20 - ret =3D of_parse_phandle_with_fixed_args(np, phandle_name, 1, 0, - &out_args); - if (ret < 0) - return ERR_PTR(ret); - - if (!of_match_node(qmc_driver.driver.of_match_table, out_args.np)) { - of_node_put(out_args.np); + if (!of_match_node(qmc_driver.driver.of_match_table, qmc_np)) return ERR_PTR(-EINVAL); - } =20 - pdev =3D of_find_device_by_node(out_args.np); - of_node_put(out_args.np); + pdev =3D of_find_device_by_node(qmc_np); if (!pdev) return ERR_PTR(-ENODEV); =20 @@ -1494,17 +1492,12 @@ struct qmc_chan *qmc_chan_get_byphandle(struct devi= ce_node *np, const char *phan return ERR_PTR(-EPROBE_DEFER); } =20 - if (out_args.args_count !=3D 1) { + if (chan_index >=3D ARRAY_SIZE(qmc->chans)) { platform_device_put(pdev); return ERR_PTR(-EINVAL); } =20 - if (out_args.args[0] >=3D ARRAY_SIZE(qmc->chans)) { - platform_device_put(pdev); - return ERR_PTR(-EINVAL); - } - - qmc_chan =3D qmc->chans[out_args.args[0]]; + qmc_chan =3D qmc->chans[chan_index]; if (!qmc_chan) { platform_device_put(pdev); return ERR_PTR(-ENOENT); @@ -1512,8 +1505,44 @@ struct qmc_chan *qmc_chan_get_byphandle(struct devic= e_node *np, const char *phan =20 return qmc_chan; } + +struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char= *phandle_name) +{ + struct of_phandle_args out_args; + struct qmc_chan *qmc_chan; + int ret; + + ret =3D of_parse_phandle_with_fixed_args(np, phandle_name, 1, 0, + &out_args); + if (ret < 0) + return ERR_PTR(ret); + + if (out_args.args_count !=3D 1) { + of_node_put(out_args.np); + return ERR_PTR(-EINVAL); + } + + qmc_chan =3D qmc_chan_get_from_qmc(out_args.np, out_args.args[0]); + of_node_put(out_args.np); + return qmc_chan; +} EXPORT_SYMBOL(qmc_chan_get_byphandle); =20 +struct qmc_chan *qmc_chan_get_bychild(struct device_node *np) +{ + struct device_node *qmc_np; + u32 chan_index; + int ret; + + qmc_np =3D np->parent; + ret =3D of_property_read_u32(np, "reg", &chan_index); + if (ret) + return ERR_PTR(-EINVAL); + + return qmc_chan_get_from_qmc(qmc_np, chan_index); +} +EXPORT_SYMBOL(qmc_chan_get_bychild); + void qmc_chan_put(struct qmc_chan *chan) { put_device(chan->qmc->dev); @@ -1550,6 +1579,28 @@ struct qmc_chan *devm_qmc_chan_get_byphandle(struct = device *dev, } EXPORT_SYMBOL(devm_qmc_chan_get_byphandle); =20 +struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev, + struct device_node *np) +{ + struct qmc_chan *qmc_chan; + struct qmc_chan **dr; + + dr =3D devres_alloc(devm_qmc_chan_release, sizeof(*dr), GFP_KERNEL); + if (!dr) + return ERR_PTR(-ENOMEM); + + qmc_chan =3D qmc_chan_get_bychild(np); + if (!IS_ERR(qmc_chan)) { + *dr =3D qmc_chan; + devres_add(dev, dr); + } else { + devres_free(dr); + } + + return qmc_chan; +} +EXPORT_SYMBOL(devm_qmc_chan_get_bychild); + MODULE_AUTHOR("Herve Codina "); MODULE_DESCRIPTION("CPM QMC driver"); MODULE_LICENSE("GPL"); diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h index 6f1d6cebc9fe..166484bb4294 100644 --- a/include/soc/fsl/qe/qmc.h +++ b/include/soc/fsl/qe/qmc.h @@ -17,9 +17,11 @@ struct device; struct qmc_chan; =20 struct qmc_chan *qmc_chan_get_byphandle(struct device_node *np, const char= *phandle_name); +struct qmc_chan *qmc_chan_get_bychild(struct device_node *np); void qmc_chan_put(struct qmc_chan *chan); struct qmc_chan *devm_qmc_chan_get_byphandle(struct device *dev, struct de= vice_node *np, const char *phandle_name); +struct qmc_chan *devm_qmc_chan_get_bychild(struct device *dev, struct devi= ce_node *np); =20 enum qmc_mode { QMC_TRANSPARENT, --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94009C4167B for ; Tue, 28 Nov 2023 14:08:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346184AbjK1OIr (ORCPT ); Tue, 28 Nov 2023 09:08:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345911AbjK1OId (ORCPT ); Tue, 28 Nov 2023 09:08:33 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 455F410DA for ; Tue, 28 Nov 2023 06:08:31 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 2FC336000A; Tue, 28 Nov 2023 14:08:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180510; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eJosuVS67B3SR/85nZ6Wx85Kw09CqGjLv+oPzD8Rn2U=; b=SzXb9TkYchl0rTqkA3UtYkw9S5Q63KYUYtkv5muVcQhY2Mpmbp8AnNpltvyuXQk2SbD68s 2ah8fH3AJ16Xepf4+iflodsNaMjSCN+rJSVyTA5X6RDtdHdFdEZHQg6XSBAZUOKhFOGRNJ qAw5orshx7JWBNbHrJuVFBQOe9GQxBmZyN1T6O876SbXJZEwxxwWEB5dB2I7Uj2wwOipQC aVXtQb0If9te8ku9Ge+q9aszV1h813xL1ijHyv+AnY5vI03RW2nWDivkE47IJ4guK/ZRhr W7rYGAb+mLqFnujI3aXdI+d6XsmJ1srK4ECpTfAw2UyjD8Rv/1r71VKdJsztjg== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 07/17] soc: fsl: cpm1: qmc: Introduce available timeslots masks Date: Tue, 28 Nov 2023 15:08:06 +0100 Message-ID: <20231128140818.261541-8-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Available timeslots masks define timeslots available for the related channel. These timeslots are defined by the QMC binding. Timeslots used are initialized to available timeslots but can be a subset of available timeslots. This prepares the dynamic timeslots management (ie. changing timeslots at runtime). Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index e716f13669a0..0413e25d4c67 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -177,7 +177,9 @@ struct qmc_chan { struct qmc *qmc; void __iomem *s_param; enum qmc_mode mode; + u64 tx_ts_mask_avail; u64 tx_ts_mask; + u64 rx_ts_mask_avail; u64 rx_ts_mask; bool is_reverse_data; =20 @@ -875,7 +877,8 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct d= evice_node *np) of_node_put(chan_np); return ret; } - chan->tx_ts_mask =3D ts_mask; + chan->tx_ts_mask_avail =3D ts_mask; + chan->tx_ts_mask =3D chan->tx_ts_mask_avail; =20 ret =3D of_property_read_u64(chan_np, "fsl,rx-ts-mask", &ts_mask); if (ret) { @@ -884,7 +887,8 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct d= evice_node *np) of_node_put(chan_np); return ret; } - chan->rx_ts_mask =3D ts_mask; + chan->rx_ts_mask_avail =3D ts_mask; + chan->rx_ts_mask =3D chan->rx_ts_mask_avail; =20 mode =3D "transparent"; ret =3D of_property_read_string(chan_np, "fsl,operational-mode", &mode); --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26B9CC07E97 for ; Tue, 28 Nov 2023 14:09:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346195AbjK1OIw (ORCPT ); Tue, 28 Nov 2023 09:08:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345591AbjK1OIe (ORCPT ); Tue, 28 Nov 2023 09:08:34 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4902910F0 for ; Tue, 28 Nov 2023 06:08:32 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 2AA9460011; Tue, 28 Nov 2023 14:08:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180510; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=282hcH89JVtequN/Tx+bi17jTVwS4jbP3rmgY25XcYY=; b=Y5lQZvkffElWDiwaQeqCVprLA/uEKsTSaTYH/j9DbzELUeqUYwUzp0OGaTkaRjf1ZADs42 xlLETRaG+SSZgGvLaC9S5BGJ8X0B35c7yB4hjl/hLt17hZc3qnhzDDlMtM66laZQCVdlop Yitr4SC57O6LXd3S+QvPJs/bHVoyBMpRkSFNfGoetjE4x7aFZHqCgoWGiFGrk6xwwIFn3S Of1wVE5FDLnbDTMpqkkmGeLfWOuvvthwFbIlqFGXCe9DuUkJVhCr1MePR+03gwR/Hj33dp msvHvntjNC8uylYdS/znlD+ZGvIqkdpN8OvCqj605gvva1rNZrA+6Y44VdD3MQ== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 08/17] soc: fsl: cpm1: qmc: Rename qmc_setup_tsa* to qmc_init_tsa* Date: Tue, 28 Nov 2023 15:08:07 +0100 Message-ID: <20231128140818.261541-9-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" qmc_setup_tsa* are called once at initialisation. They initialize the QMC TSA table. In order to introduce setup function later on for dynamic timeslots management, rename the function to avoid later confusion. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 0413e25d4c67..e3f2afb8fa4d 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -919,7 +919,7 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct d= evice_node *np) return qmc_check_chans(qmc); } =20 -static int qmc_setup_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_i= nfo *info) +static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_in= fo *info) { struct qmc_chan *chan; unsigned int i; @@ -961,7 +961,7 @@ static int qmc_setup_tsa_64rxtx(struct qmc *qmc, const = struct tsa_serial_info *i return 0; } =20 -static int qmc_setup_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_seria= l_info *info) +static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial= _info *info) { struct qmc_chan *chan; unsigned int i; @@ -1019,7 +1019,7 @@ static int qmc_setup_tsa_32rx_32tx(struct qmc *qmc, c= onst struct tsa_serial_info return 0; } =20 -static int qmc_setup_tsa(struct qmc *qmc) +static int qmc_init_tsa(struct qmc *qmc) { struct tsa_serial_info info; int ret; @@ -1030,12 +1030,12 @@ static int qmc_setup_tsa(struct qmc *qmc) return ret; =20 /* - * Setup one common 64 entries table or two 32 entries (one for Tx and - * one for Tx) according to assigned TS numbers. + * Initialize one common 64 entries table or two 32 entries (one for Tx + * and one for Tx) according to assigned TS numbers. */ return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ? - qmc_setup_tsa_64rxtx(qmc, &info) : - qmc_setup_tsa_32rx_32tx(qmc, &info); + qmc_init_tsa_64rxtx(qmc, &info) : + qmc_init_tsa_32rx_32tx(qmc, &info); } =20 static int qmc_setup_chan_trnsync(struct qmc *qmc, struct qmc_chan *chan) @@ -1391,7 +1391,7 @@ static int qmc_probe(struct platform_device *pdev) qmc_write32(qmc->scc_pram + QMC_GBL_C_MASK32, 0xDEBB20E3); qmc_write16(qmc->scc_pram + QMC_GBL_C_MASK16, 0xF0B8); =20 - ret =3D qmc_setup_tsa(qmc); + ret =3D qmc_init_tsa(qmc); if (ret) goto err_tsa_serial_disconnect; =20 --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A57F9C4167B for ; Tue, 28 Nov 2023 14:09:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345604AbjK1OI4 (ORCPT ); Tue, 28 Nov 2023 09:08:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345987AbjK1OIe (ORCPT ); Tue, 28 Nov 2023 09:08:34 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D2C010F7 for ; Tue, 28 Nov 2023 06:08:32 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 119BF60010; Tue, 28 Nov 2023 14:08:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180511; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Zz1ZSWhesx2d8c0NZFELt4xynqYdE38OR15azgcLscQ=; b=CxCVUB/8kFinXWaDFzVyzOmSOhktqV1nsk8cs9JGZ5F0LPa+2icfWnnFD3GbAwzlZqMuih aAtB8O5ZMuR4Q9OLco5ALg4MaGG8/VWp+Jns0750e7s657DEWuNDtwtVw0hNXlcklyhn9m 8TVi3uoG69fPGyoNO+0JZcMaNmfVNSVl1L++3j12RY9JfpUFHexpE6jJNaxzaO9Hl6NdYy nJhWlUezo6mF2yDJir362r9HIsE/LDNVcuzNopMf/e6xzq8L/jIB0ukeBrtVuyIYL5qYE2 b7WCvD2UsxPh0Y0yj2jh5gqwdGMHPgV9Qf2+tUyWz19MY2Y6fhBieeE7fKAzWw== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 09/17] soc: fsl: cpm1: qmc: Introduce qmc_chan_setup_tsa* Date: Tue, 28 Nov 2023 15:08:08 +0100 Message-ID: <20231128140818.261541-10-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce the qmc_chan_setup_tsa* functions to setup entries related to the given channel. Use them during QMC channels setup. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 161 ++++++++++++++++++++++++++++++--------- 1 file changed, 125 insertions(+), 36 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index e3f2afb8fa4d..5d7e2ecdd933 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -240,6 +240,11 @@ static void qmc_clrbits16(void __iomem *addr, u16 clr) qmc_write16(addr, qmc_read16(addr) & ~clr); } =20 +static void qmc_clrsetbits16(void __iomem *addr, u16 clr, u16 set) +{ + qmc_write16(addr, (qmc_read16(addr) & ~clr) | set); +} + static void qmc_write32(void __iomem *addr, u32 val) { iowrite32be(val, addr); @@ -562,6 +567,122 @@ static void qmc_chan_read_done(struct qmc_chan *chan) spin_unlock_irqrestore(&chan->rx_lock, flags); } =20 +static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct t= sa_serial_info *info) +{ + unsigned int i; + u16 curr; + u16 val; + + /* + * Use a common Tx/Rx 64 entries table. + * Tx and Rx related stuffs must be identical + */ + if (chan->tx_ts_mask !=3D chan->rx_ts_mask) { + dev_err(chan->qmc->dev, "chan %u uses different Rx and Tx TS\n", chan->i= d); + return -EINVAL; + } + + val =3D QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); + + /* Check entries based on Rx stuff*/ + for (i =3D 0; i < info->nb_rx_ts; i++) { + if (!(chan->rx_ts_mask & (((u64)1) << i))) + continue; + + curr =3D qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2)); + if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) !=3D val) { + dev_err(chan->qmc->dev, "chan %u TxRx entry %d already used\n", + chan->id, i); + return -EBUSY; + } + } + + /* Set entries based on Rx stuff*/ + for (i =3D 0; i < info->nb_rx_ts; i++) { + if (!(chan->rx_ts_mask & (((u64)1) << i))) + continue; + + qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), + ~QMC_TSA_WRAP, val); + } + + return 0; +} + +static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struc= t tsa_serial_info *info) +{ + unsigned int i; + u16 curr; + u16 val; + + /* Use a Tx 32 entries table and a Rx 32 entries table */ + + val =3D QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); + + /* Check entries based on Rx stuff */ + for (i =3D 0; i < info->nb_rx_ts; i++) { + if (!(chan->rx_ts_mask & (((u64)1) << i))) + continue; + + curr =3D qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2)); + if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) !=3D val) { + dev_err(chan->qmc->dev, "chan %u Rx entry %d already used\n", + chan->id, i); + return -EBUSY; + } + } + /* Check entries based on Tx stuff */ + for (i =3D 0; i < info->nb_tx_ts; i++) { + if (!(chan->tx_ts_mask & (((u64)1) << i))) + continue; + + curr =3D qmc_read16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2)); + if (curr & QMC_TSA_VALID && (curr & ~QMC_TSA_WRAP) !=3D val) { + dev_err(chan->qmc->dev, "chan %u Tx entry %d already used\n", + chan->id, i); + return -EBUSY; + } + } + + /* Set entries based on Rx stuff */ + for (i =3D 0; i < info->nb_rx_ts; i++) { + if (!(chan->rx_ts_mask & (((u64)1) << i))) + continue; + + qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), + ~QMC_TSA_WRAP, val); + } + /* Set entries based on Tx stuff */ + for (i =3D 0; i < info->nb_tx_ts; i++) { + if (!(chan->tx_ts_mask & (((u64)1) << i))) + continue; + + qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), + ~QMC_TSA_WRAP, val); + } + + return 0; +} + +static int qmc_chan_setup_tsa(struct qmc_chan *chan) +{ + struct tsa_serial_info info; + int ret; + + /* Retrieve info from the TSA related serial */ + ret =3D tsa_serial_get_info(chan->qmc->tsa_serial, &info); + if (ret) + return ret; + + /* + * Setup one common 64 entries table or two 32 entries (one for Tx + * and one for Tx) according to assigned TS numbers. + */ + return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ? + qmc_chan_setup_tsa_64rxtx(chan, &info) : + qmc_chan_setup_tsa_32rx_32tx(chan, &info); +} + static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode) { return cpm_command(chan->id << 2, (qmc_opcode << 4) | 0x0E); @@ -921,7 +1042,6 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct = device_node *np) =20 static int qmc_init_tsa_64rxtx(struct qmc *qmc, const struct tsa_serial_in= fo *info) { - struct qmc_chan *chan; unsigned int i; u16 val; =20 @@ -935,18 +1055,6 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const= struct tsa_serial_info *in for (i =3D 0; i < 64; i++) qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), 0x0000); =20 - /* Set entries based on Rx stuff*/ - list_for_each_entry(chan, &qmc->chan_head, list) { - for (i =3D 0; i < info->nb_rx_ts; i++) { - if (!(chan->rx_ts_mask & (((u64)1) << i))) - continue; - - val =3D QMC_TSA_VALID | QMC_TSA_MASK | - QMC_TSA_CHANNEL(chan->id); - qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), val); - } - } - /* Set Wrap bit on last entry */ qmc_setbits16(qmc->scc_pram + QMC_GBL_TSATRX + ((info->nb_rx_ts - 1) * 2), QMC_TSA_WRAP); @@ -963,7 +1071,6 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const = struct tsa_serial_info *in =20 static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, const struct tsa_serial= _info *info) { - struct qmc_chan *chan; unsigned int i; u16 val; =20 @@ -978,28 +1085,6 @@ static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, co= nst struct tsa_serial_info qmc_write16(qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), 0x0000); } =20 - /* Set entries based on Rx and Tx stuff*/ - list_for_each_entry(chan, &qmc->chan_head, list) { - /* Rx part */ - for (i =3D 0; i < info->nb_rx_ts; i++) { - if (!(chan->rx_ts_mask & (((u64)1) << i))) - continue; - - val =3D QMC_TSA_VALID | QMC_TSA_MASK | - QMC_TSA_CHANNEL(chan->id); - qmc_write16(qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), val); - } - /* Tx part */ - for (i =3D 0; i < info->nb_tx_ts; i++) { - if (!(chan->tx_ts_mask & (((u64)1) << i))) - continue; - - val =3D QMC_TSA_VALID | QMC_TSA_MASK | - QMC_TSA_CHANNEL(chan->id); - qmc_write16(qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), val); - } - } - /* Set Wrap bit on last entries */ qmc_setbits16(qmc->scc_pram + QMC_GBL_TSATRX + ((info->nb_rx_ts - 1) * 2), QMC_TSA_WRAP); @@ -1081,6 +1166,10 @@ static int qmc_setup_chan(struct qmc *qmc, struct qm= c_chan *chan) =20 chan->qmc =3D qmc; =20 + ret =3D qmc_chan_setup_tsa(chan); + if (ret) + return ret; + /* Set channel specific parameter base address */ chan->s_param =3D qmc->dpram + (chan->id * 64); /* 16 bd per channel (8 rx and 8 tx) */ --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BB2EC4167B for ; Tue, 28 Nov 2023 14:09:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346141AbjK1OI7 (ORCPT ); Tue, 28 Nov 2023 09:08:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345643AbjK1OIf (ORCPT ); Tue, 28 Nov 2023 09:08:35 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A89A1702 for ; Tue, 28 Nov 2023 06:08:33 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id 055A560019; Tue, 28 Nov 2023 14:08:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180512; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3HnC31hSxmZV54Av1uYqv8xlMMFu4tlE/lTrC/V/gEc=; b=EKPaBoIRvTW/5ppCis1S+25udDqzlucm3iPrxYLH3oVp/ZWH4ca1SUk0NzCR+KYHATZTw3 KF/ydqf2BaL5GATgodrX/YXezDmX8iE/zDe9aNqLBrD2Mq8b3WHazSbOwwH1bFIw5K3lpW Cy6cFk52r8jpmndBjVocDFhfhsW7iGcLa67L7uxbvvg3u9lYCjyx2Cn8+vreWw0xEXzsxk prHTjedvyFouzAiNe1HAypMv1yNzWQuu99F+IbMENj6c3DrR+UnSivZYgAzNdNUwJmOUMf TpFfWVb/8g+N2fKZ0Q/G5VcHp/kBBtSEse1j4aybbY+Rb3yIuSW83UTfs4l8vQ== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 10/17] soc: fsl: cpm1: qmc: Remove no more needed checks from qmc_check_chans() Date: Tue, 28 Nov 2023 15:08:09 +0100 Message-ID: <20231128140818.261541-11-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The newly introduced qmc_chan_setup_tsa* functions check that the channel entries are not already used. These checks are also performed by qmc_check_chans() and are no more needed. Remove them from qmc_check_chans(). Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 5d7e2ecdd933..f2a71a140db7 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -884,10 +884,7 @@ EXPORT_SYMBOL(qmc_chan_reset); static int qmc_check_chans(struct qmc *qmc) { struct tsa_serial_info info; - bool is_one_table =3D false; struct qmc_chan *chan; - u64 tx_ts_mask =3D 0; - u64 rx_ts_mask =3D 0; u64 tx_ts_assigned_mask; u64 rx_ts_assigned_mask; int ret; @@ -911,7 +908,6 @@ static int qmc_check_chans(struct qmc *qmc) dev_err(qmc->dev, "Number of TSA Tx/Rx TS assigned are not equal\n"); return -EINVAL; } - is_one_table =3D true; } =20 tx_ts_assigned_mask =3D info.nb_tx_ts =3D=3D 64 ? U64_MAX : (((u64)1) << = info.nb_tx_ts) - 1; @@ -922,27 +918,11 @@ static int qmc_check_chans(struct qmc *qmc) dev_err(qmc->dev, "chan %u uses TSA unassigned Tx TS\n", chan->id); return -EINVAL; } - if (tx_ts_mask & chan->tx_ts_mask) { - dev_err(qmc->dev, "chan %u uses an already used Tx TS\n", chan->id); - return -EINVAL; - } =20 if (chan->rx_ts_mask > rx_ts_assigned_mask) { dev_err(qmc->dev, "chan %u uses TSA unassigned Rx TS\n", chan->id); return -EINVAL; } - if (rx_ts_mask & chan->rx_ts_mask) { - dev_err(qmc->dev, "chan %u uses an already used Rx TS\n", chan->id); - return -EINVAL; - } - - if (is_one_table && (chan->tx_ts_mask !=3D chan->rx_ts_mask)) { - dev_err(qmc->dev, "chan %u uses different Rx and Tx TS\n", chan->id); - return -EINVAL; - } - - tx_ts_mask |=3D chan->tx_ts_mask; - rx_ts_mask |=3D chan->rx_ts_mask; } =20 return 0; --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 751E8C4167B for ; Tue, 28 Nov 2023 14:09:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346251AbjK1OJB (ORCPT ); Tue, 28 Nov 2023 09:09:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346017AbjK1OIf (ORCPT ); Tue, 28 Nov 2023 09:08:35 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 368F91710 for ; Tue, 28 Nov 2023 06:08:35 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id EFBDE60004; Tue, 28 Nov 2023 14:08:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180513; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GVuTwhCVXrXaMm3ot/4hj4miUNcKZkq86yB6yXDjnng=; b=HKz663bgEeldH0FU4o0nXL2LMX4R7SR7bzpTq5c6vtJm+dl/suNEd6Q9bMNFyD28OZOccm eTsl2HYEBDxBUjhXxvKqotKhagx7OZGxHMZcsyOF9jJjFb5rdnWnefgMKoYN/CIqikpLWm +EZ5BnefMkg+HkYKly+LQk5fc8ZrPNZTfT8P2lbCYJYzKAzbpuZfmAN8g/QgLfoBxDa9Ho gH1xl3Zbnxu8obHdxl6IjGzy4R84lGvnPY/nPRKqdLM4J9F5WOyTC/HXXHY+W4vKIq1Ckd cwNmlCx8odxBdEYM6g50ldMrEDTJLBypoBMt5HtuFA5+z/8Kq8NE6WCoCVlyMA== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 11/17] soc: fsl: cpm1: qmc: Check available timeslots in qmc_check_chans() Date: Tue, 28 Nov 2023 15:08:10 +0100 Message-ID: <20231128140818.261541-12-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The timeslots checked in qmc_check_chans() are the timeslots used. With the introduction of the available timeslots, the used timeslots are a subset of the available timeslots. The timeslots checked during the qmc_check_chans() call should be the available ones. Simply update and check the available timeslots instead of the used timeslots in qmc_check_chans(). Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index f2a71a140db7..8d71e63d0f21 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -914,13 +914,13 @@ static int qmc_check_chans(struct qmc *qmc) rx_ts_assigned_mask =3D info.nb_rx_ts =3D=3D 64 ? U64_MAX : (((u64)1) << = info.nb_rx_ts) - 1; =20 list_for_each_entry(chan, &qmc->chan_head, list) { - if (chan->tx_ts_mask > tx_ts_assigned_mask) { - dev_err(qmc->dev, "chan %u uses TSA unassigned Tx TS\n", chan->id); + if (chan->tx_ts_mask_avail > tx_ts_assigned_mask) { + dev_err(qmc->dev, "chan %u can use TSA unassigned Tx TS\n", chan->id); return -EINVAL; } =20 - if (chan->rx_ts_mask > rx_ts_assigned_mask) { - dev_err(qmc->dev, "chan %u uses TSA unassigned Rx TS\n", chan->id); + if (chan->rx_ts_mask_avail > rx_ts_assigned_mask) { + dev_err(qmc->dev, "chan %u can use TSA unassigned Rx TS\n", chan->id); return -EINVAL; } } --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9D9DC4167B for ; Tue, 28 Nov 2023 14:09:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346286AbjK1OJN (ORCPT ); Tue, 28 Nov 2023 09:09:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346044AbjK1OIg (ORCPT ); Tue, 28 Nov 2023 09:08:36 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 206C51735 for ; Tue, 28 Nov 2023 06:08:35 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id F01FC60008; Tue, 28 Nov 2023 14:08:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180514; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JWHgBlygVL1LuwsPq3d724YHN4EBk4wsLUMnSb1bhgA=; b=F3uMowcK+/y8P7goYwCcRSJE2Sc3uNGVzLqcbAcWjXgDLr86uJ7HFkGvKkZItiIp+jqwwY GM6NOmmokiNm5Y+6LVfKwz8uBhFAqw4IpZaHWS5t7iAdlVJZRtKkffmm6AuSGfbaxgMR63 XaurN86rbLaP+DCfrXHrsalgYyWukCmmxDM8wVvpySWNtuTp6XsXgfLyYdy3Ntu7vej2wz SEX67rSuwYaul/MJK92eadRsEj5jimSKkytOXkpZva9bwMkn3oEpCmN6YH/nG7DdxPz8Ho L7q18qwcqY2cFjPSbGe4/YO9lpKMKt7vw1got0aBi1fg0JubocyuMR3rGJPolw== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 12/17] soc: fsl: cpm1: qmc: Add support for disabling channel TSA entries Date: Tue, 28 Nov 2023 15:08:11 +0100 Message-ID: <20231128140818.261541-13-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to allow runtime timeslot route changes, disabling channel TSA entries needs to be supported. Add support for this new feature. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 8d71e63d0f21..c1318fad296b 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -567,7 +567,8 @@ static void qmc_chan_read_done(struct qmc_chan *chan) spin_unlock_irqrestore(&chan->rx_lock, flags); } =20 -static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct t= sa_serial_info *info) +static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan *chan, const struct t= sa_serial_info *info, + bool enable) { unsigned int i; u16 curr; @@ -603,13 +604,14 @@ static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan = *chan, const struct tsa_ser continue; =20 qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), - ~QMC_TSA_WRAP, val); + ~QMC_TSA_WRAP, enable ? val : 0x0000); } =20 return 0; } =20 -static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struc= t tsa_serial_info *info) +static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struc= t tsa_serial_info *info, + bool enable) { unsigned int i; u16 curr; @@ -650,7 +652,7 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan= *chan, const struct tsa_ continue; =20 qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), - ~QMC_TSA_WRAP, val); + ~QMC_TSA_WRAP, enable ? val : 0x0000); } /* Set entries based on Tx stuff */ for (i =3D 0; i < info->nb_tx_ts; i++) { @@ -658,13 +660,13 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_ch= an *chan, const struct tsa_ continue; =20 qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATTX + (i * 2), - ~QMC_TSA_WRAP, val); + ~QMC_TSA_WRAP, enable ? val : 0x0000); } =20 return 0; } =20 -static int qmc_chan_setup_tsa(struct qmc_chan *chan) +static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable) { struct tsa_serial_info info; int ret; @@ -679,8 +681,8 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan) * and one for Tx) according to assigned TS numbers. */ return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ? - qmc_chan_setup_tsa_64rxtx(chan, &info) : - qmc_chan_setup_tsa_32rx_32tx(chan, &info); + qmc_chan_setup_tsa_64rxtx(chan, &info, enable) : + qmc_chan_setup_tsa_32rx_32tx(chan, &info, enable); } =20 static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode) @@ -1146,7 +1148,7 @@ static int qmc_setup_chan(struct qmc *qmc, struct qmc= _chan *chan) =20 chan->qmc =3D qmc; =20 - ret =3D qmc_chan_setup_tsa(chan); + ret =3D qmc_chan_setup_tsa(chan, true); if (ret) return ret; =20 --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B0C8C4167B for ; Tue, 28 Nov 2023 14:09:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346282AbjK1OJJ (ORCPT ); Tue, 28 Nov 2023 09:09:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345801AbjK1OIg (ORCPT ); Tue, 28 Nov 2023 09:08:36 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A9A71987 for ; Tue, 28 Nov 2023 06:08:36 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id E4C5A60006; Tue, 28 Nov 2023 14:08:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180515; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Dt8E2D4ZnskziNqA8VgLYvP0cEsUOjj8FKYX1alFvDY=; b=oBJ1HyQRXrLan+tGpeNHGICi4a7exxCy4rXkYTEsNTBCkmfjDg4BJS6WiYZAwEVcUBLbvw sV1DGVNyLlckoltG51O8qRm4RraB0W0vk2EL31rRKGsfI6CktEttrOgeR2+9F1L7Vmeu4E Go9RLNP0hlp3yp4JgDB7/qYWVib9ovSGCUUz0nnevBOKjwCFUxTB5PkfXKB40crGjTfmtP Oj9rQgDs+bXsclqeoty0rgKNyBBkE1PLg9Fva1j3JuNr2s9ACAr5AUIfLKXH06gkMO4mOy xyxYd43q/KBhBgi4l8s+sljl++GHcu25albRhMQOyQhwoTizrGDf5ZA+hNvfuA== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 13/17] soc: fsl: cpm1: qmc: Split Tx and Rx TSA entries setup Date: Tue, 28 Nov 2023 15:08:12 +0100 Message-ID: <20231128140818.261541-14-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The Tx and Rx entries for a given channel are set in one function. In order to modify Rx entries and Tx entries independently of one other, split this function in one for the Rx part and one for the Tx part. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 49 ++++++++++++++++++++++++++++------------ 1 file changed, 35 insertions(+), 14 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index c1318fad296b..5ca4120779f8 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -610,14 +610,14 @@ static int qmc_chan_setup_tsa_64rxtx(struct qmc_chan = *chan, const struct tsa_ser return 0; } =20 -static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_chan *chan, const struc= t tsa_serial_info *info, - bool enable) +static int qmc_chan_setup_tsa_32rx(struct qmc_chan *chan, const struct tsa= _serial_info *info, + bool enable) { unsigned int i; u16 curr; u16 val; =20 - /* Use a Tx 32 entries table and a Rx 32 entries table */ + /* Use a Rx 32 entries table */ =20 val =3D QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); =20 @@ -633,6 +633,30 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_cha= n *chan, const struct tsa_ return -EBUSY; } } + + /* Set entries based on Rx stuff */ + for (i =3D 0; i < info->nb_rx_ts; i++) { + if (!(chan->rx_ts_mask & (((u64)1) << i))) + continue; + + qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), + ~QMC_TSA_WRAP, enable ? val : 0x0000); + } + + return 0; +} + +static int qmc_chan_setup_tsa_32tx(struct qmc_chan *chan, const struct tsa= _serial_info *info, + bool enable) +{ + unsigned int i; + u16 curr; + u16 val; + + /* Use a Tx 32 entries table */ + + val =3D QMC_TSA_VALID | QMC_TSA_MASK | QMC_TSA_CHANNEL(chan->id); + /* Check entries based on Tx stuff */ for (i =3D 0; i < info->nb_tx_ts; i++) { if (!(chan->tx_ts_mask & (((u64)1) << i))) @@ -646,14 +670,6 @@ static int qmc_chan_setup_tsa_32rx_32tx(struct qmc_cha= n *chan, const struct tsa_ } } =20 - /* Set entries based on Rx stuff */ - for (i =3D 0; i < info->nb_rx_ts; i++) { - if (!(chan->rx_ts_mask & (((u64)1) << i))) - continue; - - qmc_clrsetbits16(chan->qmc->scc_pram + QMC_GBL_TSATRX + (i * 2), - ~QMC_TSA_WRAP, enable ? val : 0x0000); - } /* Set entries based on Tx stuff */ for (i =3D 0; i < info->nb_tx_ts; i++) { if (!(chan->tx_ts_mask & (((u64)1) << i))) @@ -680,9 +696,14 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, b= ool enable) * Setup one common 64 entries table or two 32 entries (one for Tx * and one for Tx) according to assigned TS numbers. */ - return ((info.nb_tx_ts > 32) || (info.nb_rx_ts > 32)) ? - qmc_chan_setup_tsa_64rxtx(chan, &info, enable) : - qmc_chan_setup_tsa_32rx_32tx(chan, &info, enable); + if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32) + return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); + + ret =3D qmc_chan_setup_tsa_32rx(chan, &info, enable); + if (ret) + return ret; + + return qmc_chan_setup_tsa_32tx(chan, &info, enable); } =20 static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode) --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DF42C4167B for ; Tue, 28 Nov 2023 14:09:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346168AbjK1OJE (ORCPT ); Tue, 28 Nov 2023 09:09:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346064AbjK1OIg (ORCPT ); Tue, 28 Nov 2023 09:08:36 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2652619A3 for ; Tue, 28 Nov 2023 06:08:37 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id E531060005; Tue, 28 Nov 2023 14:08:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180516; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xHk9CdyIDprG+6Gwz4WRxtkc6hwo9HZn9NzP3/YrC7w=; b=Desx5TSsmTS0/uzGXiO4Lq4aFbdVWG8lmbAaJFFFRhvlRy1o2l+lhBElBTKkjBGOfMnqIE uSpc3zCiWMxyWDER3hRO2XYyHLp5pnytJH1HIJz04GYla3n0CmIZ501+Y/ASQ2UJleAkkJ r58O62KxHlo4gFC3JOSNEuaZzMj/udWounvjEO0T9UV8LTgaMBYLX6NBsT9JMlKCRHLUIy c3wygvYCjTeLlHou2sJ+0gyDWPksKZy4XMAC4q+OmDfLsLCPG941Wrc4Xxj1XTQZ6IH7zB CzJLNqj+or7iNXvEY8anY6SbtslaasEn6tlUPbvCbNqJRNi5xtsp/BK8aDHLoQ== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 14/17] soc: fsl: cpm1: qmc: Introduce is_tsa_64rxtx flag Date: Tue, 28 Nov 2023 15:08:13 +0100 Message-ID: <20231128140818.261541-15-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to support runtime timeslot route changes, some operations will be different according the routing table used (common Rx and Tx table or one table for Rx and one for Tx). The is_tsa_64rxtx flag is introduced to avoid extra computation to determine the table format each time we need it. It is set once at initialization. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 5ca4120779f8..e651b3bba1ca 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -216,6 +216,7 @@ struct qmc { u16 __iomem *int_curr; dma_addr_t int_dma_addr; size_t int_size; + bool is_tsa_64rxtx; struct list_head chan_head; struct qmc_chan *chans[64]; }; @@ -696,7 +697,7 @@ static int qmc_chan_setup_tsa(struct qmc_chan *chan, bo= ol enable) * Setup one common 64 entries table or two 32 entries (one for Tx * and one for Tx) according to assigned TS numbers. */ - if (info.nb_tx_ts > 32 || info.nb_rx_ts > 32) + if (chan->qmc->is_tsa_64rxtx) return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); =20 ret =3D qmc_chan_setup_tsa_32rx(chan, &info, enable); @@ -1053,6 +1054,7 @@ static int qmc_init_tsa_64rxtx(struct qmc *qmc, const= struct tsa_serial_info *in * Everything was previously checked, Tx and Rx related stuffs are * identical -> Used Rx related stuff to build the table */ + qmc->is_tsa_64rxtx =3D true; =20 /* Invalidate all entries */ for (i =3D 0; i < 64; i++) @@ -1081,6 +1083,7 @@ static int qmc_init_tsa_32rx_32tx(struct qmc *qmc, co= nst struct tsa_serial_info * Use a Tx 32 entries table and a Rx 32 entries table. * Everything was previously checked. */ + qmc->is_tsa_64rxtx =3D false; =20 /* Invalidate all entries */ for (i =3D 0; i < 32; i++) { --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9A69C07CA9 for ; Tue, 28 Nov 2023 14:09:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346139AbjK1OJG (ORCPT ); Tue, 28 Nov 2023 09:09:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346090AbjK1OIg (ORCPT ); Tue, 28 Nov 2023 09:08:36 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DABB19AA for ; Tue, 28 Nov 2023 06:08:38 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id E5FA160012; Tue, 28 Nov 2023 14:08:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180517; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=C0KV5VSap2HeJW6mH5ydEZnvSodIWVNbkUiCcgxqwGg=; b=iP4PyNaMFAzPpWrUyhyN1eAf+GpeCRmRivAivlyfFLvIw1wU6IQW91PMSIE0zqRi2KNez4 +QRv3C8vDOi2amOgEM31Pdtn7Zo2y8tTpKLyfKlznaHRIzldp/zfpgumH3HUab5p1EWcD/ HuF4oKqZ85D2fCKwo+Kafk2ifYuPrJKJv2+m1C7gqQds1Q1GBNzdGdTGelRt2GN9GLP+Vj O9qdoDY/hTZqUkycvpE17IL7V9hRKY1wkDUPVxRwio2B4tAKZEjwBjX30xvGSiXPIuxFnP PxcGj6ac2REM+XQB6jb3kSy693SA0Gj297g1ZdSvYW72k791DkpjjxCZuZk2NA== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 15/17] soc: fsl: cpm1: qmc: Handle timeslot entries at channel start() and stop() Date: Tue, 28 Nov 2023 15:08:14 +0100 Message-ID: <20231128140818.261541-16-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to support runtime timeslot route changes, enable the channel timeslot entries at channel start() and disable them at channel stop(). Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 175 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 163 insertions(+), 12 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index e651b3bba1ca..e56aea5803bf 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -177,6 +177,7 @@ struct qmc_chan { struct qmc *qmc; void __iomem *s_param; enum qmc_mode mode; + spinlock_t ts_lock; /* Protect timeslots */ u64 tx_ts_mask_avail; u64 tx_ts_mask; u64 rx_ts_mask_avail; @@ -265,6 +266,7 @@ static void qmc_setbits32(void __iomem *addr, u32 set) int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info) { struct tsa_serial_info tsa_info; + unsigned long flags; int ret; =20 /* Retrieve info from the TSA related serial */ @@ -272,6 +274,8 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct qmc= _chan_info *info) if (ret) return ret; =20 + spin_lock_irqsave(&chan->ts_lock, flags); + info->mode =3D chan->mode; info->rx_fs_rate =3D tsa_info.rx_fs_rate; info->rx_bit_rate =3D tsa_info.rx_bit_rate; @@ -280,6 +284,8 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct qmc= _chan_info *info) info->tx_bit_rate =3D tsa_info.tx_bit_rate; info->nb_rx_ts =3D hweight64(chan->rx_ts_mask); =20 + spin_unlock_irqrestore(&chan->ts_lock, flags); + return 0; } EXPORT_SYMBOL(qmc_chan_get_info); @@ -683,6 +689,40 @@ static int qmc_chan_setup_tsa_32tx(struct qmc_chan *ch= an, const struct tsa_seria return 0; } =20 +static int qmc_chan_setup_tsa_tx(struct qmc_chan *chan, bool enable) +{ + struct tsa_serial_info info; + int ret; + + /* Retrieve info from the TSA related serial */ + ret =3D tsa_serial_get_info(chan->qmc->tsa_serial, &info); + if (ret) + return ret; + + /* Setup entries */ + if (chan->qmc->is_tsa_64rxtx) + return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); + + return qmc_chan_setup_tsa_32tx(chan, &info, enable); +} + +static int qmc_chan_setup_tsa_rx(struct qmc_chan *chan, bool enable) +{ + struct tsa_serial_info info; + int ret; + + /* Retrieve info from the TSA related serial */ + ret =3D tsa_serial_get_info(chan->qmc->tsa_serial, &info); + if (ret) + return ret; + + /* Setup entries */ + if (chan->qmc->is_tsa_64rxtx) + return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); + + return qmc_chan_setup_tsa_32rx(chan, &info, enable); +} + static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable) { struct tsa_serial_info info; @@ -719,6 +759,12 @@ static int qmc_chan_stop_rx(struct qmc_chan *chan) =20 spin_lock_irqsave(&chan->rx_lock, flags); =20 + if (chan->is_rx_stopped) { + /* The channel is already stopped -> simply return ok */ + ret =3D 0; + goto end; + } + /* Send STOP RECEIVE command */ ret =3D qmc_chan_command(chan, 0x0); if (ret) { @@ -729,6 +775,15 @@ static int qmc_chan_stop_rx(struct qmc_chan *chan) =20 chan->is_rx_stopped =3D true; =20 + if (!chan->qmc->is_tsa_64rxtx || chan->is_tx_stopped) { + ret =3D qmc_chan_setup_tsa_rx(chan, false); + if (ret) { + dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n", + chan->id, ret); + goto end; + } + } + end: spin_unlock_irqrestore(&chan->rx_lock, flags); return ret; @@ -741,6 +796,12 @@ static int qmc_chan_stop_tx(struct qmc_chan *chan) =20 spin_lock_irqsave(&chan->tx_lock, flags); =20 + if (chan->is_tx_stopped) { + /* The channel is already stopped -> simply return ok */ + ret =3D 0; + goto end; + } + /* Send STOP TRANSMIT command */ ret =3D qmc_chan_command(chan, 0x1); if (ret) { @@ -751,37 +812,82 @@ static int qmc_chan_stop_tx(struct qmc_chan *chan) =20 chan->is_tx_stopped =3D true; =20 + if (!chan->qmc->is_tsa_64rxtx || chan->is_rx_stopped) { + ret =3D qmc_chan_setup_tsa_tx(chan, false); + if (ret) { + dev_err(chan->qmc->dev, "chan %u: Disable tsa entries failed (%d)\n", + chan->id, ret); + goto end; + } + } + end: spin_unlock_irqrestore(&chan->tx_lock, flags); return ret; } =20 +static int qmc_chan_start_rx(struct qmc_chan *chan); + int qmc_chan_stop(struct qmc_chan *chan, int direction) { - int ret; + bool is_rx_rollback_needed =3D false; + unsigned long flags; + int ret =3D 0; + + spin_lock_irqsave(&chan->ts_lock, flags); =20 if (direction & QMC_CHAN_READ) { + is_rx_rollback_needed =3D !chan->is_rx_stopped; ret =3D qmc_chan_stop_rx(chan); if (ret) - return ret; + goto end; } =20 if (direction & QMC_CHAN_WRITE) { ret =3D qmc_chan_stop_tx(chan); - if (ret) - return ret; + if (ret) { + /* Restart rx if needed */ + if (is_rx_rollback_needed) + qmc_chan_start_rx(chan); + goto end; + } } =20 - return 0; +end: + spin_unlock_irqrestore(&chan->ts_lock, flags); + return ret; } EXPORT_SYMBOL(qmc_chan_stop); =20 -static void qmc_chan_start_rx(struct qmc_chan *chan) +static int qmc_setup_chan_trnsync(struct qmc *qmc, struct qmc_chan *chan); + +static int qmc_chan_start_rx(struct qmc_chan *chan) { unsigned long flags; + int ret; =20 spin_lock_irqsave(&chan->rx_lock, flags); =20 + if (!chan->is_rx_stopped) { + /* The channel is already started -> simply return ok */ + ret =3D 0; + goto end; + } + + ret =3D qmc_chan_setup_tsa_rx(chan, true); + if (ret) { + dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n", + chan->id, ret); + goto end; + } + + ret =3D qmc_setup_chan_trnsync(chan->qmc, chan); + if (ret) { + dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n", + chan->id, ret); + goto end; + } + /* Restart the receiver */ if (chan->mode =3D=3D QMC_TRANSPARENT) qmc_write32(chan->s_param + QMC_SPE_ZDSTATE, 0x18000080); @@ -792,15 +898,38 @@ static void qmc_chan_start_rx(struct qmc_chan *chan) =20 chan->is_rx_stopped =3D false; =20 +end: spin_unlock_irqrestore(&chan->rx_lock, flags); + return ret; } =20 -static void qmc_chan_start_tx(struct qmc_chan *chan) +static int qmc_chan_start_tx(struct qmc_chan *chan) { unsigned long flags; + int ret; =20 spin_lock_irqsave(&chan->tx_lock, flags); =20 + if (!chan->is_tx_stopped) { + /* The channel is already started -> simply return ok */ + ret =3D 0; + goto end; + } + + ret =3D qmc_chan_setup_tsa_tx(chan, true); + if (ret) { + dev_err(chan->qmc->dev, "chan %u: Enable tsa entries failed (%d)\n", + chan->id, ret); + goto end; + } + + ret =3D qmc_setup_chan_trnsync(chan->qmc, chan); + if (ret) { + dev_err(chan->qmc->dev, "chan %u: setup TRNSYNC failed (%d)\n", + chan->id, ret); + goto end; + } + /* * Enable channel transmitter as it could be disabled if * qmc_chan_reset() was called. @@ -812,18 +941,39 @@ static void qmc_chan_start_tx(struct qmc_chan *chan) =20 chan->is_tx_stopped =3D false; =20 +end: spin_unlock_irqrestore(&chan->tx_lock, flags); + return ret; } =20 int qmc_chan_start(struct qmc_chan *chan, int direction) { - if (direction & QMC_CHAN_READ) - qmc_chan_start_rx(chan); + bool is_rx_rollback_needed =3D false; + unsigned long flags; + int ret =3D 0; =20 - if (direction & QMC_CHAN_WRITE) - qmc_chan_start_tx(chan); + spin_lock_irqsave(&chan->ts_lock, flags); =20 - return 0; + if (direction & QMC_CHAN_READ) { + is_rx_rollback_needed =3D chan->is_rx_stopped; + ret =3D qmc_chan_start_rx(chan); + if (ret) + goto end; + } + + if (direction & QMC_CHAN_WRITE) { + ret =3D qmc_chan_start_tx(chan); + if (ret) { + /* Restop rx if needed */ + if (is_rx_rollback_needed) + qmc_chan_stop_rx(chan); + goto end; + } + } + +end: + spin_unlock_irqrestore(&chan->ts_lock, flags); + return ret; } EXPORT_SYMBOL(qmc_chan_start); =20 @@ -992,6 +1142,7 @@ static int qmc_of_parse_chans(struct qmc *qmc, struct = device_node *np) } =20 chan->id =3D chan_id; + spin_lock_init(&chan->ts_lock); spin_lock_init(&chan->rx_lock); spin_lock_init(&chan->tx_lock); =20 --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5DDCC07CA9 for ; Tue, 28 Nov 2023 14:09:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346295AbjK1OJS (ORCPT ); Tue, 28 Nov 2023 09:09:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346104AbjK1OIh (ORCPT ); Tue, 28 Nov 2023 09:08:37 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::223]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1075F19AE for ; Tue, 28 Nov 2023 06:08:39 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id E545060019; Tue, 28 Nov 2023 14:08:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180518; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Bma3mZKmxIFArO90vzJrs+KgkGYG3Bl8WMHHLKhSC0s=; b=otLRTa+7QSuZQkh1nILWZqkKn5Mgn30FbLC5bNoYef0r029RpN6mFtOI+0TfCsCMf1uPx6 Z0dF+l0iFhyuKmY/L7Jb2L/DHCYvueoOUGIcUhJJc59IBR4bsvSVbvX1lgyD9LeuVOnRFI Z5VOPIGaTU3T6ipg2n4zRVGFZaVfoH38QpMXhOB3z3zRpkYWuqsRxiod2nwknV0vacwuEO KsIXaVjf6CcuZTBI+UJkHPB+3yZU2wj/cFv4z0F0egsu4NYiPUGtgUXuohNdf7bRBSPUXK 7VZA+4KP0CXWNnFbcFcoqfCj04fWhZTw6zsMXbmC0KEe93W16IKJfGqm9eWABA== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 16/17] soc: fsl: cpm1: qmc: Remove timeslots handling from setup_chan() Date: Tue, 28 Nov 2023 15:08:15 +0100 Message-ID: <20231128140818.261541-17-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Timeslots setting is done at channel start() and stop(). There is no more need to do that during setup_chan(). Simply remove timeslot setting from setup_chan(). Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 28 ---------------------------- 1 file changed, 28 deletions(-) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index e56aea5803bf..73903ce31695 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -723,30 +723,6 @@ static int qmc_chan_setup_tsa_rx(struct qmc_chan *chan= , bool enable) return qmc_chan_setup_tsa_32rx(chan, &info, enable); } =20 -static int qmc_chan_setup_tsa(struct qmc_chan *chan, bool enable) -{ - struct tsa_serial_info info; - int ret; - - /* Retrieve info from the TSA related serial */ - ret =3D tsa_serial_get_info(chan->qmc->tsa_serial, &info); - if (ret) - return ret; - - /* - * Setup one common 64 entries table or two 32 entries (one for Tx - * and one for Tx) according to assigned TS numbers. - */ - if (chan->qmc->is_tsa_64rxtx) - return qmc_chan_setup_tsa_64rxtx(chan, &info, enable); - - ret =3D qmc_chan_setup_tsa_32rx(chan, &info, enable); - if (ret) - return ret; - - return qmc_chan_setup_tsa_32tx(chan, &info, enable); -} - static int qmc_chan_command(struct qmc_chan *chan, u8 qmc_opcode) { return cpm_command(chan->id << 2, (qmc_opcode << 4) | 0x0E); @@ -1323,10 +1299,6 @@ static int qmc_setup_chan(struct qmc *qmc, struct qm= c_chan *chan) =20 chan->qmc =3D qmc; =20 - ret =3D qmc_chan_setup_tsa(chan, true); - if (ret) - return ret; - /* Set channel specific parameter base address */ chan->s_param =3D qmc->dpram + (chan->id * 64); /* 16 bd per channel (8 rx and 8 tx) */ --=20 2.42.0 From nobody Thu Dec 18 23:00:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46B75C10DC3 for ; Tue, 28 Nov 2023 14:09:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345651AbjK1OJU (ORCPT ); Tue, 28 Nov 2023 09:09:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1346133AbjK1OIi (ORCPT ); Tue, 28 Nov 2023 09:08:38 -0500 Received: from relay3-d.mail.gandi.net (relay3-d.mail.gandi.net [217.70.183.195]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E24C519B3 for ; Tue, 28 Nov 2023 06:08:40 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPA id D33656000B; Tue, 28 Nov 2023 14:08:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1701180519; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qB5PQIsjg4vNdEztMunF8K802tA8yt3Tver1m2WVF68=; b=ed6RUCNm7a7brdsSg9wc5Qc1Y1ptEjdyXGcpjOjS8tt9TPY7J1Zm00ocuG+1r+Aj5mjkLn 8k01XwTM9iM8kgXPBgG1oz/1iVQ95LdYUxkaogcDe9qI5yKtssOfA9kKjrqAZAb4O7wQUD d1/mkVaUE0N5ZxrRG6OVDlgG2LwKZzKGA2y4pRXUNSq8llJqTSES3uPQkp433T9LVyWsjc Mze/Z6YlVrBgq4G8ipe32F4IIGbwoh4ZVRJRRr9/HS9N/iaJHiTxmiZ7X41sKgOJIlTxoe ZclZCzDritqoGY6QeqQcz/8FN3HJ1XBCIVJJBopoz1wMS7igDPecTgua1Bdg5A== From: Herve Codina To: Herve Codina , Qiang Zhao , Li Yang , Jakub Kicinski , Shengjiu Wang , Xiubo Li , Fabio Estevam , Nicolin Chen , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Christophe Leroy Cc: Arnd Bergmann , linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org, Thomas Petazzoni Subject: [PATCH 17/17] soc: fsl: cpm1: qmc: Introduce functions to change timeslots at runtime Date: Tue, 28 Nov 2023 15:08:16 +0100 Message-ID: <20231128140818.261541-18-herve.codina@bootlin.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231128140818.261541-1-herve.codina@bootlin.com> References: <20231128140818.261541-1-herve.codina@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-GND-Sasl: herve.codina@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Introduce qmc_chan_{get,set}_ts_info() function to allow timeslots modification at runtime. The modification is provided using qmc_chan_set_ts_info() and will be applied on next qmc_chan_start(). qmc_chan_set_ts_info() must be called with the channel rx and/or tx stopped. Signed-off-by: Herve Codina Reviewed-by: Christophe Leroy --- drivers/soc/fsl/qe/qmc.c | 51 ++++++++++++++++++++++++++++++++++++++++ include/soc/fsl/qe/qmc.h | 10 ++++++++ 2 files changed, 61 insertions(+) diff --git a/drivers/soc/fsl/qe/qmc.c b/drivers/soc/fsl/qe/qmc.c index 73903ce31695..79fe79b9464f 100644 --- a/drivers/soc/fsl/qe/qmc.c +++ b/drivers/soc/fsl/qe/qmc.c @@ -290,6 +290,57 @@ int qmc_chan_get_info(struct qmc_chan *chan, struct qm= c_chan_info *info) } EXPORT_SYMBOL(qmc_chan_get_info); =20 +int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *t= s_info) +{ + unsigned long flags; + + spin_lock_irqsave(&chan->ts_lock, flags); + + ts_info->rx_ts_mask_avail =3D chan->rx_ts_mask_avail; + ts_info->tx_ts_mask_avail =3D chan->tx_ts_mask_avail; + ts_info->rx_ts_mask =3D chan->rx_ts_mask; + ts_info->tx_ts_mask =3D chan->tx_ts_mask; + + spin_unlock_irqrestore(&chan->ts_lock, flags); + + return 0; +} +EXPORT_SYMBOL(qmc_chan_get_ts_info); + +int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_i= nfo *ts_info) +{ + unsigned long flags; + int ret; + + /* Only a subset of available timeslots is allowed */ + if ((ts_info->rx_ts_mask & chan->rx_ts_mask_avail) !=3D ts_info->rx_ts_ma= sk) + return -EINVAL; + if ((ts_info->tx_ts_mask & chan->tx_ts_mask_avail) !=3D ts_info->tx_ts_ma= sk) + return -EINVAL; + + /* In case of common rx/tx table, rx/tx masks must be identical */ + if (chan->qmc->is_tsa_64rxtx) { + if (ts_info->rx_ts_mask !=3D ts_info->tx_ts_mask) + return -EINVAL; + } + + spin_lock_irqsave(&chan->ts_lock, flags); + + if ((chan->tx_ts_mask !=3D ts_info->tx_ts_mask && !chan->is_tx_stopped) || + (chan->rx_ts_mask !=3D ts_info->rx_ts_mask && !chan->is_rx_stopped)) { + dev_err(chan->qmc->dev, "Channel rx and/or tx not stopped\n"); + ret =3D -EBUSY; + } else { + chan->tx_ts_mask =3D ts_info->tx_ts_mask; + chan->rx_ts_mask =3D ts_info->rx_ts_mask; + ret =3D 0; + } + spin_unlock_irqrestore(&chan->ts_lock, flags); + + return ret; +} +EXPORT_SYMBOL(qmc_chan_set_ts_info); + int qmc_chan_set_param(struct qmc_chan *chan, const struct qmc_chan_param = *param) { if (param->mode !=3D chan->mode) diff --git a/include/soc/fsl/qe/qmc.h b/include/soc/fsl/qe/qmc.h index 166484bb4294..2a333fc1ea81 100644 --- a/include/soc/fsl/qe/qmc.h +++ b/include/soc/fsl/qe/qmc.h @@ -40,6 +40,16 @@ struct qmc_chan_info { =20 int qmc_chan_get_info(struct qmc_chan *chan, struct qmc_chan_info *info); =20 +struct qmc_chan_ts_info { + u64 rx_ts_mask_avail; + u64 tx_ts_mask_avail; + u64 rx_ts_mask; + u64 tx_ts_mask; +}; + +int qmc_chan_get_ts_info(struct qmc_chan *chan, struct qmc_chan_ts_info *t= s_info); +int qmc_chan_set_ts_info(struct qmc_chan *chan, const struct qmc_chan_ts_i= nfo *ts_info); + struct qmc_chan_param { enum qmc_mode mode; union { --=20 2.42.0