From nobody Wed Dec 17 12:46:50 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4696C4167B for ; Tue, 28 Nov 2023 05:53:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343622AbjK1FxV (ORCPT ); Tue, 28 Nov 2023 00:53:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50372 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343625AbjK1FxI (ORCPT ); Tue, 28 Nov 2023 00:53:08 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F06B11A5; Mon, 27 Nov 2023 21:53:13 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5r87f077368; Mon, 27 Nov 2023 23:53:08 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701150788; bh=EvhllPdn0T4Rb3F6rMCJ5f3ZnzgT/73fDxcOUSorAkQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CdoLI2PW3WvNI94gytwki9IMrOY94O/0iAyPDG6rAiSOt7BYt/IibwDe8eBcrcs5p Af3FVKKkr6pj+5k5eg7R2aZHYHywU1OqxqgXrEqvKUBMcudE7gr+Kk8BK4fe0XyOQa Xybqb/LLgzM4ee+4CINinheEwEaWWMecPt85NwPY= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AS5r8rK026718 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Nov 2023 23:53:08 -0600 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 23:53:08 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 23:53:08 -0600 Received: from a0497641-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5qUuK104118; Mon, 27 Nov 2023 23:53:03 -0600 From: Neha Malcom Francis To: , , , , , , CC: , , , , , , , , , , , , Subject: [PATCH v8 6/7] arm64: dts: ti: k3-j721e-sk: Add TPS6594 family PMICs Date: Tue, 28 Nov 2023 11:22:29 +0530 Message-ID: <20231128055230.342547-7-n-francis@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128055230.342547-1-n-francis@ti.com> References: <20231128055230.342547-1-n-francis@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds support for TPS6594 PMIC family on wakeup I2C0 bus. These devices provide regulators (bucks and LDOs), but also GPIOs, a RTC, a watchdog, an ESM (Error Signal Monitor) which monitors the SoC error output signal, and a PFSM (Pre-configurable Finite State Machine) which manages the operational modes of the PMIC. Signed-off-by: Neha Malcom Francis --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 154 +++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/t= i/k3-j721e-sk.dts index 42fe8eee9ec8..3e801b4cdb1e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -459,6 +459,12 @@ J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.G= PIO1_12 */ }; =20 &wkup_pmx0 { + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + J721E_WKUP_IOPAD(0x0cc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-default-pins { pinctrl-single,pins =3D < J721E_WKUP_IOPAD(0x84, PIN_INPUT, 0) /* (B24) MCU_RGMII1_RD0 */ @@ -560,6 +566,154 @@ eeprom@51 { compatible =3D "atmel,24c512"; reg =3D <0x51>; }; + + tps659413: pmic@48 { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x48>; + system-power-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <9 IRQ_TYPE_EDGE_FALLING>; + ti,primary-pmic; + + gpio-controller; + #gpio-cells =3D <2>; + + buck123-supply =3D <&vsys_3v3>; + buck4-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + bucka123: buck123 { + regulator-name =3D "vdd_cpu_avs"; + regulator-min-microvolt =3D <600000>; + regulator-max-microvolt =3D <900000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka4: buck4 { + regulator-name =3D "vdd_mcu_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + bucka5: buck5 { + regulator-name =3D "vdd_phyio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa1: ldo1 { + regulator-name =3D "vdd1_lpddr4_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa2: ldo2 { + regulator-name =3D "vdd_mcuio_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa3: ldo3 { + regulator-name =3D "vdda_dll_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldoa4: ldo4 { + regulator-name =3D "vda_mcu_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659411: pmic@4c { + compatible =3D "ti,tps6594-q1"; + reg =3D <0x4c>; + system-power-controller; + interrupt-parent =3D <&wkup_gpio0>; + interrupts =3D <9 IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells =3D <2>; + + buck1234-supply =3D <&vsys_3v3>; + buck5-supply =3D <&vsys_3v3>; + ldo1-supply =3D <&vsys_3v3>; + ldo2-supply =3D <&vsys_3v3>; + ldo3-supply =3D <&vsys_3v3>; + ldo4-supply =3D <&vsys_3v3>; + + regulators { + buckb1234: buck1234 { + regulator-name =3D "vdd_core_0v8"; + regulator-min-microvolt =3D <800000>; + regulator-max-microvolt =3D <800000>; + regulator-boot-on; + regulator-always-on; + }; + + buckb5: buck5 { + regulator-name =3D "vdd_ram_0v85"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob1: ldo1 { + regulator-name =3D "vdd_sd_dv"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob2: ldo2 { + regulator-name =3D "vdd_usb_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob3: ldo3 { + regulator-name =3D "vdd_io_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldob4: ldo4 { + regulator-name =3D "vda_pll_1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; }; =20 &mcu_uart0 { --=20 2.34.1