From nobody Sun Sep 14 14:31:04 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9936C4167B for ; Tue, 28 Nov 2023 05:44:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234636AbjK1Fon (ORCPT ); Tue, 28 Nov 2023 00:44:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343573AbjK1Foa (ORCPT ); Tue, 28 Nov 2023 00:44:30 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E3FDDE; Mon, 27 Nov 2023 21:44:36 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5iQRj072810; Mon, 27 Nov 2023 23:44:26 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701150266; bh=fbkuiSgCNDpWbASQgL29p346CS4aTmJI9c50yuRTTd0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=SlHCrixe3nDdr/NeJITbDr8cdf794zOgh81Yi4P3W5UK0uNzLEhMagQwzwoRMKQqU GW2XO461+rS5yIHUy0aTAM7ST+k1JVrYlmMsiP28hvNc8e/6Mj9L/HOsxkORoVPrrW +10nmhSTJF98Jcnhp2IJFg4lN4t19SN4X2fhpV9g= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AS5iQci017538 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Nov 2023 23:44:26 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 23:44:26 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 23:44:26 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5i2uS096776; Mon, 27 Nov 2023 23:44:22 -0600 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v13 4/5] PCI: j721e: Add PCIe 4x lane selection support Date: Tue, 28 Nov 2023 11:14:01 +0530 Message-ID: <20231128054402.2155183-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128054402.2155183-1-s-vadapalli@ti.com> References: <20231128054402.2155183-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra Reviewed-by: Roger Quadros Signed-off-by: Achal Verma Signed-off-by: Siddharth Vadapalli --- drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index 63c758b14314..645597856a1d 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -42,7 +42,6 @@ enum link_status { }; =20 #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) =20 #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -52,6 +51,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + u32 max_lanes; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pci= e *pcie, { struct device *dev =3D pcie->cdns_pcie->dev; u32 lanes =3D pcie->num_lanes; + u32 mask =3D BIT(8); u32 val =3D 0; int ret; =20 + if (pcie->max_lanes =3D=3D 4) + mask =3D GENMASK(9, 8); + val =3D LANE_COUNT(lanes - 1); - ret =3D regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret =3D regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n"); =20 @@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pde= v) dev_warn(dev, "num-lanes property not provided or invalid, setting num-l= anes to 1\n"); num_lanes =3D 1; } + pcie->num_lanes =3D num_lanes; + pcie->max_lanes =3D data->max_lanes; =20 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) return -EINVAL; --=20 2.34.1