From nobody Sun Sep 14 12:36:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3BD35C4167B for ; Tue, 28 Nov 2023 05:44:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343575AbjK1Foa (ORCPT ); Tue, 28 Nov 2023 00:44:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233002AbjK1FoY (ORCPT ); Tue, 28 Nov 2023 00:44:24 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 611BAD6; Mon, 27 Nov 2023 21:44:31 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5iCtI072775; Mon, 27 Nov 2023 23:44:12 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701150252; bh=0m2Zfqeb+FQunMXPM7eB5iriJ4FlPLIrtvm2HPPZ7tc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Xq8z0LiAaN9jCKOaxykMQADY52tyI5253/RsVRrZUgoYBUqfUZKDh5zZ6WOw/3/yN ILEk3XVe/DbPOY+YUaKU5Favc+Zi4WGozwMgSNlhg8jAX2WntFmpCC3nEFDXJ/poNH CxTJwjpmb/r3SmJCvKXf4j/tP+sKQ+mjc5zvdUw8= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AS5iCx1021460 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Nov 2023 23:44:12 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 23:44:12 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 23:44:12 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5i2uP096776; Mon, 27 Nov 2023 23:44:08 -0600 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v13 1/5] dt-bindings: PCI: ti,j721e-pci-*: add checks for num-lanes Date: Tue, 28 Nov 2023 11:13:58 +0530 Message-ID: <20231128054402.2155183-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128054402.2155183-1-s-vadapalli@ti.com> References: <20231128054402.2155183-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Add num-lanes schema checks based on compatible string on available lanes for that platform. Signed-off-by: Matt Ranostay Signed-off-by: Achal Verma Reviewed-by: Krzysztof Kozlowski Signed-off-by: Siddharth Vadapalli --- .../bindings/pci/ti,j721e-pci-ep.yaml | 27 ++++++++++++++++--- .../bindings/pci/ti,j721e-pci-host.yaml | 27 ++++++++++++++++--- 2 files changed, 48 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/D= ocumentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 62292185fe2e..162e5c2906e1 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -10,9 +10,6 @@ title: TI J721E PCI EP (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I =20 -allOf: - - $ref: cdns-pcie-ep.yaml# - properties: compatible: oneOf: @@ -65,6 +62,30 @@ properties: items: - const: link_state =20 +allOf: + - $ref: cdns-pcie-ep.yaml# + - if: + properties: + compatible: + enum: + - ti,am64-pcie-ep + then: + properties: + num-lanes: + const: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-ep + - ti,j721e-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b= /Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index a2c5eaea57f5..854dc9e08dcf 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -10,9 +10,6 @@ title: TI J721E PCI Host (PCIe Wrapper) maintainers: - Kishon Vijay Abraham I =20 -allOf: - - $ref: cdns-pcie-host.yaml# - properties: compatible: oneOf: @@ -94,6 +91,30 @@ properties: interrupts: maxItems: 1 =20 +allOf: + - $ref: cdns-pcie-host.yaml# + - if: + properties: + compatible: + enum: + - ti,am64-pcie-host + then: + properties: + num-lanes: + const: 1 + + - if: + properties: + compatible: + enum: + - ti,j7200-pcie-host + - ti,j721e-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 2 + required: - compatible - reg --=20 2.34.1 From nobody Sun Sep 14 12:36:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E21FEC4167B for ; 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Mon, 27 Nov 2023 23:44:17 -0600 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 23:44:16 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 23:44:17 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5i2uQ096776; Mon, 27 Nov 2023 23:44:12 -0600 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v13 2/5] dt-bindings: PCI: ti,j721e-pci-*: add j784s4-pci-* compatible strings Date: Tue, 28 Nov 2023 11:13:59 +0530 Message-ID: <20231128054402.2155183-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128054402.2155183-1-s-vadapalli@ti.com> References: <20231128054402.2155183-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Add definition for j784s4-pci-ep + j784s4-pci-host devices along with schema checks for num-lanes. Signed-off-by: Matt Ranostay Acked-by: Krzysztof Kozlowski Signed-off-by: Achal Verma Signed-off-by: Siddharth Vadapalli --- .../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 12 ++++++++++++ .../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 12 ++++++++++++ 2 files changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml b/D= ocumentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml index 162e5c2906e1..97f2579ea908 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml @@ -14,6 +14,7 @@ properties: compatible: oneOf: - const: ti,j721e-pcie-ep + - const: ti,j784s4-pcie-ep - description: PCIe EP controller in AM64 items: - const: ti,am64-pcie-ep @@ -86,6 +87,17 @@ allOf: minimum: 1 maximum: 2 =20 + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-ep + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b= /Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 854dc9e08dcf..b7a534cef24d 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -14,6 +14,7 @@ properties: compatible: oneOf: - const: ti,j721e-pcie-host + - const: ti,j784s4-pcie-host - description: PCIe controller in AM64 items: - const: ti,am64-pcie-host @@ -115,6 +116,17 @@ allOf: minimum: 1 maximum: 2 =20 + - if: + properties: + compatible: + enum: + - ti,j784s4-pcie-host + then: + properties: + num-lanes: + minimum: 1 + maximum: 4 + required: - compatible - reg --=20 2.34.1 From nobody Sun Sep 14 12:36:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3326CC4167B for ; Tue, 28 Nov 2023 05:44:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343582AbjK1Foi (ORCPT ); Tue, 28 Nov 2023 00:44:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343568AbjK1Fo1 (ORCPT ); Tue, 28 Nov 2023 00:44:27 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9523D0; Mon, 27 Nov 2023 21:44:33 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5iM0B042816; Mon, 27 Nov 2023 23:44:22 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701150262; bh=vdRFuuK893UD4rU+C8SivGsR6/Yo5lUUWHFtiT9ZlRY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VXXsY5l7bntvU6h03PTtqCc7ZYKWnrn7dTGT4XmqXAX9H1kGyqCOfFCnWwKqp7aoj Bf+tpqRb0Hf9GKm2ktpv68vuNXk+vIHw8im2KLHAETqsCPzpL8astQ3B+54DuWW7Hl zhXGF7Vp2DdoTqG900d9UG/A2OyDTKRpHwun5PZA= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AS5iL4U001211 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Nov 2023 23:44:22 -0600 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 23:44:21 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 23:44:21 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5i2uR096776; Mon, 27 Nov 2023 23:44:17 -0600 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v13 3/5] PCI: j721e: Add per platform maximum lane settings Date: Tue, 28 Nov 2023 11:14:00 +0530 Message-ID: <20231128054402.2155183-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128054402.2155183-1-s-vadapalli@ti.com> References: <20231128054402.2155183-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Various platforms have different maximum amount of lanes that can be selected. Add max_lanes to struct j721e_pcie to allow for detection of this which is needed to calculate the needed bitmask size for the possible lane count. Signed-off-by: Matt Ranostay Signed-off-by: Achal Verma Signed-off-by: Siddharth Vadapalli Reviewed-by: Ravi Gunasekaran --- drivers/pci/controller/cadence/pci-j721e.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index 2c87e7728a65..63c758b14314 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -47,8 +47,6 @@ enum link_status { =20 #define GENERATION_SEL_MASK GENMASK(1, 0) =20 -#define MAX_LANES 2 - struct j721e_pcie { struct cdns_pcie *cdns_pcie; struct clk *refclk; @@ -71,6 +69,7 @@ struct j721e_pcie_data { unsigned int quirk_disable_flr:1; u32 linkdown_irq_regfield; unsigned int byte_access_allowed:1; + unsigned int max_lanes; }; =20 static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offse= t) @@ -290,11 +289,13 @@ static const struct j721e_pcie_data j721e_pcie_rc_dat= a =3D { .quirk_retrain_flag =3D true, .byte_access_allowed =3D false, .linkdown_irq_regfield =3D LINK_DOWN, + .max_lanes =3D 2, }; =20 static const struct j721e_pcie_data j721e_pcie_ep_data =3D { .mode =3D PCI_MODE_EP, .linkdown_irq_regfield =3D LINK_DOWN, + .max_lanes =3D 2, }; =20 static const struct j721e_pcie_data j7200_pcie_rc_data =3D { @@ -302,23 +303,27 @@ static const struct j721e_pcie_data j7200_pcie_rc_dat= a =3D { .quirk_detect_quiet_flag =3D true, .linkdown_irq_regfield =3D J7200_LINK_DOWN, .byte_access_allowed =3D true, + .max_lanes =3D 2, }; =20 static const struct j721e_pcie_data j7200_pcie_ep_data =3D { .mode =3D PCI_MODE_EP, .quirk_detect_quiet_flag =3D true, .quirk_disable_flr =3D true, + .max_lanes =3D 2, }; =20 static const struct j721e_pcie_data am64_pcie_rc_data =3D { .mode =3D PCI_MODE_RC, .linkdown_irq_regfield =3D J7200_LINK_DOWN, .byte_access_allowed =3D true, + .max_lanes =3D 1, }; =20 static const struct j721e_pcie_data am64_pcie_ep_data =3D { .mode =3D PCI_MODE_EP, .linkdown_irq_regfield =3D J7200_LINK_DOWN, + .max_lanes =3D 1, }; =20 static const struct of_device_id of_j721e_pcie_match[] =3D { @@ -432,8 +437,10 @@ static int j721e_pcie_probe(struct platform_device *pd= ev) pcie->user_cfg_base =3D base; =20 ret =3D of_property_read_u32(node, "num-lanes", &num_lanes); - if (ret || num_lanes > MAX_LANES) + if (ret || num_lanes > data->max_lanes) { + dev_warn(dev, "num-lanes property not provided or invalid, setting num-l= anes to 1\n"); num_lanes =3D 1; + } pcie->num_lanes =3D num_lanes; =20 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) --=20 2.34.1 From nobody Sun Sep 14 12:36:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9936C4167B for ; Tue, 28 Nov 2023 05:44:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234636AbjK1Fon (ORCPT ); Tue, 28 Nov 2023 00:44:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343573AbjK1Foa (ORCPT ); Tue, 28 Nov 2023 00:44:30 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E3FDDE; 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Mon, 27 Nov 2023 23:44:26 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 23:44:26 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5i2uS096776; Mon, 27 Nov 2023 23:44:22 -0600 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v13 4/5] PCI: j721e: Add PCIe 4x lane selection support Date: Tue, 28 Nov 2023 11:14:01 +0530 Message-ID: <20231128054402.2155183-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128054402.2155183-1-s-vadapalli@ti.com> References: <20231128054402.2155183-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Add support for setting of two-bit field that allows selection of 4x lane PCIe which was previously limited to only 2x lanes. Signed-off-by: Matt Ranostay Reviewed-by: Vignesh Raghavendra Reviewed-by: Roger Quadros Signed-off-by: Achal Verma Signed-off-by: Siddharth Vadapalli --- drivers/pci/controller/cadence/pci-j721e.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index 63c758b14314..645597856a1d 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -42,7 +42,6 @@ enum link_status { }; =20 #define J721E_MODE_RC BIT(7) -#define LANE_COUNT_MASK BIT(8) #define LANE_COUNT(n) ((n) << 8) =20 #define GENERATION_SEL_MASK GENMASK(1, 0) @@ -52,6 +51,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + u32 max_lanes; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -205,11 +205,15 @@ static int j721e_pcie_set_lane_count(struct j721e_pci= e *pcie, { struct device *dev =3D pcie->cdns_pcie->dev; u32 lanes =3D pcie->num_lanes; + u32 mask =3D BIT(8); u32 val =3D 0; int ret; =20 + if (pcie->max_lanes =3D=3D 4) + mask =3D GENMASK(9, 8); + val =3D LANE_COUNT(lanes - 1); - ret =3D regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val); + ret =3D regmap_update_bits(syscon, offset, mask, val); if (ret) dev_err(dev, "failed to set link count\n"); =20 @@ -441,7 +445,9 @@ static int j721e_pcie_probe(struct platform_device *pde= v) dev_warn(dev, "num-lanes property not provided or invalid, setting num-l= anes to 1\n"); num_lanes =3D 1; } + pcie->num_lanes =3D num_lanes; + pcie->max_lanes =3D data->max_lanes; =20 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48))) return -EINVAL; --=20 2.34.1 From nobody Sun Sep 14 12:36:54 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64120C4167B for ; Tue, 28 Nov 2023 05:45:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343637AbjK1Fox (ORCPT ); Tue, 28 Nov 2023 00:44:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34350 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343578AbjK1Fog (ORCPT ); Tue, 28 Nov 2023 00:44:36 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0746D6D; Mon, 27 Nov 2023 21:44:40 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5iV6R072818; Mon, 27 Nov 2023 23:44:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701150271; bh=C7nLneLG/Oh9BPvoztNlayKtN+X4/S2BfHVVmetyqmQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=b/bS/4SMVXWeTaBX54ZcF9ROImJ0vhwI9JTbQ8xm7xwkXS4oEOILfk1VqezSiLijf /oaKowtLIVuYskkdNbKt0AHeZHVFAIp027M3zRNEnohSoFg/mqCVGs4eT87fkBO28D Rf9dy7X++7ZHn9Q+xNd9fxBqQnOD1xGokOP1IF1Q= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AS5iVpZ055937 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 27 Nov 2023 23:44:31 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 27 Nov 2023 23:44:30 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 27 Nov 2023 23:44:30 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AS5i2uT096776; Mon, 27 Nov 2023 23:44:26 -0600 From: Siddharth Vadapalli To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v13 5/5] PCI: j721e: add j784s4 PCIe configuration Date: Tue, 28 Nov 2023 11:14:02 +0530 Message-ID: <20231128054402.2155183-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231128054402.2155183-1-s-vadapalli@ti.com> References: <20231128054402.2155183-1-s-vadapalli@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Matt Ranostay Add PCIe configuration for j784s4 platform which has 4x lane support. Tested-by: Achal Verma Signed-off-by: Matt Ranostay Reviewed-by: Roger Quadros Signed-off-by: Achal Verma Signed-off-by: Siddharth Vadapalli --- drivers/pci/controller/cadence/pci-j721e.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/contr= oller/cadence/pci-j721e.c index 645597856a1d..85718246016b 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -330,6 +330,20 @@ static const struct j721e_pcie_data am64_pcie_ep_data = =3D { .max_lanes =3D 1, }; =20 +static const struct j721e_pcie_data j784s4_pcie_rc_data =3D { + .mode =3D PCI_MODE_RC, + .quirk_retrain_flag =3D true, + .byte_access_allowed =3D false, + .linkdown_irq_regfield =3D LINK_DOWN, + .max_lanes =3D 4, +}; + +static const struct j721e_pcie_data j784s4_pcie_ep_data =3D { + .mode =3D PCI_MODE_EP, + .linkdown_irq_regfield =3D LINK_DOWN, + .max_lanes =3D 4, +}; + static const struct of_device_id of_j721e_pcie_match[] =3D { { .compatible =3D "ti,j721e-pcie-host", @@ -355,6 +369,14 @@ static const struct of_device_id of_j721e_pcie_match[]= =3D { .compatible =3D "ti,am64-pcie-ep", .data =3D &am64_pcie_ep_data, }, + { + .compatible =3D "ti,j784s4-pcie-host", + .data =3D &j784s4_pcie_rc_data, + }, + { + .compatible =3D "ti,j784s4-pcie-ep", + .data =3D &j784s4_pcie_ep_data, + }, {}, }; =20 --=20 2.34.1