From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D011BC4167B for ; Mon, 27 Nov 2023 12:45:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233397AbjK0Mpu (ORCPT ); Mon, 27 Nov 2023 07:45:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233405AbjK0Mpn (ORCPT ); Mon, 27 Nov 2023 07:45:43 -0500 Received: from mail-qv1-xf33.google.com (mail-qv1-xf33.google.com [IPv6:2607:f8b0:4864:20::f33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 585FF10F for ; Mon, 27 Nov 2023 04:45:49 -0800 (PST) Received: by mail-qv1-xf33.google.com with SMTP id 6a1803df08f44-677f832d844so21992876d6.2 for ; Mon, 27 Nov 2023 04:45:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089148; x=1701693948; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=no0VTw7AaZRHaEYiXHFJsL4mdLmGMlJqeRVIKxNTTiA=; b=tI7iWclB75NeVByt/ZumuGf8SutG07BYCTzXF84OO+tks/LGUIgFZUChblMVyoUwh5 Z9y8r2Zk6Fgb0YKn6LueXNK0DBxILp18b9M6vRShEYEUNHGezHkJO7HYWLRt4SobBF6q 29II976loJCqCIOJ8y/PdnB7IpFHLjAhZZyxnNOTFJbZgsy2uej4zJGnxm+HLOKRS1XA R3qTVLixahPR2oyw6CR3zTslzeQoouf5yh3jFb+pJTw1vUtF+asaMmN1vmsWsJ0RgURe QyQJ5RY6aNjl1GCxw3BPtiK/+mhFq6xwjBiovWn6Hbz0Izkm/Gv5CdkdIgO8ucuYic/d Gafg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089148; x=1701693948; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=no0VTw7AaZRHaEYiXHFJsL4mdLmGMlJqeRVIKxNTTiA=; b=qTwg01iorlDAbSNjaNsbCqHrA/Lkwdh0HwZ/pW2jDCn71X+XpXeBT83Aovhf9ktDRk iT3/8x2mxZ8xC9vdWM2T2Kpixlh5cQ5lMkyNdg7GCH2D9r1/8vOS3bhC60CZhDNeL+vL uPUxDVg9qBzp5oNlCju0RYR4uP6ar88yUGGj5qTDTl3DxvhP4jwY2/oc04ZoCMJjj8dY hDy5K7R0qCSaXk4JAeGHF/ujVkQy6dNwCK/lnZspjdLzxrLHmBNU7uYF8ZzsRJ9btA0J xtBPfY7Q87ZRvkbGVgpbMGSINtmZuCrIdzwz/Blp40FsPj9EqrJovEOld6gH8fkK1hKr 5lyw== X-Gm-Message-State: AOJu0YymcojlMs8taMei2x+RBWkbROwDKKVBF0XUZM9xZWcjFXE3/lrt 7A7u+hjbZw1fkFoNP0RMaVDS X-Google-Smtp-Source: AGHT+IEDsR6fqa+PkwYSpn0j413uev3E0r+IobYut8mCcD//Br+4lRGXm5ATAklV35mB//KZGADMyw== X-Received: by 2002:a0c:e887:0:b0:67a:2ae3:a971 with SMTP id b7-20020a0ce887000000b0067a2ae3a971mr6857772qvo.2.1701089148388; Mon, 27 Nov 2023 04:45:48 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:45:47 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 1/9] bus: mhi: ep: Pass mhi_ep_buf_info struct to read/write APIs Date: Mon, 27 Nov 2023 18:15:21 +0530 Message-Id: <20231127124529.78203-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the preparation of DMA async support, let's pass the parameters to read_from_host() and write_to_host() APIs using mhi_ep_buf_info structure. No functional change. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas --- drivers/bus/mhi/ep/main.c | 23 +++---- drivers/bus/mhi/ep/ring.c | 41 ++++++------ drivers/pci/endpoint/functions/pci-epf-mhi.c | 66 +++++++++++--------- include/linux/mhi_ep.h | 16 ++++- 4 files changed, 84 insertions(+), 62 deletions(-) diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 4c8773881e1f..cdf5a84d1f21 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -344,10 +344,9 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *mh= i_cntrl, struct mhi_ep_chan *mhi_chan =3D &mhi_cntrl->mhi_chan[ring->ch_id]; struct device *dev =3D &mhi_cntrl->mhi_dev->dev; size_t tr_len, read_offset, write_offset; + struct mhi_ep_buf_info buf_info =3D {}; struct mhi_ring_element *el; bool tr_done =3D false; - void *write_addr; - u64 read_addr; u32 buf_left; int ret; =20 @@ -376,11 +375,13 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *m= hi_cntrl, =20 read_offset =3D mhi_chan->tre_size - mhi_chan->tre_bytes_left; write_offset =3D len - buf_left; - read_addr =3D mhi_chan->tre_loc + read_offset; - write_addr =3D result->buf_addr + write_offset; + + buf_info.host_addr =3D mhi_chan->tre_loc + read_offset; + buf_info.dev_addr =3D result->buf_addr + write_offset; + buf_info.size =3D tr_len; =20 dev_dbg(dev, "Reading %zd bytes from channel (%u)\n", tr_len, ring->ch_i= d); - ret =3D mhi_cntrl->read_from_host(mhi_cntrl, read_addr, write_addr, tr_l= en); + ret =3D mhi_cntrl->read_from_host(mhi_cntrl, &buf_info); if (ret < 0) { dev_err(&mhi_chan->mhi_dev->dev, "Error reading from channel\n"); return ret; @@ -503,12 +504,11 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, s= truct sk_buff *skb) struct mhi_ep_cntrl *mhi_cntrl =3D mhi_dev->mhi_cntrl; struct mhi_ep_chan *mhi_chan =3D mhi_dev->dl_chan; struct device *dev =3D &mhi_chan->mhi_dev->dev; + struct mhi_ep_buf_info buf_info =3D {}; struct mhi_ring_element *el; u32 buf_left, read_offset; struct mhi_ep_ring *ring; enum mhi_ev_ccs code; - void *read_addr; - u64 write_addr; size_t tr_len; u32 tre_len; int ret; @@ -537,11 +537,13 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, s= truct sk_buff *skb) =20 tr_len =3D min(buf_left, tre_len); read_offset =3D skb->len - buf_left; - read_addr =3D skb->data + read_offset; - write_addr =3D MHI_TRE_DATA_GET_PTR(el); + + buf_info.dev_addr =3D skb->data + read_offset; + buf_info.host_addr =3D MHI_TRE_DATA_GET_PTR(el); + buf_info.size =3D tr_len; =20 dev_dbg(dev, "Writing %zd bytes to channel (%u)\n", tr_len, ring->ch_id); - ret =3D mhi_cntrl->write_to_host(mhi_cntrl, read_addr, write_addr, tr_le= n); + ret =3D mhi_cntrl->write_to_host(mhi_cntrl, &buf_info); if (ret < 0) { dev_err(dev, "Error writing to the channel\n"); goto err_exit; @@ -1449,7 +1451,6 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *m= hi_cntrl, ret =3D -ENOMEM; goto err_destroy_tre_buf_cache; } - INIT_WORK(&mhi_cntrl->state_work, mhi_ep_state_worker); INIT_WORK(&mhi_cntrl->reset_work, mhi_ep_reset_worker); INIT_WORK(&mhi_cntrl->cmd_ring_work, mhi_ep_cmd_ring_worker); diff --git a/drivers/bus/mhi/ep/ring.c b/drivers/bus/mhi/ep/ring.c index a1071c13761b..7ea952860def 100644 --- a/drivers/bus/mhi/ep/ring.c +++ b/drivers/bus/mhi/ep/ring.c @@ -30,7 +30,8 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, = size_t end) { struct mhi_ep_cntrl *mhi_cntrl =3D ring->mhi_cntrl; struct device *dev =3D &mhi_cntrl->mhi_dev->dev; - size_t start, copy_size; + struct mhi_ep_buf_info buf_info =3D {}; + size_t start; int ret; =20 /* Don't proceed in the case of event ring. This happens during mhi_ep_ri= ng_start(). */ @@ -43,30 +44,34 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring= , size_t end) =20 start =3D ring->wr_offset; if (start < end) { - copy_size =3D (end - start) * sizeof(struct mhi_ring_element); - ret =3D mhi_cntrl->read_from_host(mhi_cntrl, ring->rbase + - (start * sizeof(struct mhi_ring_element)), - &ring->ring_cache[start], copy_size); + buf_info.size =3D (end - start) * sizeof(struct mhi_ring_element); + buf_info.host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_ele= ment)); + buf_info.dev_addr =3D &ring->ring_cache[start]; + + ret =3D mhi_cntrl->read_from_host(mhi_cntrl, &buf_info); if (ret < 0) return ret; } else { - copy_size =3D (ring->ring_size - start) * sizeof(struct mhi_ring_element= ); - ret =3D mhi_cntrl->read_from_host(mhi_cntrl, ring->rbase + - (start * sizeof(struct mhi_ring_element)), - &ring->ring_cache[start], copy_size); + buf_info.size =3D (ring->ring_size - start) * sizeof(struct mhi_ring_ele= ment); + buf_info.host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_ele= ment)); + buf_info.dev_addr =3D &ring->ring_cache[start]; + + ret =3D mhi_cntrl->read_from_host(mhi_cntrl, &buf_info); if (ret < 0) return ret; =20 if (end) { - ret =3D mhi_cntrl->read_from_host(mhi_cntrl, ring->rbase, - &ring->ring_cache[0], - end * sizeof(struct mhi_ring_element)); + buf_info.host_addr =3D ring->rbase; + buf_info.dev_addr =3D &ring->ring_cache[0]; + buf_info.size =3D end * sizeof(struct mhi_ring_element); + + ret =3D mhi_cntrl->read_from_host(mhi_cntrl, &buf_info); if (ret < 0) return ret; } } =20 - dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, cop= y_size); + dev_dbg(dev, "Cached ring: start %zu end %zu size %zu\n", start, end, buf= _info.size); =20 return 0; } @@ -102,6 +107,7 @@ int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, s= truct mhi_ring_element *e { struct mhi_ep_cntrl *mhi_cntrl =3D ring->mhi_cntrl; struct device *dev =3D &mhi_cntrl->mhi_dev->dev; + struct mhi_ep_buf_info buf_info =3D {}; size_t old_offset =3D 0; u32 num_free_elem; __le64 rp; @@ -133,12 +139,11 @@ int mhi_ep_ring_add_element(struct mhi_ep_ring *ring,= struct mhi_ring_element *e rp =3D cpu_to_le64(ring->rd_offset * sizeof(*el) + ring->rbase); memcpy_toio((void __iomem *) &ring->ring_ctx->generic.rp, &rp, sizeof(u64= )); =20 - ret =3D mhi_cntrl->write_to_host(mhi_cntrl, el, ring->rbase + (old_offset= * sizeof(*el)), - sizeof(*el)); - if (ret < 0) - return ret; + buf_info.host_addr =3D ring->rbase + (old_offset * sizeof(*el)); + buf_info.dev_addr =3D el; + buf_info.size =3D sizeof(*el); =20 - return 0; + return mhi_cntrl->write_to_host(mhi_cntrl, &buf_info); } =20 void mhi_ep_ring_init(struct mhi_ep_ring *ring, enum mhi_ep_ring_type type= , u32 id) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index daa09289eede..6dc918a8a023 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -209,28 +209,28 @@ static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl= *mhi_cntrl, u32 vector) vector + 1); } =20 -static int pci_epf_mhi_iatu_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from, - void *to, size_t size) +static int pci_epf_mhi_iatu_read(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info) { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); - size_t offset =3D get_align_offset(epf_mhi, from); + size_t offset =3D get_align_offset(epf_mhi, buf_info->host_addr); void __iomem *tre_buf; phys_addr_t tre_phys; int ret; =20 mutex_lock(&epf_mhi->lock); =20 - ret =3D __pci_epf_mhi_alloc_map(mhi_cntrl, from, &tre_phys, &tre_buf, - offset, size); + ret =3D __pci_epf_mhi_alloc_map(mhi_cntrl, buf_info->host_addr, &tre_phys, + &tre_buf, offset, buf_info->size); if (ret) { mutex_unlock(&epf_mhi->lock); return ret; } =20 - memcpy_fromio(to, tre_buf, size); + memcpy_fromio(buf_info->dev_addr, tre_buf, buf_info->size); =20 - __pci_epf_mhi_unmap_free(mhi_cntrl, from, tre_phys, tre_buf, offset, - size); + __pci_epf_mhi_unmap_free(mhi_cntrl, buf_info->host_addr, tre_phys, + tre_buf, offset, buf_info->size); =20 mutex_unlock(&epf_mhi->lock); =20 @@ -238,27 +238,27 @@ static int pci_epf_mhi_iatu_read(struct mhi_ep_cntrl = *mhi_cntrl, u64 from, } =20 static int pci_epf_mhi_iatu_write(struct mhi_ep_cntrl *mhi_cntrl, - void *from, u64 to, size_t size) + struct mhi_ep_buf_info *buf_info) { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); - size_t offset =3D get_align_offset(epf_mhi, to); + size_t offset =3D get_align_offset(epf_mhi, buf_info->host_addr); void __iomem *tre_buf; phys_addr_t tre_phys; int ret; =20 mutex_lock(&epf_mhi->lock); =20 - ret =3D __pci_epf_mhi_alloc_map(mhi_cntrl, to, &tre_phys, &tre_buf, - offset, size); + ret =3D __pci_epf_mhi_alloc_map(mhi_cntrl, buf_info->host_addr, &tre_phys, + &tre_buf, offset, buf_info->size); if (ret) { mutex_unlock(&epf_mhi->lock); return ret; } =20 - memcpy_toio(tre_buf, from, size); + memcpy_toio(tre_buf, buf_info->dev_addr, buf_info->size); =20 - __pci_epf_mhi_unmap_free(mhi_cntrl, to, tre_phys, tre_buf, offset, - size); + __pci_epf_mhi_unmap_free(mhi_cntrl, buf_info->host_addr, tre_phys, + tre_buf, offset, buf_info->size); =20 mutex_unlock(&epf_mhi->lock); =20 @@ -270,8 +270,8 @@ static void pci_epf_mhi_dma_callback(void *param) complete(param); } =20 -static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from, - void *to, size_t size) +static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info) { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; @@ -284,13 +284,13 @@ static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl = *mhi_cntrl, u64 from, dma_addr_t dst_addr; int ret; =20 - if (size < SZ_4K) - return pci_epf_mhi_iatu_read(mhi_cntrl, from, to, size); + if (buf_info->size < SZ_4K) + return pci_epf_mhi_iatu_read(mhi_cntrl, buf_info); =20 mutex_lock(&epf_mhi->lock); =20 config.direction =3D DMA_DEV_TO_MEM; - config.src_addr =3D from; + config.src_addr =3D buf_info->host_addr; =20 ret =3D dmaengine_slave_config(chan, &config); if (ret) { @@ -298,14 +298,16 @@ static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl = *mhi_cntrl, u64 from, goto err_unlock; } =20 - dst_addr =3D dma_map_single(dma_dev, to, size, DMA_FROM_DEVICE); + dst_addr =3D dma_map_single(dma_dev, buf_info->dev_addr, buf_info->size, + DMA_FROM_DEVICE); ret =3D dma_mapping_error(dma_dev, dst_addr); if (ret) { dev_err(dev, "Failed to map remote memory\n"); goto err_unlock; } =20 - desc =3D dmaengine_prep_slave_single(chan, dst_addr, size, DMA_DEV_TO_MEM, + desc =3D dmaengine_prep_slave_single(chan, dst_addr, buf_info->size, + DMA_DEV_TO_MEM, DMA_CTRL_ACK | DMA_PREP_INTERRUPT); if (!desc) { dev_err(dev, "Failed to prepare DMA\n"); @@ -332,15 +334,15 @@ static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl = *mhi_cntrl, u64 from, } =20 err_unmap: - dma_unmap_single(dma_dev, dst_addr, size, DMA_FROM_DEVICE); + dma_unmap_single(dma_dev, dst_addr, buf_info->size, DMA_FROM_DEVICE); err_unlock: mutex_unlock(&epf_mhi->lock); =20 return ret; } =20 -static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *mhi_cntrl, void *fr= om, - u64 to, size_t size) +static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info) { struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; @@ -353,13 +355,13 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl= *mhi_cntrl, void *from, dma_addr_t src_addr; int ret; =20 - if (size < SZ_4K) - return pci_epf_mhi_iatu_write(mhi_cntrl, from, to, size); + if (buf_info->size < SZ_4K) + return pci_epf_mhi_iatu_write(mhi_cntrl, buf_info); =20 mutex_lock(&epf_mhi->lock); =20 config.direction =3D DMA_MEM_TO_DEV; - config.dst_addr =3D to; + config.dst_addr =3D buf_info->host_addr; =20 ret =3D dmaengine_slave_config(chan, &config); if (ret) { @@ -367,14 +369,16 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl= *mhi_cntrl, void *from, goto err_unlock; } =20 - src_addr =3D dma_map_single(dma_dev, from, size, DMA_TO_DEVICE); + src_addr =3D dma_map_single(dma_dev, buf_info->dev_addr, buf_info->size, + DMA_TO_DEVICE); ret =3D dma_mapping_error(dma_dev, src_addr); if (ret) { dev_err(dev, "Failed to map remote memory\n"); goto err_unlock; } =20 - desc =3D dmaengine_prep_slave_single(chan, src_addr, size, DMA_MEM_TO_DEV, + desc =3D dmaengine_prep_slave_single(chan, src_addr, buf_info->size, + DMA_MEM_TO_DEV, DMA_CTRL_ACK | DMA_PREP_INTERRUPT); if (!desc) { dev_err(dev, "Failed to prepare DMA\n"); @@ -401,7 +405,7 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *= mhi_cntrl, void *from, } =20 err_unmap: - dma_unmap_single(dma_dev, src_addr, size, DMA_TO_DEVICE); + dma_unmap_single(dma_dev, src_addr, buf_info->size, DMA_TO_DEVICE); err_unlock: mutex_unlock(&epf_mhi->lock); =20 diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index ce85d42b685d..96f3a133540d 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -49,6 +49,18 @@ struct mhi_ep_db_info { u32 status; }; =20 +/** + * struct mhi_ep_buf_info - MHI Endpoint transfer buffer info + * @dev_addr: Address of the buffer in endpoint + * @host_addr: Address of the bufffer in host + * @size: Size of the buffer + */ +struct mhi_ep_buf_info { + void *dev_addr; + u64 host_addr; + size_t size; +}; + /** * struct mhi_ep_cntrl - MHI Endpoint controller structure * @cntrl_dev: Pointer to the struct device of physical bus acting as the = MHI @@ -137,8 +149,8 @@ struct mhi_ep_cntrl { void __iomem **virt, size_t size); void (*unmap_free)(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, phys_add= r_t phys, void __iomem *virt, size_t size); - int (*read_from_host)(struct mhi_ep_cntrl *mhi_cntrl, u64 from, void *to,= size_t size); - int (*write_to_host)(struct mhi_ep_cntrl *mhi_cntrl, void *from, u64 to, = size_t size); + int (*read_from_host)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_i= nfo *buf_info); + int (*write_to_host)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_in= fo *buf_info); =20 enum mhi_state mhi_state; =20 --=20 2.25.1 From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FA34C4167B for ; Mon, 27 Nov 2023 12:46:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233407AbjK0Mpy (ORCPT ); Mon, 27 Nov 2023 07:45:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233372AbjK0Mps (ORCPT ); Mon, 27 Nov 2023 07:45:48 -0500 Received: from mail-qk1-x72a.google.com (mail-qk1-x72a.google.com [IPv6:2607:f8b0:4864:20::72a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2965183 for ; Mon, 27 Nov 2023 04:45:53 -0800 (PST) Received: by mail-qk1-x72a.google.com with SMTP id af79cd13be357-778927f2dd3so183501185a.2 for ; Mon, 27 Nov 2023 04:45:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089153; x=1701693953; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eJdqJoClpTS7fqDf791uIaijLcGC8pNYAqyRdW5OMs4=; b=vjniASW2b0aS9pB9ayNFz4LW3kj9xZenT9qAym/OSGHUXTbVxFmrLQV3SjchhEjNvU CYehKqp6uoY0Lo+xflNl1p/6/r/e6b2O9D7Im/H6jcKZ4V66YnOUUy6GTHJ6wlAetkqc o4t8qSF12je2Dcs6NBD7C+D27UtdhGgdPqd8/EhOHowEMK3n4NTc9YU4JdcnOqwd4EYp ll3LXOLlp0Joly0hM4cRROngajMh7DHUoBrP1TM925mSeqYmYEuW8NfsS2jLVingx7xm 1F8t32ABBbrY9D77M4hrJPCaufiD6jcyAQyDNmjFMwoPWWoqeGGONDObl1dcG9SdVsJ8 b2cQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089153; x=1701693953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eJdqJoClpTS7fqDf791uIaijLcGC8pNYAqyRdW5OMs4=; b=C+04e/z5cxwVOinr28W5RzEnF0qC6l6QqOFgDV2E78bzL6BuLi0DPk2Fa+WnXq3GZr kx6VtxjjGdzQsy4J5NcqLqAks85eY8vlUWZ3ab+JJV+gtBCInEtucQx3BE6BQLYPpnLH ki1Q70xcXrgES84Y7Mq6xABls9de9M0txUt9i7/tLYpzLBGS96vdJ5DXDrvn7Ink1UmF vfsTdhLajWds3oHR34botL+76TOhayRqk/L8umi9rEJkMTL61Y3EXvyU6a81vC7QujvD fNSYr3SxISuDIFlFS5JaQGWPB4+5BHYCE8+Uji6CoYa0gQdP3qh1SS7fQqA65uGlzFMY WNCw== X-Gm-Message-State: AOJu0Yxhu0TkyvtMa0aOz+qkrRFNKQkrG85x4QuF7pGcz0TZkjx1Vpzx /xBsVvXT/QT7WeiszBTo0Mwi X-Google-Smtp-Source: AGHT+IHHFiydlH5dK8iSV8PMwXuYzFkx7SuLOEGF/fo5W8bAxDfHHMiuC2aBFQbxTuWHYuWWal/HtA== X-Received: by 2002:ad4:452c:0:b0:67a:338d:2efc with SMTP id l12-20020ad4452c000000b0067a338d2efcmr5135972qvu.11.1701089152934; Mon, 27 Nov 2023 04:45:52 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.45.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:45:52 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 2/9] bus: mhi: ep: Rename read_from_host() and write_to_host() APIs Date: Mon, 27 Nov 2023 18:15:22 +0530 Message-Id: <20231127124529.78203-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the preparation for adding async API support, let's rename the existing APIs to read_sync() and write_sync() to make it explicit that these APIs are used for synchronous read/write. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas --- drivers/bus/mhi/ep/main.c | 4 ++-- drivers/bus/mhi/ep/ring.c | 8 ++++---- drivers/pci/endpoint/functions/pci-epf-mhi.c | 8 ++++---- include/linux/mhi_ep.h | 8 ++++---- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index cdf5a84d1f21..5748a1da0803 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -381,7 +381,7 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi= _cntrl, buf_info.size =3D tr_len; =20 dev_dbg(dev, "Reading %zd bytes from channel (%u)\n", tr_len, ring->ch_i= d); - ret =3D mhi_cntrl->read_from_host(mhi_cntrl, &buf_info); + ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); if (ret < 0) { dev_err(&mhi_chan->mhi_dev->dev, "Error reading from channel\n"); return ret; @@ -543,7 +543,7 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, str= uct sk_buff *skb) buf_info.size =3D tr_len; =20 dev_dbg(dev, "Writing %zd bytes to channel (%u)\n", tr_len, ring->ch_id); - ret =3D mhi_cntrl->write_to_host(mhi_cntrl, &buf_info); + ret =3D mhi_cntrl->write_sync(mhi_cntrl, &buf_info); if (ret < 0) { dev_err(dev, "Error writing to the channel\n"); goto err_exit; diff --git a/drivers/bus/mhi/ep/ring.c b/drivers/bus/mhi/ep/ring.c index 7ea952860def..aeb53b2c34a8 100644 --- a/drivers/bus/mhi/ep/ring.c +++ b/drivers/bus/mhi/ep/ring.c @@ -48,7 +48,7 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, = size_t end) buf_info.host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_ele= ment)); buf_info.dev_addr =3D &ring->ring_cache[start]; =20 - ret =3D mhi_cntrl->read_from_host(mhi_cntrl, &buf_info); + ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); if (ret < 0) return ret; } else { @@ -56,7 +56,7 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, = size_t end) buf_info.host_addr =3D ring->rbase + (start * sizeof(struct mhi_ring_ele= ment)); buf_info.dev_addr =3D &ring->ring_cache[start]; =20 - ret =3D mhi_cntrl->read_from_host(mhi_cntrl, &buf_info); + ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); if (ret < 0) return ret; =20 @@ -65,7 +65,7 @@ static int __mhi_ep_cache_ring(struct mhi_ep_ring *ring, = size_t end) buf_info.dev_addr =3D &ring->ring_cache[0]; buf_info.size =3D end * sizeof(struct mhi_ring_element); =20 - ret =3D mhi_cntrl->read_from_host(mhi_cntrl, &buf_info); + ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); if (ret < 0) return ret; } @@ -143,7 +143,7 @@ int mhi_ep_ring_add_element(struct mhi_ep_ring *ring, s= truct mhi_ring_element *e buf_info.dev_addr =3D el; buf_info.size =3D sizeof(*el); =20 - return mhi_cntrl->write_to_host(mhi_cntrl, &buf_info); + return mhi_cntrl->write_sync(mhi_cntrl, &buf_info); } =20 void mhi_ep_ring_init(struct mhi_ep_ring *ring, enum mhi_ep_ring_type type= , u32 id) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 6dc918a8a023..34e7191f9508 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -536,11 +536,11 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->alloc_map =3D pci_epf_mhi_alloc_map; mhi_cntrl->unmap_free =3D pci_epf_mhi_unmap_free; if (info->flags & MHI_EPF_USE_DMA) { - mhi_cntrl->read_from_host =3D pci_epf_mhi_edma_read; - mhi_cntrl->write_to_host =3D pci_epf_mhi_edma_write; + mhi_cntrl->read_sync =3D pci_epf_mhi_edma_read; + mhi_cntrl->write_sync =3D pci_epf_mhi_edma_write; } else { - mhi_cntrl->read_from_host =3D pci_epf_mhi_iatu_read; - mhi_cntrl->write_to_host =3D pci_epf_mhi_iatu_write; + mhi_cntrl->read_sync =3D pci_epf_mhi_iatu_read; + mhi_cntrl->write_sync =3D pci_epf_mhi_iatu_write; } =20 /* Register the MHI EP controller */ diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index 96f3a133540d..b96b543bf2f6 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -94,8 +94,8 @@ struct mhi_ep_buf_info { * @raise_irq: CB function for raising IRQ to the host * @alloc_map: CB function for allocating memory in endpoint for storing h= ost context and mapping it * @unmap_free: CB function to unmap and free the allocated memory in endp= oint for storing host context - * @read_from_host: CB function for reading from host memory from endpoint - * @write_to_host: CB function for writing to host memory from endpoint + * @read_sync: CB function for reading from host memory synchronously + * @write_sync: CB function for writing to host memory synchronously * @mhi_state: MHI Endpoint state * @max_chan: Maximum channels supported by the endpoint controller * @mru: MRU (Maximum Receive Unit) value of the endpoint controller @@ -149,8 +149,8 @@ struct mhi_ep_cntrl { void __iomem **virt, size_t size); void (*unmap_free)(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, phys_add= r_t phys, void __iomem *virt, size_t size); - int (*read_from_host)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_i= nfo *buf_info); - int (*write_to_host)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_in= fo *buf_info); + int (*read_sync)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info *= buf_info); + int (*write_sync)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info); =20 enum mhi_state mhi_state; =20 --=20 2.25.1 From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 282F4C4167B for ; Mon, 27 Nov 2023 12:46:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233428AbjK0Mp5 (ORCPT ); Mon, 27 Nov 2023 07:45:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233400AbjK0Mpw (ORCPT ); Mon, 27 Nov 2023 07:45:52 -0500 Received: from mail-ot1-x32f.google.com (mail-ot1-x32f.google.com [IPv6:2607:f8b0:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5ED63198 for ; Mon, 27 Nov 2023 04:45:58 -0800 (PST) Received: by mail-ot1-x32f.google.com with SMTP id 46e09a7af769-6d30d9f4549so2577195a34.0 for ; Mon, 27 Nov 2023 04:45:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089157; x=1701693957; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ah8iq1Txz+5feKQ56aPHrEDMCkBylT8O2PmEcpgbM28=; b=RuXvUBGAKjjtt2WFuHTMGCEakadqjzI5hBbsshSwCsGVPxJUrrRoHPAwEoQNbE+mn2 0PE1tUs8o4ndBJ0Aq1vSJB2DEJu9+7YBMEPXL3LTCE4gYvrQ7ZGr2VHsfueiohs3kzN8 YkL9FYSepfSdRNlek8TI2UsJVIJG1HOWwSb1rLZEqtAdaimu0qMRzylJ29AABlUTDVW4 /VdgPlb5Y9GO2q0A5Kpg9oRfjmn9dODyckzwxhlLgdZEB1+XeaKbQOSSeyFhn4du3vEY /Uf/QIa363jhYvqLHtARPTEjx/uzFW58k0axdx1I0U/zSargvJ9fjAymQWIRxZtMOg3b RAEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089157; x=1701693957; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ah8iq1Txz+5feKQ56aPHrEDMCkBylT8O2PmEcpgbM28=; b=QlWs2XJZCX5qNILHSvHaQEYuULh1tjXGWsXd4QFgB/giR/OS9A07yBp0AbJrxr3dyK Mw9l4rzjb1bB93S5BAsgyrvVTZp0fWDG6ASVI7bPDGVYxt1oDuLTn891mJtv/PXE9yI9 B7Qmb9x2QPo/duSvTVnPVxtAuMoeOhNMpPE8VcYO6JaQCYItJySmBmi5//Dyqw7wMCf4 ruZv//qdtW9DAfRy65Fne2nQRgxYjzBXjMc+crkIRNCfIQ9hg0yxSXK6Hx4unhCXU+8a JgT5tNiIuATXsle9g96Tl8lsQ87LTbP09A3MYg7WmE9CyBPKOc3LjZuskknfS6N3s0+j BV6A== X-Gm-Message-State: AOJu0YwxYh+i3PqhEr1eJnXjBiJfdqsFzXVt5a/g0KLOfwZUHNKnEkNu s4dy4SSvml82xi+YUVe7TDS0 X-Google-Smtp-Source: AGHT+IG8yTjpBWVehWRL+B7ZcIXrUSuHpjOgGUeYzRMY3Yi+8iNrXtu1MquzIqT++f3DfkvIy4QlUQ== X-Received: by 2002:a9d:7d96:0:b0:6d7:f8c1:e473 with SMTP id j22-20020a9d7d96000000b006d7f8c1e473mr14360011otn.19.1701089157632; Mon, 27 Nov 2023 04:45:57 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.45.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:45:57 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 3/9] bus: mhi: ep: Introduce async read/write callbacks Date: Mon, 27 Nov 2023 18:15:23 +0530 Message-Id: <20231127124529.78203-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" These callbacks can be implemented by the controller drivers to perform async read/write operation that increases the throughput. For aiding the async operation, a completion callback is also introduced. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas --- include/linux/mhi_ep.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index b96b543bf2f6..14c6e8d3f573 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -54,11 +54,16 @@ struct mhi_ep_db_info { * @dev_addr: Address of the buffer in endpoint * @host_addr: Address of the bufffer in host * @size: Size of the buffer + * @cb: Callback to be executed by controller drivers after transfer compl= etion (async) + * @cb_buf: Opaque buffer to be passed to the callback */ struct mhi_ep_buf_info { void *dev_addr; u64 host_addr; size_t size; + + void (*cb)(struct mhi_ep_buf_info *buf_info); + void *cb_buf; }; =20 /** @@ -96,6 +101,8 @@ struct mhi_ep_buf_info { * @unmap_free: CB function to unmap and free the allocated memory in endp= oint for storing host context * @read_sync: CB function for reading from host memory synchronously * @write_sync: CB function for writing to host memory synchronously + * @read_async: CB function for reading from host memory asynchronously + * @write_async: CB function for writing to host memory asynchronously * @mhi_state: MHI Endpoint state * @max_chan: Maximum channels supported by the endpoint controller * @mru: MRU (Maximum Receive Unit) value of the endpoint controller @@ -151,6 +158,8 @@ struct mhi_ep_cntrl { void __iomem *virt, size_t size); int (*read_sync)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info *= buf_info); int (*write_sync)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info); + int (*read_async)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info = *buf_info); + int (*write_async)(struct mhi_ep_cntrl *mhi_cntrl, struct mhi_ep_buf_info= *buf_info); =20 enum mhi_state mhi_state; =20 --=20 2.25.1 From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8ED68C46CA0 for ; Mon, 27 Nov 2023 12:46:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233467AbjK0MqL (ORCPT ); Mon, 27 Nov 2023 07:46:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40908 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233410AbjK0MqB (ORCPT ); Mon, 27 Nov 2023 07:46:01 -0500 Received: from mail-qv1-xf30.google.com (mail-qv1-xf30.google.com [IPv6:2607:f8b0:4864:20::f30]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F26A3D5D for ; Mon, 27 Nov 2023 04:46:02 -0800 (PST) Received: by mail-qv1-xf30.google.com with SMTP id 6a1803df08f44-67a12079162so16282776d6.1 for ; Mon, 27 Nov 2023 04:46:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089162; x=1701693962; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=szORryW2l9J0pCg1kQG3OS6E1waFAt6BYGHK4qsw87M=; b=VAGhosd+z4xCejRdQEfPTtAgYbU0nVPbLa8Nq4RJjBNaj79B97hgFMQkObjHlqGfcr Znpb7txSt7DOV0k+R+G0cGz1HtkIuUJFIxd8VwpJrWG9rJul8rprB19xwhcyyAP1SxAq aDnUoo7auy4+MM78SavGy4XVDMpSo0ExF5M5R7nPY5ooj6+MqhR2IKb/oMz2hqx3mATW sa7P5U1ZougXN6WWfVXrwNnITBEIg5TaQoEGr40P+jUtjmV8merK8RhOrZ34/zQMhKjw 2KtYHfkU1rQR8KtaLmPNWZGqSkgNzXoYm8LBAPzPSZRXPE7G8P8S5opVdC9G9ozna4Ur K83w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089162; x=1701693962; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=szORryW2l9J0pCg1kQG3OS6E1waFAt6BYGHK4qsw87M=; b=i8HegVR79/m6PwXRQFAGT5Ctk76ZFVIHL6QFjlIB/NyIQO8XgzWBzpFiSJuOkwf32X I0zhEBh5zCZcHzJlF0Hr5hqTKuLvxaTFqlaM9zaXTnskrMUdYF32t7Gmnz+Mo4ydxmzc zE/n8jvEtO9FWMiUJxJ/2us2nd4ZQY++cIi52C4fBJXv5xWzK14WpXOyII4YCHThEpvk YH3uEVT97iLYgIeaFH54zZJ1HxKCQM/MmZoR969zB6rkjQ91GkMiTsdy7MCm3/6GOQMa hvFMbC6m/ljpCT179M1Pttn5Toqd9lGoRrgZMV0bo6hgpEpn4SpaAomHgr0r4uUrE0Li N9/Q== X-Gm-Message-State: AOJu0YzBPF2fOukjAQTOTvz4rjl3zCbkElgf/7lX9zHq/pxXr0Iku18w RPggvTJJ6Jmn643dYIeJg11S X-Google-Smtp-Source: AGHT+IGNZ+5w8hg9MvVkI8DO0QPnjtjCxvmdxlHAK2q1lIEDQmZD7Ge/AJWS0HSg8+MEFEMaOLLfag== X-Received: by 2002:a05:6214:5596:b0:67a:191f:2872 with SMTP id mi22-20020a056214559600b0067a191f2872mr12122455qvb.11.1701089162091; Mon, 27 Nov 2023 04:46:02 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.45.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:46:01 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 4/9] PCI: epf-mhi: Simulate async read/write using iATU Date: Mon, 27 Nov 2023 18:15:24 +0530 Message-Id: <20231127124529.78203-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Even though iATU only supports synchronous read/write, the MHI stack may call async read/write callbacks without knowing the limitations of the controller driver. So in order to maintain compatibility, let's simulate async read/write operation with iATU by invoking the completion callback after memcpy. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas Reviewed-by: Krzysztof Wilczy=C5=84ski --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 34e7191f9508..7214f4da733b 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -234,6 +234,9 @@ static int pci_epf_mhi_iatu_read(struct mhi_ep_cntrl *m= hi_cntrl, =20 mutex_unlock(&epf_mhi->lock); =20 + if (buf_info->cb) + buf_info->cb(buf_info); + return 0; } =20 @@ -262,6 +265,9 @@ static int pci_epf_mhi_iatu_write(struct mhi_ep_cntrl *= mhi_cntrl, =20 mutex_unlock(&epf_mhi->lock); =20 + if (buf_info->cb) + buf_info->cb(buf_info); + return 0; } =20 --=20 2.25.1 From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3561C0755A for ; Mon, 27 Nov 2023 12:46:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233517AbjK0Mq0 (ORCPT ); Mon, 27 Nov 2023 07:46:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233449AbjK0MqI (ORCPT ); Mon, 27 Nov 2023 07:46:08 -0500 Received: from mail-ot1-x32b.google.com (mail-ot1-x32b.google.com [IPv6:2607:f8b0:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B65231B4 for ; Mon, 27 Nov 2023 04:46:07 -0800 (PST) Received: by mail-ot1-x32b.google.com with SMTP id 46e09a7af769-6d81580d696so1075928a34.2 for ; Mon, 27 Nov 2023 04:46:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089166; x=1701693966; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=39EwDzZn0NPRyj1qXqtCdOxw1lfeEL1OF+pNH5oiRHU=; b=B5epaKsa3Sajl6ClCAlaYWAXke2IRjMH+wcLP7UjNScqemLiyeR3rLuY3vG3BCjzj1 EOrXxEkT6Tj45hguTlKcO8ZEw86TUzU2N0aKoDtpPAROlDplR8stcHJEqDsjjyFPksLr KR4iH3dEcmD+MocDq+Gwwi6Dnq0fEf5FUNTOus8BbYtMYV72wEuytJ2cWVxmUy6NKtCL cRh4ys7DS1IiVmQooDkVRCAO7LQAsUutlGHkOywOO/zh42fS32wO6ewyK5OCK2CIgIul UNeb53o367S/bhHoDgsCDHul/Mo5L8OvvPaC72d/iN8alHS8Mc0FabUFgZTIFU759RZk Vmpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089166; x=1701693966; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=39EwDzZn0NPRyj1qXqtCdOxw1lfeEL1OF+pNH5oiRHU=; b=l1Z7cHOc09CCvKPdEHvhaD6/qW9zVVbCK9zvnCimBjFm6fJbeiWAfRm/NYL1xmmBRr +5/B+YVgsnK30NADfXKSTDg+k31mQnk1CpObWNR38vbZPJix8oZlKDPq8Cw02gh8TQe9 qszAZhj++hHj2GyuvxouKFLVRlkjOSYei+15RQTBI7vHas6nEb+bLf4TYDskS/G6IMRx C6L3ERxwEmXFnggB9awDS9A858D/7WFYebgVeCbBm4YzOkrp2xsJuUS7+kWcRO2J7/T7 iDEyDcc68fs+vFdna8A4jESCGxlFV523j2LQvKEiw9WG/wtK72Z9dMDRrJ1bJmF/nc3Q 2SRQ== X-Gm-Message-State: AOJu0YzDu4/fWPqNkjRf0z9qaIhg0ugbGYjLGPn3RCKHPIy9wRKcbTua pTw158HC2xu+kFJLjtVk5E2/72Jmqj3MOjFYfA== X-Google-Smtp-Source: AGHT+IEf9XxgXqwBznbFGVOrIEZhtalj01eODY8VxfKTHk4t+FUDBuAKGwYEb/qCa5BZABeEE4aKxA== X-Received: by 2002:a9d:6c91:0:b0:6bc:63c9:7946 with SMTP id c17-20020a9d6c91000000b006bc63c97946mr12684837otr.14.1701089166388; Mon, 27 Nov 2023 04:46:06 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.46.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:46:06 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 5/9] PCI: epf-mhi: Add support for DMA async read/write operation Date: Mon, 27 Nov 2023 18:15:25 +0530 Message-Id: <20231127124529.78203-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The driver currently supports only the sync read/write operation i.e., it waits for the DMA transfer to complete before returning to the caller (MHI stack). But it is sub-optimal and defeats the actual purpose of using DMA. So let's add support for DMA async read/write operation by skipping the DMA transfer completion and returning to the caller immediately. When the completion actually happens later, the driver will be notified using the DMA completion handler and in turn it will notify the caller using the newly introduced callback in "struct mhi_ep_buf_info". Since the DMA completion handler is invoked from the interrupt context, a separate workqueue (epf_mhi->dma_wq) is used to notify the caller about the completion of the transfer. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas Reviewed-by: Krzysztof Wilczy=C5=84ski --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 231 ++++++++++++++++++- 1 file changed, 228 insertions(+), 3 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 7214f4da733b..3d09a37e5f7c 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -21,6 +21,15 @@ /* Platform specific flags */ #define MHI_EPF_USE_DMA BIT(0) =20 +struct pci_epf_mhi_dma_transfer { + struct pci_epf_mhi *epf_mhi; + struct mhi_ep_buf_info buf_info; + struct list_head node; + dma_addr_t paddr; + enum dma_data_direction dir; + size_t size; +}; + struct pci_epf_mhi_ep_info { const struct mhi_ep_cntrl_config *config; struct pci_epf_header *epf_header; @@ -124,6 +133,10 @@ struct pci_epf_mhi { resource_size_t mmio_phys; struct dma_chan *dma_chan_tx; struct dma_chan *dma_chan_rx; + struct workqueue_struct *dma_wq; + struct work_struct dma_work; + struct list_head dma_list; + spinlock_t list_lock; u32 mmio_size; int irq; }; @@ -418,6 +431,198 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl= *mhi_cntrl, return ret; } =20 +static void pci_epf_mhi_dma_worker(struct work_struct *work) +{ + struct pci_epf_mhi *epf_mhi =3D container_of(work, struct pci_epf_mhi, dm= a_work); + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct pci_epf_mhi_dma_transfer *itr, *tmp; + struct mhi_ep_buf_info *buf_info; + unsigned long flags; + LIST_HEAD(head); + + spin_lock_irqsave(&epf_mhi->list_lock, flags); + list_splice_tail_init(&epf_mhi->dma_list, &head); + spin_unlock_irqrestore(&epf_mhi->list_lock, flags); + + list_for_each_entry_safe(itr, tmp, &head, node) { + list_del(&itr->node); + dma_unmap_single(dma_dev, itr->paddr, itr->size, itr->dir); + buf_info =3D &itr->buf_info; + buf_info->cb(buf_info); + kfree(itr); + } +} + +static void pci_epf_mhi_dma_async_callback(void *param) +{ + struct pci_epf_mhi_dma_transfer *transfer =3D param; + struct pci_epf_mhi *epf_mhi =3D transfer->epf_mhi; + + spin_lock(&epf_mhi->list_lock); + list_add_tail(&transfer->node, &epf_mhi->dma_list); + spin_unlock(&epf_mhi->list_lock); + + queue_work(epf_mhi->dma_wq, &epf_mhi->dma_work); +} + +static int pci_epf_mhi_edma_read_async(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct pci_epf_mhi_dma_transfer *transfer =3D NULL; + struct dma_chan *chan =3D epf_mhi->dma_chan_rx; + struct device *dev =3D &epf_mhi->epf->dev; + DECLARE_COMPLETION_ONSTACK(complete); + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config =3D {}; + dma_cookie_t cookie; + dma_addr_t dst_addr; + int ret; + + mutex_lock(&epf_mhi->lock); + + config.direction =3D DMA_DEV_TO_MEM; + config.src_addr =3D buf_info->host_addr; + + ret =3D dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel\n"); + goto err_unlock; + } + + dst_addr =3D dma_map_single(dma_dev, buf_info->dev_addr, buf_info->size, + DMA_FROM_DEVICE); + ret =3D dma_mapping_error(dma_dev, dst_addr); + if (ret) { + dev_err(dev, "Failed to map remote memory\n"); + goto err_unlock; + } + + desc =3D dmaengine_prep_slave_single(chan, dst_addr, buf_info->size, + DMA_DEV_TO_MEM, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare DMA\n"); + ret =3D -EIO; + goto err_unmap; + } + + transfer =3D kzalloc(sizeof(*transfer), GFP_KERNEL); + if (!transfer) { + ret =3D -ENOMEM; + goto err_unmap; + } + + transfer->epf_mhi =3D epf_mhi; + transfer->paddr =3D dst_addr; + transfer->size =3D buf_info->size; + transfer->dir =3D DMA_FROM_DEVICE; + memcpy(&transfer->buf_info, buf_info, sizeof(*buf_info)); + + desc->callback =3D pci_epf_mhi_dma_async_callback; + desc->callback_param =3D transfer; + + cookie =3D dmaengine_submit(desc); + ret =3D dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to do DMA submit\n"); + goto err_free_transfer; + } + + dma_async_issue_pending(chan); + + goto err_unlock; + +err_free_transfer: + kfree(transfer); +err_unmap: + dma_unmap_single(dma_dev, dst_addr, buf_info->size, DMA_FROM_DEVICE); +err_unlock: + mutex_unlock(&epf_mhi->lock); + + return ret; +} + +static int pci_epf_mhi_edma_write_async(struct mhi_ep_cntrl *mhi_cntrl, + struct mhi_ep_buf_info *buf_info) +{ + struct pci_epf_mhi *epf_mhi =3D to_epf_mhi(mhi_cntrl); + struct device *dma_dev =3D epf_mhi->epf->epc->dev.parent; + struct pci_epf_mhi_dma_transfer *transfer =3D NULL; + struct dma_chan *chan =3D epf_mhi->dma_chan_tx; + struct device *dev =3D &epf_mhi->epf->dev; + DECLARE_COMPLETION_ONSTACK(complete); + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config =3D {}; + dma_cookie_t cookie; + dma_addr_t src_addr; + int ret; + + mutex_lock(&epf_mhi->lock); + + config.direction =3D DMA_MEM_TO_DEV; + config.dst_addr =3D buf_info->host_addr; + + ret =3D dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel\n"); + goto err_unlock; + } + + src_addr =3D dma_map_single(dma_dev, buf_info->dev_addr, buf_info->size, + DMA_TO_DEVICE); + ret =3D dma_mapping_error(dma_dev, src_addr); + if (ret) { + dev_err(dev, "Failed to map remote memory\n"); + goto err_unlock; + } + + desc =3D dmaengine_prep_slave_single(chan, src_addr, buf_info->size, + DMA_MEM_TO_DEV, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare DMA\n"); + ret =3D -EIO; + goto err_unmap; + } + + transfer =3D kzalloc(sizeof(*transfer), GFP_KERNEL); + if (!transfer) { + ret =3D -ENOMEM; + goto err_unmap; + } + + transfer->epf_mhi =3D epf_mhi; + transfer->paddr =3D src_addr; + transfer->size =3D buf_info->size; + transfer->dir =3D DMA_TO_DEVICE; + memcpy(&transfer->buf_info, buf_info, sizeof(*buf_info)); + + desc->callback =3D pci_epf_mhi_dma_async_callback; + desc->callback_param =3D transfer; + + cookie =3D dmaengine_submit(desc); + ret =3D dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to do DMA submit\n"); + goto err_free_transfer; + } + + dma_async_issue_pending(chan); + + goto err_unlock; + +err_free_transfer: + kfree(transfer); +err_unmap: + dma_unmap_single(dma_dev, src_addr, buf_info->size, DMA_TO_DEVICE); +err_unlock: + mutex_unlock(&epf_mhi->lock); + + return ret; +} + struct epf_dma_filter { struct device *dev; u32 dma_mask; @@ -441,6 +646,7 @@ static int pci_epf_mhi_dma_init(struct pci_epf_mhi *epf= _mhi) struct device *dev =3D &epf_mhi->epf->dev; struct epf_dma_filter filter; dma_cap_mask_t mask; + int ret; =20 dma_cap_zero(mask); dma_cap_set(DMA_SLAVE, mask); @@ -459,16 +665,35 @@ static int pci_epf_mhi_dma_init(struct pci_epf_mhi *e= pf_mhi) &filter); if (IS_ERR_OR_NULL(epf_mhi->dma_chan_rx)) { dev_err(dev, "Failed to request rx channel\n"); - dma_release_channel(epf_mhi->dma_chan_tx); - epf_mhi->dma_chan_tx =3D NULL; - return -ENODEV; + ret =3D -ENODEV; + goto err_release_tx; + } + + epf_mhi->dma_wq =3D alloc_workqueue("pci_epf_mhi_dma_wq", 0, 0); + if (!epf_mhi->dma_wq) { + ret =3D -ENOMEM; + goto err_release_rx; } =20 + INIT_LIST_HEAD(&epf_mhi->dma_list); + INIT_WORK(&epf_mhi->dma_work, pci_epf_mhi_dma_worker); + spin_lock_init(&epf_mhi->list_lock); + return 0; + +err_release_rx: + dma_release_channel(epf_mhi->dma_chan_rx); + epf_mhi->dma_chan_rx =3D NULL; +err_release_tx: + dma_release_channel(epf_mhi->dma_chan_tx); + epf_mhi->dma_chan_tx =3D NULL; + + return ret; } =20 static void pci_epf_mhi_dma_deinit(struct pci_epf_mhi *epf_mhi) { + destroy_workqueue(epf_mhi->dma_wq); dma_release_channel(epf_mhi->dma_chan_tx); dma_release_channel(epf_mhi->dma_chan_rx); epf_mhi->dma_chan_tx =3D NULL; --=20 2.25.1 From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 343E2C07CB1 for ; Mon, 27 Nov 2023 12:46:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233406AbjK0Mqk (ORCPT ); Mon, 27 Nov 2023 07:46:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233423AbjK0MqR (ORCPT ); Mon, 27 Nov 2023 07:46:17 -0500 Received: from mail-qk1-x729.google.com (mail-qk1-x729.google.com [IPv6:2607:f8b0:4864:20::729]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FB52D4D for ; Mon, 27 Nov 2023 04:46:12 -0800 (PST) Received: by mail-qk1-x729.google.com with SMTP id af79cd13be357-777745f1541so238561185a.0 for ; Mon, 27 Nov 2023 04:46:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089171; x=1701693971; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n0WeQVv6xDz1fA7FB+siaDKsF7jHm7RdEkvM6+sXcAk=; b=lZ6cKU83Ln+yT/quD7SMkjuwFY3qBG0aTEJS0eDJLPc+z7f10ZTOE9BTw5yPQsMu4B KjA05E+EIQ82KNtEcJ36VDnA78Sz+Pel8lJ1fOAw2dqzaNyxD2Uwfmot7VKOl8WwAtVC vWol2mFYS1sLZKRoplGwX7i4y+wYwYshYesxG7U/3G8fh+5x7vd33LULhwf8G9yXYGXv cJBGctkrKlqBTw0i2lrLUeQ4/sLTHFND19X7Nv+BzbZpvQ7UsNSfS/lLZd63BYfDszcW MLQw4nTqae/FSEK5EarttPP5YNwtAbXJckpVIq/bVSAddd5zD2r87JsLLJk4PeJ7sQG6 2XQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089171; x=1701693971; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n0WeQVv6xDz1fA7FB+siaDKsF7jHm7RdEkvM6+sXcAk=; b=oGEkHWSq6QTomEV6/QL8dkTxRhx20SynMNm/1w909cuI99tYl6yyp9qyJ0EaWU0jDn YvWldwlEx/xPW9oidiVZ6XCivp+i0T6yz7/r17UdS9h8Jd/rW7dEKz7vSCQ+jKoMGbAM mRcZbZQhXvpw9hJw7St1DZ/UPCmU3CgQ36+pWxUGH2ceYjbVf4jKiavoqCptZ9eYA2uh GpNDIp/KasKqlIDiqjATOru+n/07iG17MlElcQaFg3iKNW6Xrqe8t8uH42FN+Krcm2hg OQEyNja/YlwnrHJ8+/0g9luiee5sGnQeaLtK+xN9d5+7IvJFpNGD9OG+jr4wq68P4d7/ RixA== X-Gm-Message-State: AOJu0Yz8+edPOmSGVPlS4fPWxpkxpocksmCkkDVzJTsAO5B0xgr5Bx6b qGaV3cSqCxCKqTvJVoRW/qrC X-Google-Smtp-Source: AGHT+IERxAcM9ld/cVONnYwD9Qw8esi9QM+/QvFXWK+aoyDNWVgo9aOd0jymm0Z4uVeT5EbnhzFY6g== X-Received: by 2002:a05:6214:469b:b0:67a:35f3:4408 with SMTP id or27-20020a056214469b00b0067a35f34408mr9911296qvb.31.1701089170905; Mon, 27 Nov 2023 04:46:10 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:46:10 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 6/9] PCI: epf-mhi: Enable MHI async read/write support Date: Mon, 27 Nov 2023 18:15:26 +0530 Message-Id: <20231127124529.78203-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Now that both eDMA and iATU are prepared to support async transfer, let's enable MHI async read/write by supplying the relevant callbacks. In the absence of eDMA, iATU will be used for both sync and async operations. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas Reviewed-by: Krzysztof Wilczy=C5=84ski --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/end= point/functions/pci-epf-mhi.c index 3d09a37e5f7c..d3d6a1054036 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -766,12 +766,13 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->raise_irq =3D pci_epf_mhi_raise_irq; mhi_cntrl->alloc_map =3D pci_epf_mhi_alloc_map; mhi_cntrl->unmap_free =3D pci_epf_mhi_unmap_free; + mhi_cntrl->read_sync =3D mhi_cntrl->read_async =3D pci_epf_mhi_iatu_read; + mhi_cntrl->write_sync =3D mhi_cntrl->write_async =3D pci_epf_mhi_iatu_wri= te; if (info->flags & MHI_EPF_USE_DMA) { mhi_cntrl->read_sync =3D pci_epf_mhi_edma_read; mhi_cntrl->write_sync =3D pci_epf_mhi_edma_write; - } else { - mhi_cntrl->read_sync =3D pci_epf_mhi_iatu_read; - mhi_cntrl->write_sync =3D pci_epf_mhi_iatu_write; + mhi_cntrl->read_async =3D pci_epf_mhi_edma_read_async; + mhi_cntrl->write_async =3D pci_epf_mhi_edma_write_async; } =20 /* Register the MHI EP controller */ --=20 2.25.1 From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3FED0C4167B for ; Mon, 27 Nov 2023 12:46:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233505AbjK0Mqu (ORCPT ); Mon, 27 Nov 2023 07:46:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233508AbjK0MqY (ORCPT ); Mon, 27 Nov 2023 07:46:24 -0500 Received: from mail-qv1-xf32.google.com (mail-qv1-xf32.google.com [IPv6:2607:f8b0:4864:20::f32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B39631BD9 for ; Mon, 27 Nov 2023 04:46:16 -0800 (PST) Received: by mail-qv1-xf32.google.com with SMTP id 6a1803df08f44-67a2661560dso9458796d6.0 for ; Mon, 27 Nov 2023 04:46:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089175; x=1701693975; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qW88ClllHDY6AjewN5n1WX1VoidY5SA8L3B/8hzPqPI=; b=ByM5i+wZ7sLT7oHeruBSAjMulETO8Ub71bZPJLx7gLMiPiPktpbaapbHBjbpUPGvve TAnlwKhWQOhI3voXSCRlRXDkQV5nPfS76OAS9OwT8lBC323fZT6clTi1XjburpMsDGJU IJv+5EWPeI4J9tq5J3loPNqYuy0b6AvYUakkQBRQOzdbicXNnSgvY7Wtzq06cXeTWwN8 PGLnM7pd5YKp7rTltl6LGZ/STOx3Gs5Uhj2Gp9OHUcsqC5FEO9S8beB73zo/zeoHuMGH Y0FlayrlTBkUgPDsa+XXT9Ps6ASEXU3w/awrYucgoNpZK0dxcvM5JsxnxmxYaKcCEbwE Y9JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089175; x=1701693975; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qW88ClllHDY6AjewN5n1WX1VoidY5SA8L3B/8hzPqPI=; b=KeXZjazKu3dcIZ5PxFQTaPsXBRhj8v5QMkE1njiODjEbdXtcqRiNuEwsNCUrbp6EOg dyiwVvbWB6sM1aX0nH/mhHsiDkqXBcySkr00CAlwhjmtpGicwaOp3L1jYTi4ds4vhXZ3 zmZt669OpA+RNjxQdxXDAoF+UBGUqggKb+p2+sa3nMd0qnNJU9sKoJ4nvr2lWfdxdXuI YB+IdJ3u+/8ey+VgRWXyLqUodJxJrjJQFvBah357HYGBO5bAyfTIFgOWH+qsGQ+1Gupp zUKGX63+6yNdK3Y7CF93JrDSuFEtI2EWc13o0+PlMmsMuJa2j+BwRXnakhvjWx+phuD/ DkWw== X-Gm-Message-State: AOJu0YxZz1GyzsfQLauYrlmua38m401r5UAN+T1x/HiZgKXVph6mTf0b L7KYDFzGVnnyMmSU3+bb1RaY X-Google-Smtp-Source: AGHT+IFdbCFqoTtX+Sm5S1xk56menW+JLhUPVQVwmdvIov/0nHzslDYIDH2kfOOwiSGoAB/8AOKesQ== X-Received: by 2002:a05:6214:260d:b0:67a:5174:57d4 with SMTP id gu13-20020a056214260d00b0067a517457d4mr1037634qvb.47.1701089175547; Mon, 27 Nov 2023 04:46:15 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.46.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:46:15 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 7/9] bus: mhi: ep: Add support for async DMA write operation Date: Mon, 27 Nov 2023 18:15:27 +0530 Message-Id: <20231127124529.78203-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In order to optimize the data transfer, let's use the async DMA operation for writing (queuing) data to the host. In the async path, the completion event for the transfer ring will only be sent to the host when the controller driver notifies the MHI stack of the actual transfer completion using the callback (mhi_ep_skb_completion) supplied in "struct mhi_ep_buf_info". Also to accommodate the async operation, the transfer ring read offset (ring->rd_offset) is cached in the "struct mhi_ep_chan" and updated locally to let the stack queue further ring items to the controller driver. But the actual read offset of the transfer ring will only be updated in the completion callback. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas --- drivers/bus/mhi/ep/internal.h | 1 + drivers/bus/mhi/ep/main.c | 77 ++++++++++++++++++++++++++--------- include/linux/mhi_ep.h | 4 ++ 3 files changed, 62 insertions(+), 20 deletions(-) diff --git a/drivers/bus/mhi/ep/internal.h b/drivers/bus/mhi/ep/internal.h index 8c5cf2b67951..577965f95fda 100644 --- a/drivers/bus/mhi/ep/internal.h +++ b/drivers/bus/mhi/ep/internal.h @@ -162,6 +162,7 @@ struct mhi_ep_chan { void (*xfer_cb)(struct mhi_ep_device *mhi_dev, struct mhi_result *result); enum mhi_ch_state state; enum dma_data_direction dir; + size_t rd_offset; u64 tre_loc; u32 tre_size; u32 tre_bytes_left; diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 5748a1da0803..81d693433a5f 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -203,6 +203,8 @@ static int mhi_ep_process_cmd_ring(struct mhi_ep_ring *= ring, struct mhi_ring_ele =20 goto err_unlock; } + + mhi_chan->rd_offset =3D ch_ring->rd_offset; } =20 /* Set channel state to RUNNING */ @@ -332,7 +334,7 @@ bool mhi_ep_queue_is_empty(struct mhi_ep_device *mhi_de= v, enum dma_data_directio struct mhi_ep_cntrl *mhi_cntrl =3D mhi_dev->mhi_cntrl; struct mhi_ep_ring *ring =3D &mhi_cntrl->mhi_chan[mhi_chan->chan].ring; =20 - return !!(ring->rd_offset =3D=3D ring->wr_offset); + return !!(mhi_chan->rd_offset =3D=3D ring->wr_offset); } EXPORT_SYMBOL_GPL(mhi_ep_queue_is_empty); =20 @@ -359,7 +361,7 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi= _cntrl, return -ENODEV; } =20 - el =3D &ring->ring_cache[ring->rd_offset]; + el =3D &ring->ring_cache[mhi_chan->rd_offset]; =20 /* Check if there is data pending to be read from previous read operatio= n */ if (mhi_chan->tre_bytes_left) { @@ -438,6 +440,7 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi= _cntrl, tr_done =3D true; } =20 + mhi_chan->rd_offset =3D (mhi_chan->rd_offset + 1) % ring->ring_size; mhi_ep_ring_inc_index(ring); } =20 @@ -498,6 +501,37 @@ static int mhi_ep_process_ch_ring(struct mhi_ep_ring *= ring, struct mhi_ring_elem return 0; } =20 +static void mhi_ep_skb_completion(struct mhi_ep_buf_info *buf_info) +{ + struct mhi_ep_device *mhi_dev =3D buf_info->mhi_dev; + struct mhi_ep_cntrl *mhi_cntrl =3D mhi_dev->mhi_cntrl; + struct mhi_ep_chan *mhi_chan =3D mhi_dev->dl_chan; + struct mhi_ep_ring *ring =3D &mhi_cntrl->mhi_chan[mhi_chan->chan].ring; + struct mhi_ring_element *el =3D &ring->ring_cache[ring->rd_offset]; + struct device *dev =3D &mhi_dev->dev; + struct mhi_result result =3D {}; + int ret; + + if (mhi_chan->xfer_cb) { + result.buf_addr =3D buf_info->cb_buf; + result.dir =3D mhi_chan->dir; + result.bytes_xferd =3D buf_info->size; + + mhi_chan->xfer_cb(mhi_dev, &result); + } + + dev_dbg(dev, "Sending completion for ring (%d) rd_offset: %ld\n", +ring->er_index, ring->rd_offset); + ret =3D mhi_ep_send_completion_event(mhi_cntrl, ring, el, buf_info->size, + buf_info->code); + if (ret) { + dev_err(dev, "Error sending transfer completion event\n"); + return; + } + + mhi_ep_ring_inc_index(ring); +} + /* TODO: Handle partially formed TDs */ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, struct sk_buff *skb) { @@ -508,7 +542,6 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, str= uct sk_buff *skb) struct mhi_ring_element *el; u32 buf_left, read_offset; struct mhi_ep_ring *ring; - enum mhi_ev_ccs code; size_t tr_len; u32 tre_len; int ret; @@ -532,7 +565,7 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, str= uct sk_buff *skb) goto err_exit; } =20 - el =3D &ring->ring_cache[ring->rd_offset]; + el =3D &ring->ring_cache[mhi_chan->rd_offset]; tre_len =3D MHI_TRE_DATA_GET_LEN(el); =20 tr_len =3D min(buf_left, tre_len); @@ -541,33 +574,36 @@ int mhi_ep_queue_skb(struct mhi_ep_device *mhi_dev, s= truct sk_buff *skb) buf_info.dev_addr =3D skb->data + read_offset; buf_info.host_addr =3D MHI_TRE_DATA_GET_PTR(el); buf_info.size =3D tr_len; + buf_info.cb =3D mhi_ep_skb_completion; + buf_info.cb_buf =3D skb; + buf_info.mhi_dev =3D mhi_dev; =20 - dev_dbg(dev, "Writing %zd bytes to channel (%u)\n", tr_len, ring->ch_id); - ret =3D mhi_cntrl->write_sync(mhi_cntrl, &buf_info); - if (ret < 0) { - dev_err(dev, "Error writing to the channel\n"); - goto err_exit; - } - - buf_left -=3D tr_len; /* * For all TREs queued by the host for DL channel, only the EOT flag wil= l be set. * If the packet doesn't fit into a single TRE, send the OVERFLOW event = to * the host so that the host can adjust the packet boundary to next TREs= . Else send * the EOT event to the host indicating the packet boundary. */ - if (buf_left) - code =3D MHI_EV_CC_OVERFLOW; + if (buf_left - tr_len) + buf_info.code =3D MHI_EV_CC_OVERFLOW; else - code =3D MHI_EV_CC_EOT; + buf_info.code =3D MHI_EV_CC_EOT; =20 - ret =3D mhi_ep_send_completion_event(mhi_cntrl, ring, el, tr_len, code); - if (ret) { - dev_err(dev, "Error sending transfer completion event\n"); + dev_dbg(dev, "Writing %zd bytes to channel (%u)\n", tr_len, ring->ch_id); + ret =3D mhi_cntrl->write_async(mhi_cntrl, &buf_info); + if (ret < 0) { + dev_err(dev, "Error writing to the channel\n"); goto err_exit; } =20 - mhi_ep_ring_inc_index(ring); + buf_left -=3D tr_len; + /* + * Update the read offset cached in mhi_chan. Actual read offset + * will be updated by the completion handler. + */ + dev_dbg(dev, "rd_offset at the end of queue_skb: %ld\n", +mhi_chan->rd_offset); + mhi_chan->rd_offset =3D (mhi_chan->rd_offset + 1) % ring->ring_size; } while (buf_left); =20 mutex_unlock(&mhi_chan->lock); @@ -807,7 +843,7 @@ static void mhi_ep_ch_ring_worker(struct work_struct *w= ork) } =20 /* Sanity check to make sure there are elements in the ring */ - if (ring->rd_offset =3D=3D ring->wr_offset) { + if (chan->rd_offset =3D=3D ring->wr_offset) { mutex_unlock(&chan->lock); kmem_cache_free(mhi_cntrl->ring_item_cache, itr); continue; @@ -1451,6 +1487,7 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *m= hi_cntrl, ret =3D -ENOMEM; goto err_destroy_tre_buf_cache; } + INIT_WORK(&mhi_cntrl->state_work, mhi_ep_state_worker); INIT_WORK(&mhi_cntrl->reset_work, mhi_ep_reset_worker); INIT_WORK(&mhi_cntrl->cmd_ring_work, mhi_ep_cmd_ring_worker); diff --git a/include/linux/mhi_ep.h b/include/linux/mhi_ep.h index 14c6e8d3f573..11bf3212f782 100644 --- a/include/linux/mhi_ep.h +++ b/include/linux/mhi_ep.h @@ -51,16 +51,20 @@ struct mhi_ep_db_info { =20 /** * struct mhi_ep_buf_info - MHI Endpoint transfer buffer info + * @mhi_dev: MHI device associated with this buffer * @dev_addr: Address of the buffer in endpoint * @host_addr: Address of the bufffer in host * @size: Size of the buffer + * @code: Transfer completion code * @cb: Callback to be executed by controller drivers after transfer compl= etion (async) * @cb_buf: Opaque buffer to be passed to the callback */ struct mhi_ep_buf_info { + struct mhi_ep_device *mhi_dev; void *dev_addr; u64 host_addr; size_t size; + int code; =20 void (*cb)(struct mhi_ep_buf_info *buf_info); void *cb_buf; --=20 2.25.1 From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D53AC4167B for ; Mon, 27 Nov 2023 12:47:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233438AbjK0MrB (ORCPT ); Mon, 27 Nov 2023 07:47:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233469AbjK0Mq3 (ORCPT ); Mon, 27 Nov 2023 07:46:29 -0500 Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F247C19A3 for ; Mon, 27 Nov 2023 04:46:20 -0800 (PST) Received: by mail-qk1-x736.google.com with SMTP id af79cd13be357-77d5cf15280so225428785a.0 for ; Mon, 27 Nov 2023 04:46:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089180; x=1701693980; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XP1Q62qn1qYbW0mN98jl6FxqyTfpy980y9btw+6Mx30=; b=dIELJ4041EVuJczGWeurU8L6f3gdMe6j44u6lWX+p57v8wlpIArjBeykCj1OFsm31v d2LnMa5X1XC2qcNFLBO1Ua4KKYAgpkNqCWc9Z7hiu6ppu7px9/zDhsocGf00oiQmHyIP Y3PT7XjK7ppsuMSy5ekb2YhQBVcIUDiJpdCK4/bTCDK2ccekemtl+WXxrX61S76Slspy lrSQAvYcTYQf+5wAOGWXdlo8jgEISYJIxK5ZBQKMLuAKNbNY0rKZMpqF81u8mewTrtWz BReWI3ksRi7eoNrQIG5Bz2L7LFY/ZVyymqeExrt+/nd4Xw12IA7WRzivaQYcBdA1KcK/ L1Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089180; x=1701693980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XP1Q62qn1qYbW0mN98jl6FxqyTfpy980y9btw+6Mx30=; b=EdkUeIeOZ5E39W4OBhjUPFqRyVg9GlXm/K9lnqXru2mFn8QRIBvAGLe+/KqJLbkz+u OZMk1bBltAAH8yEuaUN+BZprD6u7oZJWcwZzFGSUwgeaXuZroUHlID0h5elzxMDp28p3 suF2rlE3M8+NYrcfUANe9ql9FEt9ngoNlk/SKBb4fV2p0fJgYiA+Qe/hO3/4B/qYhkKU hS3BqHSIl6agZx7Gb0sUKyfq1kVn4AeMWXUrvlYbGVqvWGAu72yVt7i93Iaz/9WyASbG o36L+njOMI8IUaLPTKJIOdt+KZN392+Fx6466pSczPWbfmrBWiRXQvnBKG1dcfXu+1We j4nA== X-Gm-Message-State: AOJu0YyEnsIIP8dKfjdHHitP/HdXlj9/aUNRhvlGCcZD9XTfVtp0MkQN 4tB4/TAY3ZoKWG91vG853iWm X-Google-Smtp-Source: AGHT+IEhhSlGm9jGIVtYRxFiZjw7yEzavFBoXCkhJpRjyMEKjMSY70wOHufalLLn6XKMn005Stusaw== X-Received: by 2002:a05:6214:d8e:b0:67a:3b18:1b1e with SMTP id e14-20020a0562140d8e00b0067a3b181b1emr5073397qve.54.1701089180007; Mon, 27 Nov 2023 04:46:20 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.46.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:46:19 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 8/9] bus: mhi: ep: Add support for async DMA read operation Date: Mon, 27 Nov 2023 18:15:28 +0530 Message-Id: <20231127124529.78203-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" As like the async DMA write operation, let's add support for async DMA read operation. In the async path, the data will be read from the transfer ring continuously and when the controller driver notifies the stack using the completion callback (mhi_ep_read_completion), then the client driver will be notified with the read data and the completion event will be sent to the host for the respective ring element (if requested by the host). Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas --- drivers/bus/mhi/ep/main.c | 162 +++++++++++++++++++++----------------- 1 file changed, 89 insertions(+), 73 deletions(-) diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 81d693433a5f..3e599d9640f5 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -338,17 +338,81 @@ bool mhi_ep_queue_is_empty(struct mhi_ep_device *mhi_= dev, enum dma_data_directio } EXPORT_SYMBOL_GPL(mhi_ep_queue_is_empty); =20 +static void mhi_ep_read_completion(struct mhi_ep_buf_info *buf_info) +{ + struct mhi_ep_device *mhi_dev =3D buf_info->mhi_dev; + struct mhi_ep_cntrl *mhi_cntrl =3D mhi_dev->mhi_cntrl; + struct mhi_ep_chan *mhi_chan =3D mhi_dev->ul_chan; + struct mhi_ep_ring *ring =3D &mhi_cntrl->mhi_chan[mhi_chan->chan].ring; + struct mhi_ring_element *el =3D &ring->ring_cache[ring->rd_offset]; + struct mhi_result result =3D {}; + int ret; + + if (mhi_chan->xfer_cb) { + result.buf_addr =3D buf_info->cb_buf; + result.dir =3D mhi_chan->dir; + result.bytes_xferd =3D buf_info->size; + + mhi_chan->xfer_cb(mhi_dev, &result); + } + + /* + * The host will split the data packet into multiple TREs if it can't fit + * the packet in a single TRE. In that case, CHAIN flag will be set by the + * host for all TREs except the last one. + */ + if (buf_info->code !=3D MHI_EV_CC_OVERFLOW) { + if (MHI_TRE_DATA_GET_CHAIN(el)) { + /* + * IEOB (Interrupt on End of Block) flag will be set by the host if + * it expects the completion event for all TREs of a TD. + */ + if (MHI_TRE_DATA_GET_IEOB(el)) { + ret =3D mhi_ep_send_completion_event(mhi_cntrl, ring, el, + MHI_TRE_DATA_GET_LEN(el), + MHI_EV_CC_EOB); + if (ret < 0) { + dev_err(&mhi_chan->mhi_dev->dev, + "Error sending transfer compl. event\n"); + goto err_free_tre_buf; + } + } + } else { + /* + * IEOT (Interrupt on End of Transfer) flag will be set by the host + * for the last TRE of the TD and expects the completion event for + * the same. + */ + if (MHI_TRE_DATA_GET_IEOT(el)) { + ret =3D mhi_ep_send_completion_event(mhi_cntrl, ring, el, + MHI_TRE_DATA_GET_LEN(el), + MHI_EV_CC_EOT); + if (ret < 0) { + dev_err(&mhi_chan->mhi_dev->dev, + "Error sending transfer compl. event\n"); + goto err_free_tre_buf; + } + } + } + } + + mhi_ep_ring_inc_index(ring); + +err_free_tre_buf: + kmem_cache_free(mhi_cntrl->tre_buf_cache, buf_info->cb_buf); +} + static int mhi_ep_read_channel(struct mhi_ep_cntrl *mhi_cntrl, - struct mhi_ep_ring *ring, - struct mhi_result *result, - u32 len) + struct mhi_ep_ring *ring) { struct mhi_ep_chan *mhi_chan =3D &mhi_cntrl->mhi_chan[ring->ch_id]; struct device *dev =3D &mhi_cntrl->mhi_dev->dev; size_t tr_len, read_offset, write_offset; struct mhi_ep_buf_info buf_info =3D {}; + u32 len =3D MHI_EP_DEFAULT_MTU; struct mhi_ring_element *el; bool tr_done =3D false; + void *buf_addr; u32 buf_left; int ret; =20 @@ -378,83 +442,50 @@ static int mhi_ep_read_channel(struct mhi_ep_cntrl *m= hi_cntrl, read_offset =3D mhi_chan->tre_size - mhi_chan->tre_bytes_left; write_offset =3D len - buf_left; =20 + buf_addr =3D kmem_cache_zalloc(mhi_cntrl->tre_buf_cache, GFP_KERNEL | GF= P_DMA); + if (!buf_addr) + return -ENOMEM; + buf_info.host_addr =3D mhi_chan->tre_loc + read_offset; - buf_info.dev_addr =3D result->buf_addr + write_offset; + buf_info.dev_addr =3D buf_addr + write_offset; buf_info.size =3D tr_len; + buf_info.cb =3D mhi_ep_read_completion; + buf_info.cb_buf =3D buf_addr; + buf_info.mhi_dev =3D mhi_chan->mhi_dev; + + if (mhi_chan->tre_bytes_left - tr_len) + buf_info.code =3D MHI_EV_CC_OVERFLOW; =20 dev_dbg(dev, "Reading %zd bytes from channel (%u)\n", tr_len, ring->ch_i= d); - ret =3D mhi_cntrl->read_sync(mhi_cntrl, &buf_info); + ret =3D mhi_cntrl->read_async(mhi_cntrl, &buf_info); if (ret < 0) { dev_err(&mhi_chan->mhi_dev->dev, "Error reading from channel\n"); - return ret; + goto err_free_buf_addr; } =20 buf_left -=3D tr_len; mhi_chan->tre_bytes_left -=3D tr_len; =20 - /* - * Once the TRE (Transfer Ring Element) of a TD (Transfer Descriptor) ha= s been - * read completely: - * - * 1. Send completion event to the host based on the flags set in TRE. - * 2. Increment the local read offset of the transfer ring. - */ if (!mhi_chan->tre_bytes_left) { - /* - * The host will split the data packet into multiple TREs if it can't f= it - * the packet in a single TRE. In that case, CHAIN flag will be set by = the - * host for all TREs except the last one. - */ - if (MHI_TRE_DATA_GET_CHAIN(el)) { - /* - * IEOB (Interrupt on End of Block) flag will be set by the host if - * it expects the completion event for all TREs of a TD. - */ - if (MHI_TRE_DATA_GET_IEOB(el)) { - ret =3D mhi_ep_send_completion_event(mhi_cntrl, ring, el, - MHI_TRE_DATA_GET_LEN(el), - MHI_EV_CC_EOB); - if (ret < 0) { - dev_err(&mhi_chan->mhi_dev->dev, - "Error sending transfer compl. event\n"); - return ret; - } - } - } else { - /* - * IEOT (Interrupt on End of Transfer) flag will be set by the host - * for the last TRE of the TD and expects the completion event for - * the same. - */ - if (MHI_TRE_DATA_GET_IEOT(el)) { - ret =3D mhi_ep_send_completion_event(mhi_cntrl, ring, el, - MHI_TRE_DATA_GET_LEN(el), - MHI_EV_CC_EOT); - if (ret < 0) { - dev_err(&mhi_chan->mhi_dev->dev, - "Error sending transfer compl. event\n"); - return ret; - } - } - + if (MHI_TRE_DATA_GET_IEOT(el)) tr_done =3D true; - } =20 mhi_chan->rd_offset =3D (mhi_chan->rd_offset + 1) % ring->ring_size; - mhi_ep_ring_inc_index(ring); } - - result->bytes_xferd +=3D tr_len; } while (buf_left && !tr_done); =20 return 0; + +err_free_buf_addr: + kmem_cache_free(mhi_cntrl->tre_buf_cache, buf_addr); + + return ret; } =20 -static int mhi_ep_process_ch_ring(struct mhi_ep_ring *ring, struct mhi_rin= g_element *el) +static int mhi_ep_process_ch_ring(struct mhi_ep_ring *ring) { struct mhi_ep_cntrl *mhi_cntrl =3D ring->mhi_cntrl; struct mhi_result result =3D {}; - u32 len =3D MHI_EP_DEFAULT_MTU; struct mhi_ep_chan *mhi_chan; int ret; =20 @@ -475,27 +506,15 @@ static int mhi_ep_process_ch_ring(struct mhi_ep_ring = *ring, struct mhi_ring_elem mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); } else { /* UL channel */ - result.buf_addr =3D kmem_cache_zalloc(mhi_cntrl->tre_buf_cache, GFP_KERN= EL | GFP_DMA); - if (!result.buf_addr) - return -ENOMEM; - do { - ret =3D mhi_ep_read_channel(mhi_cntrl, ring, &result, len); + ret =3D mhi_ep_read_channel(mhi_cntrl, ring); if (ret < 0) { dev_err(&mhi_chan->mhi_dev->dev, "Failed to read channel\n"); - kmem_cache_free(mhi_cntrl->tre_buf_cache, result.buf_addr); return ret; } =20 - result.dir =3D mhi_chan->dir; - mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); - result.bytes_xferd =3D 0; - memset(result.buf_addr, 0, len); - /* Read until the ring becomes empty */ } while (!mhi_ep_queue_is_empty(mhi_chan->mhi_dev, DMA_TO_DEVICE)); - - kmem_cache_free(mhi_cntrl->tre_buf_cache, result.buf_addr); } =20 return 0; @@ -804,7 +823,6 @@ static void mhi_ep_ch_ring_worker(struct work_struct *w= ork) struct mhi_ep_cntrl *mhi_cntrl =3D container_of(work, struct mhi_ep_cntrl= , ch_ring_work); struct device *dev =3D &mhi_cntrl->mhi_dev->dev; struct mhi_ep_ring_item *itr, *tmp; - struct mhi_ring_element *el; struct mhi_ep_ring *ring; struct mhi_ep_chan *chan; unsigned long flags; @@ -849,10 +867,8 @@ static void mhi_ep_ch_ring_worker(struct work_struct *= work) continue; } =20 - el =3D &ring->ring_cache[ring->rd_offset]; - dev_dbg(dev, "Processing the ring for channel (%u)\n", ring->ch_id); - ret =3D mhi_ep_process_ch_ring(ring, el); + ret =3D mhi_ep_process_ch_ring(ring); if (ret) { dev_err(dev, "Error processing ring for channel (%u): %d\n", ring->ch_id, ret); --=20 2.25.1 From nobody Wed Dec 17 12:43:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE09FC4167B for ; Mon, 27 Nov 2023 12:47:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233560AbjK0MrM (ORCPT ); Mon, 27 Nov 2023 07:47:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233376AbjK0Mqj (ORCPT ); Mon, 27 Nov 2023 07:46:39 -0500 Received: from mail-qv1-xf2d.google.com (mail-qv1-xf2d.google.com [IPv6:2607:f8b0:4864:20::f2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A36F183 for ; Mon, 27 Nov 2023 04:46:25 -0800 (PST) Received: by mail-qv1-xf2d.google.com with SMTP id 6a1803df08f44-67a47104064so4146506d6.0 for ; Mon, 27 Nov 2023 04:46:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701089184; x=1701693984; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F+E40YbuoBKmAjqkT6wNa06Lpu/e8RsvW8Aa+FgX6YU=; b=Kv8XsuqFwPw+PendwGLsbOjgoUZwmmT3PNk1mxw2t3U3kn4cdhjOHOB3kVmNQwXRAk FwLl9+lrIHbOTprVKPx7LVmilDBdEK2cryucwPqkRQGBp7Lg95NKTJlpq+/WSAv06VnZ 4O0SK9Ve9coWk5MEVF2+fDbj3Oqi1buONg1E7Z8jg7AJ7WB5NTSHkoRUhC4CeB+Rlnfp OkNF0U8pLmkJqPOCRN0i7xURl6HMX3h6VAL8BM7k3bMwMj1Y1hO1Bn1wQNv7AjshEKdq 3ZciFLgMMhz9goS2FCBdIIWhw14c/Z1E9FscQE65HBNiJgEmyXlwNLNghmjQ2+63MhvB VYNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701089184; x=1701693984; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F+E40YbuoBKmAjqkT6wNa06Lpu/e8RsvW8Aa+FgX6YU=; b=N7Sg05hmMaV1RhreJULStwjmmuPMVMnQAJMHHO4ChGPMfBkBN1g1ScFmGzLRa9ktg4 +Dk+L1xs6VynYPFbh06e78v/kTEndtBGdcY5upctdWzkirQhnXVwXgk7grOUcbFcrFK7 /JZepxSaw4odSMup7Dn5ll0GfkWQPdHHDFCrPc9XdQpPumRIOqjLUFMVJ/Yrl7YUM3wD 9/nwV+7YW77pShFhleqW6UhqIU97pZwhz1rfbWjuL3zc+0XbsEs4s4gh92jU2iXZj7Z0 MDwrvhPOgXrPRStk6zpsGTXirg+aTOZ+WWj2OSdgC6fg2oghvENevMjh3zaaJ9GKjMo2 2RwA== X-Gm-Message-State: AOJu0Yz971G9PYWK6IoCVn4BOvdfhiTAUj2unZROU7DBX5MSj1Lbne7o cFQb+3oH3J8X3NraUYpyV4N+ X-Google-Smtp-Source: AGHT+IGjJ2kzkE/6gacJvEqAeEjIAyBT1VNMtpx4NnbwGuihBYTTMBLfyUdv0rtU06YkX96BCpwzXQ== X-Received: by 2002:a0c:edcd:0:b0:67a:49c5:8cc3 with SMTP id i13-20020a0cedcd000000b0067a49c58cc3mr1827133qvr.32.1701089184590; Mon, 27 Nov 2023 04:46:24 -0800 (PST) Received: from localhost.localdomain ([117.213.103.241]) by smtp.gmail.com with ESMTPSA id er10-20020a056214190a00b0067a204b4688sm2832231qvb.18.2023.11.27.04.46.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 04:46:24 -0800 (PST) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 9/9] bus: mhi: ep: Add checks for read/write callbacks while registering controllers Date: Mon, 27 Nov 2023 18:15:29 +0530 Message-Id: <20231127124529.78203-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The MHI EP controller drivers has to support both sync and async read/write callbacks. Hence, add a check for it. Signed-off-by: Manivannan Sadhasivam Acked-by: Bjorn Helgaas --- drivers/bus/mhi/ep/main.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/bus/mhi/ep/main.c b/drivers/bus/mhi/ep/main.c index 3e599d9640f5..6b84aeeb247a 100644 --- a/drivers/bus/mhi/ep/main.c +++ b/drivers/bus/mhi/ep/main.c @@ -1471,6 +1471,10 @@ int mhi_ep_register_controller(struct mhi_ep_cntrl *= mhi_cntrl, if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->mmio || !mhi_cntrl= ->irq) return -EINVAL; =20 + if (!mhi_cntrl->read_sync || !mhi_cntrl->write_sync || + !mhi_cntrl->read_async || !mhi_cntrl->write_async) + return -EINVAL; + ret =3D mhi_ep_chan_init(mhi_cntrl, config); if (ret) return ret; --=20 2.25.1