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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ram=C3=B3n=20N=2ERodriguez?= Subject: [PATCH 1/3] net: microchip_t1s: refactor reset functionality Date: Mon, 27 Nov 2023 11:40:43 +0100 Message-ID: <20231127104045.96722-2-ramon.nordin.rodriguez@ferroamp.se> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231127104045.96722-1-ramon.nordin.rodriguez@ferroamp.se> References: <20231127104045.96722-1-ramon.nordin.rodriguez@ferroamp.se> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ram=C3=B3n Nordin Rodriguez This commit moves the reset functionality for lan867x from the revb1 init function to a separate function. The intention with this minor refactor is to prepare for adding support for lan867x rev C1. Signed-off-by: Ram=C3=B3n Nordin Rodriguez Reviewed-by: Andrew Lunn --- drivers/net/phy/microchip_t1s.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index 534ca7d1b061..ace2bf35a18a 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -213,7 +213,7 @@ static int lan865x_revb0_config_init(struct phy_device = *phydev) return lan865x_setup_cfgparam(phydev); } =20 -static int lan867x_revb1_config_init(struct phy_device *phydev) +static int lan867x_wait_for_reset_complete(struct phy_device *phydev) { int err; =20 @@ -234,6 +234,16 @@ static int lan867x_revb1_config_init(struct phy_device= *phydev) return -ENODEV; } } + return 0; +} + +static int lan867x_revb1_config_init(struct phy_device *phydev) +{ + int err; + + err =3D lan867x_wait_for_reset_complete(phydev); + if (err) + return err; =20 /* Reference to AN1699 * https://ww1.microchip.com/downloads/aemDocuments/documents/AIS/Product= Documents/SupportingCollateral/AN-LAN8670-1-2-config-60001699.pdf --=20 2.40.1 From nobody Wed Dec 17 12:19:19 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FCDCC07D5A for ; Mon, 27 Nov 2023 10:41:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233056AbjK0Klg (ORCPT ); Mon, 27 Nov 2023 05:41:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233018AbjK0Klb (ORCPT ); Mon, 27 Nov 2023 05:41:31 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1866B136 for ; Mon, 27 Nov 2023 02:41:37 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-507962561adso6155587e87.0 for ; Mon, 27 Nov 2023 02:41:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ferroamp-se.20230601.gappssmtp.com; s=20230601; t=1701081695; x=1701686495; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ywOmUh3+E3BrPrVrzGPyOnQBIBtadDkzgT4Gfly9luU=; b=usgzsHoI3U6TkoYITS5G/id7DF71mcUwqy60tdenlD5fijl3cTV1lXtml0CVuhU3Jm 8/kM/uLx/1noQZlE7kspFrsSyi8Tmp7SFAPJq2prstC0x6Lrfm6DjSFkuMobzg9gBQwK LN9J9ycQSbROpAd19NLzOp8YoirK3TGsaHMqPv6uv1Bu8HJGCGB0GUnaXijYLi2XXMup E5yzTHK2mNLnuXhj6r3VLAK7JqdhipYZz7QW1grG6VOEDBdVmvwZgEcGZ3ZzatwFfZAR Tz+uQ2gpdxEWJ/NiF9jX9I4If9xUUAFnBvBr0BzaXFW4FqFSnBTaEeWImc80M8dt11TX j9wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701081695; x=1701686495; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ywOmUh3+E3BrPrVrzGPyOnQBIBtadDkzgT4Gfly9luU=; b=Y0srojANTglolf2+0t32ub6ji1s8YfXFe8P6+aOAMFOVQ7Rf400wUUpQdau2l6XenU zw+4CK6pyVCInJptE3hRUeSPzbnb/sh3zjIp1RcPcVNhAhOBVAXhUgRfFQLALV0gSbsj C4xfF8uJuahBtV5KBc5OtNh9/3wbt1TlsOt1lBwhx8e6knVBZkScrEk84Yuzv0+9UjUL yRFXYspUZfXrcAcnGj3XRwDTLRG52dVvZYxw2eoB1TS/L0geZBgHtXZMVeSzFnBREnKK 1G/QY7xnZHw3g7s0Lg0/rSOY1106sDEBs/s5Dq9YV3BPGraDxaxRQ6KYK3WEVLx5PAC1 r0WQ== X-Gm-Message-State: AOJu0YzzLO7kYpgjDybBPXdnD1vygYfMixBodc+7i1vbnm2ZRAFiwlP0 CKH+gaDpvEDYocgW1iTJIXwMog== X-Google-Smtp-Source: AGHT+IFnNWMBpcw27UBqGAplcSub4tfqzr/5uFem0JSEXjZ+D63ENv+dHHYwT+N5O3+TSDiDa44iGw== X-Received: by 2002:a05:6512:2101:b0:50b:aa7e:c350 with SMTP id q1-20020a056512210100b0050baa7ec350mr3988251lfr.36.1701081695415; Mon, 27 Nov 2023 02:41:35 -0800 (PST) Received: from localhost.localdomain ([185.117.107.42]) by smtp.gmail.com with ESMTPSA id l6-20020a19c206000000b004fe1f1c0ee4sm1432070lfc.82.2023.11.27.02.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 02:41:34 -0800 (PST) From: =?UTF-8?q?Ram=C3=B3n=20N=2ERodriguez?= To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ram=C3=B3n=20N=2ERodriguez?= Subject: [PATCH 2/3] net: microchip_t1s: add support for LAN867x Rev.C1 Date: Mon, 27 Nov 2023 11:40:44 +0100 Message-ID: <20231127104045.96722-3-ramon.nordin.rodriguez@ferroamp.se> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231127104045.96722-1-ramon.nordin.rodriguez@ferroamp.se> References: <20231127104045.96722-1-ramon.nordin.rodriguez@ferroamp.se> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ram=C3=B3n Nordin Rodriguez This commit adds support for yet another Microchip T1S lan867x phy revision. The only meaningful difference between Rev.B that already is supported and Rev.C is the init change where other undocumented regs needs writes with unexplained values. The changes introduced here attempts to follow the manufacturer recommendations in AN1699. Signed-off-by: Ram=C3=B3n Nordin Rodriguez --- drivers/net/phy/microchip_t1s.c | 96 +++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index ace2bf35a18a..db84d850b165 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -12,6 +12,7 @@ #include =20 #define PHY_ID_LAN867X_REVB1 0x0007C162 +#define PHY_ID_LAN867X_REVC1 0x0007C164 #define PHY_ID_LAN865X_REVB0 0x0007C1B3 =20 #define LAN867X_REG_STS2 0x0019 @@ -59,6 +60,22 @@ static const u16 lan867x_revb1_fixup_masks[12] =3D { 0x0600, 0x7F00, 0x2000, 0xFFFF, }; =20 +static const u16 lan867x_revc1_fixup_registers[12] =3D { + 0x00D0, 0x00E0, 0x0084, 0x008A, + 0x00E9, 0x00F5, 0x00F4, 0x00F8, + 0x00F9, 0x0081, 0x0091, 0x0093, +}; + +/* Index 2 & 3 will not be used, these are runtime populated/calculated. + * It makes the code a lot easier to read having this arr the same len + * as the _fixup_registers arr though + */ +static const u16 lan867x_revc1_fixup_values[12] =3D { + 0x3F31, 0xC000, 0xFFFF, 0xFFFF, + 0x9E50, 0x1CF8, 0xC020, 0x9B00, + 0x4E53, 0x0080, 0x9660, 0x06E9, +}; + /* LAN865x Rev.B0 configuration parameters from AN1760 */ static const u32 lan865x_revb0_fixup_registers[28] =3D { 0x0091, 0x0081, 0x0043, 0x0044, @@ -263,6 +280,74 @@ static int lan867x_revb1_config_init(struct phy_device= *phydev) return 0; } =20 +static int lan867x_revc1_read_fixup_value(struct phy_device *phydev, u16 a= ddr) +{ + int regval; + /* The AN pretty much just states 'trust us' regarding these magic vals */ + const u16 magic_or =3D 0xE0; + const u16 magic_reg_mask =3D 0x1F; + const u16 magic_check_mask =3D 0x10; + + regval =3D lan865x_revb0_indirect_read(phydev, addr); + if (regval < 0) + return regval; + + regval &=3D magic_reg_mask; + + return (regval & magic_check_mask) ? regval | magic_or : regval; +} + +static int lan867x_revc1_config_init(struct phy_device *phydev) +{ + int err; + int regval; + u16 override0; + u16 override1; + const u16 override_addr0 =3D 0x4; + const u16 override_addr1 =3D 0x8; + const u8 index_to_override0 =3D 2; + const u8 index_to_override1 =3D 3; + + err =3D lan867x_wait_for_reset_complete(phydev); + if (err) + return err; + + /* The application note specifies a super convenient process + * where 2 of the fixup regs needs a write with a value that is + * a modified result of another reg read. + * Enjoy the magic show. + */ + regval =3D lan867x_revc1_read_fixup_value(phydev, override_addr0); + if (regval < 0) + return regval; + override0 =3D ((regval + 9) << 10) | ((regval + 14) << 4) | 0x3; + + regval =3D lan867x_revc1_read_fixup_value(phydev, override_addr1); + if (regval < 0) + return regval; + override1 =3D (regval + 40) << 10; + + for (int i =3D 0; i < ARRAY_SIZE(lan867x_revc1_fixup_registers); i++) { + /* The hardcoded */ + if (i =3D=3D index_to_override0) + err =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan867x_revc1_fixup_registers[i], + override0); + else if (i =3D=3D index_to_override1) + err =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan867x_revc1_fixup_registers[i], + override1); + else + err =3D phy_write_mmd(phydev, MDIO_MMD_VEND2, + lan867x_revc1_fixup_registers[i], + lan867x_revc1_fixup_values[i]); + if (err) + return err; + } + + return 0; +} + static int lan86xx_read_status(struct phy_device *phydev) { /* The phy has some limitations, namely: @@ -289,6 +374,16 @@ static struct phy_driver microchip_t1s_driver[] =3D { .set_plca_cfg =3D genphy_c45_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, + { + PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1), + .name =3D "LAN867X Rev.C1", + .features =3D PHY_BASIC_T1S_P2MP_FEATURES, + .config_init =3D lan867x_revc1_config_init, + .read_status =3D lan86xx_read_status, + .get_plca_cfg =3D genphy_c45_plca_get_cfg, + .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .get_plca_status =3D genphy_c45_plca_get_status, + }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0), .name =3D "LAN865X Rev.B0 Internal Phy", @@ -305,6 +400,7 @@ module_phy_driver(microchip_t1s_driver); =20 static struct mdio_device_id __maybe_unused tbl[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1) }, + { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVC1) }, { PHY_ID_MATCH_EXACT(PHY_ID_LAN865X_REVB0) }, { } }; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Cc: =?UTF-8?q?Ram=C3=B3n=20N=2ERodriguez?= Subject: [PATCH 3/3] net: microchip_t1s: conditional collision detection Date: Mon, 27 Nov 2023 11:40:45 +0100 Message-ID: <20231127104045.96722-4-ramon.nordin.rodriguez@ferroamp.se> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231127104045.96722-1-ramon.nordin.rodriguez@ferroamp.se> References: <20231127104045.96722-1-ramon.nordin.rodriguez@ferroamp.se> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ram=C3=B3n Nordin Rodriguez This commit conditionally sets the collision detection bit on lan867x and lan865x phys on changing PLCA enabled on/off. The intended realworld scenario is that all nodes on the network run the same settings with regards to plca, and when plca is enabled the physical layer guarantees that no collisions should occur. In a practical setting where it was tested running one node with collision detection on and other off, the node with collision detection on dropped a lot of packets, leading to a poor performing link. Worth noting here is that the phys default/reset to plca disabled and collision detection enabled. Thus this change would only have an effect when changing settings via ethtool. Signed-off-by: Ram=C3=B3n Nordin Rodriguez --- drivers/net/phy/microchip_t1s.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/net/phy/microchip_t1s.c b/drivers/net/phy/microchip_t1= s.c index db84d850b165..3b1e82ecdf69 100644 --- a/drivers/net/phy/microchip_t1s.c +++ b/drivers/net/phy/microchip_t1s.c @@ -23,8 +23,10 @@ #define LAN865X_REG_CFGPARAM_DATA 0x00D9 #define LAN865X_REG_CFGPARAM_CTRL 0x00DA #define LAN865X_REG_STS2 0x0019 +#define LAN86XX_REG_COLLISION_DETECT 0x0087 =20 #define LAN865X_CFGPARAM_READ_ENABLE BIT(1) +#define LAN86XX_COLLISION_DETECT_ENABLE BIT(15) =20 /* The arrays below are pulled from the following table from AN1699 * Access MMD Address Value Mask @@ -363,6 +365,27 @@ static int lan86xx_read_status(struct phy_device *phyd= ev) return 0; } =20 +static int lan86xx_plca_set_cfg(struct phy_device *phydev, + const struct phy_plca_cfg *plca_cfg) +{ + int err; + + err =3D genphy_c45_plca_set_cfg(phydev, plca_cfg); + if (err) + return err; + + /* Disable collision detect on the phy when PLCA is enabled. + * Noise can be picked up as a false positive for collisions + * leading to the phy dropping legitimate packets. + * No collisions should be possible when all nodes are setup + * for running PLCA. + */ + return phy_modify_mmd(phydev, MDIO_MMD_VEND2, + LAN86XX_REG_COLLISION_DETECT, + LAN86XX_COLLISION_DETECT_ENABLE, + plca_cfg->enabled ? 0 : LAN86XX_COLLISION_DETECT_ENABLE); +} + static struct phy_driver microchip_t1s_driver[] =3D { { PHY_ID_MATCH_EXACT(PHY_ID_LAN867X_REVB1), @@ -371,7 +394,7 @@ static struct phy_driver microchip_t1s_driver[] =3D { .config_init =3D lan867x_revb1_config_init, .read_status =3D lan86xx_read_status, .get_plca_cfg =3D genphy_c45_plca_get_cfg, - .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, { @@ -381,7 +404,7 @@ static struct phy_driver microchip_t1s_driver[] =3D { .config_init =3D lan867x_revc1_config_init, .read_status =3D lan86xx_read_status, .get_plca_cfg =3D genphy_c45_plca_get_cfg, - .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, { @@ -391,7 +414,7 @@ static struct phy_driver microchip_t1s_driver[] =3D { .config_init =3D lan865x_revb0_config_init, .read_status =3D lan86xx_read_status, .get_plca_cfg =3D genphy_c45_plca_get_cfg, - .set_plca_cfg =3D genphy_c45_plca_set_cfg, + .set_plca_cfg =3D lan86xx_plca_set_cfg, .get_plca_status =3D genphy_c45_plca_get_status, }, }; --=20 2.40.1