From nobody Wed Dec 17 12:17:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35217C4167B for ; Mon, 27 Nov 2023 01:36:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231370AbjK0BgW convert rfc822-to-8bit (ORCPT ); Sun, 26 Nov 2023 20:36:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231230AbjK0BgS (ORCPT ); Sun, 26 Nov 2023 20:36:18 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0601811B for ; Sun, 26 Nov 2023 17:36:19 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id BE7CB24DC0A; Mon, 27 Nov 2023 09:36:15 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 27 Nov 2023 09:36:16 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 27 Nov 2023 09:36:11 +0800 From: Sia Jee Heng To: , , , , , , CC: , , , Subject: [PATCH 1/7] dt-bindings: riscv: Add StarFive Dubhe compatibles Date: Mon, 27 Nov 2023 09:35:56 +0800 Message-ID: <20231127013602.253835-2-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> References: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Dubhe-80 and Dubhe-90 are RISC-V cpu core from StarFive Technology. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentat= ion/devicetree/bindings/riscv/cpus.yaml index f392e367d673..493972b29a22 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -48,6 +48,8 @@ properties: - thead,c906 - thead,c910 - thead,c920 + - starfive,dubhe-80 + - starfive,dubhe-90 - const: riscv - items: - enum: --=20 2.34.1 From nobody Wed Dec 17 12:17:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAC0AC07CA9 for ; Mon, 27 Nov 2023 01:36:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231439AbjK0BgY convert rfc822-to-8bit (ORCPT ); Sun, 26 Nov 2023 20:36:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231281AbjK0BgS (ORCPT ); Sun, 26 Nov 2023 20:36:18 -0500 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14284119 for ; Sun, 26 Nov 2023 17:36:23 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 50CEC24E2AC; Mon, 27 Nov 2023 09:36:20 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 27 Nov 2023 09:36:20 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 27 Nov 2023 09:36:16 +0800 From: Sia Jee Heng To: , , , , , , CC: , , , Subject: [PATCH 2/7] dt-bindings: riscv: Add StarFive JH8100 SoC Date: Mon, 27 Nov 2023 09:35:57 +0800 Message-ID: <20231127013602.253835-3-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> References: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add device tree bindings for the StarFive JH8100 RISC-V SoC Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- Documentation/devicetree/bindings/riscv/starfive.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Docume= ntation/devicetree/bindings/riscv/starfive.yaml index cc4d92f0a1bf..7e2da9eef3db 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -29,7 +29,10 @@ properties: - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b - const: starfive,jh7110 - + - items: + - enum: + - starfive,jh8100-evb + - const: starfive,jh8100 additionalProperties: true =20 ... --=20 2.34.1 From nobody Wed Dec 17 12:17:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79B04C4167B for ; Mon, 27 Nov 2023 01:36:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231586AbjK0Bg2 convert rfc822-to-8bit (ORCPT ); Sun, 26 Nov 2023 20:36:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231310AbjK0BgT (ORCPT ); Sun, 26 Nov 2023 20:36:19 -0500 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20A6611D for ; Sun, 26 Nov 2023 17:36:26 -0800 (PST) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id C8BE224DC65; Mon, 27 Nov 2023 09:36:24 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 27 Nov 2023 09:36:25 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 27 Nov 2023 09:36:20 +0800 From: Sia Jee Heng To: , , , , , , CC: , , , Subject: [PATCH 3/7] dt-bindings: timer: Add StarFive JH8100 clint Date: Mon, 27 Nov 2023 09:35:58 +0800 Message-ID: <20231127013602.253835-4-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> References: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible string for the StarFive JH8100 clint Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Do= cumentation/devicetree/bindings/timer/sifive,clint.yaml index e8be6c470364..01254261e156 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -33,6 +33,7 @@ properties: - sifive,fu540-c000-clint # SiFive FU540 - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 + - starfive,jh8100-clint # StarFive JH8100 - const: sifive,clint0 # SiFive CLINT v0 IP block - items: - enum: --=20 2.34.1 From nobody Wed Dec 17 12:17:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B4850C4167B for ; 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Mon, 27 Nov 2023 09:36:25 +0800 From: Sia Jee Heng To: , , , , , , CC: , , , Subject: [PATCH 4/7] dt-bindings: interrupt-controller: Add StarFive JH8100 plic Date: Mon, 27 Nov 2023 09:35:59 +0800 Message-ID: <20231127013602.253835-5-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> References: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add compatible string for StarFive JH8100 plic Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 0c07e8dda445..8f5c6044cef7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -61,6 +61,7 @@ properties: - sifive,fu540-c000-plic - starfive,jh7100-plic - starfive,jh7110-plic + - starfive,jh8100-plic - const: sifive,plic-1.0.0 - items: - enum: --=20 2.34.1 From nobody Wed Dec 17 12:17:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5328EC4167B for ; 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Mon, 27 Nov 2023 09:36:34 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 27 Nov 2023 09:36:29 +0800 From: Sia Jee Heng To: , , , , , , CC: , , , Subject: [PATCH 5/7] dt-bindings: xilinx: Add StarFive compatible string Date: Mon, 27 Nov 2023 09:36:00 +0800 Message-ID: <20231127013602.253835-6-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> References: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add starfive,jh8100-uart compatible string Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- Documentation/devicetree/bindings/serial/cdns,uart.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Docu= mentation/devicetree/bindings/serial/cdns,uart.yaml index e35ad1109efc..254373cb1ac7 100644 --- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml +++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml @@ -20,6 +20,9 @@ properties: items: - const: xlnx,zynqmp-uart - const: cdns,uart-r1p12 + - description: UART controller for StarFive JH8100 SoC + items: + - const: starfive,jh8100-uart =20 reg: maxItems: 1 --=20 2.34.1 From nobody Wed Dec 17 12:17:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3F80C4167B for ; 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Mon, 27 Nov 2023 09:36:37 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 27 Nov 2023 09:36:34 +0800 From: Sia Jee Heng To: , , , , , , CC: , , , Subject: [PATCH 6/7] serial: xilinx_uartps: Add new compatible string for StarFive Date: Mon, 27 Nov 2023 09:36:01 +0800 Message-ID: <20231127013602.253835-7-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> References: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This patch adds the new compatible string for StarFive JH8100 SoC Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- drivers/tty/serial/xilinx_uartps.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx= _uartps.c index 66a45a634158..170901c143c2 100644 --- a/drivers/tty/serial/xilinx_uartps.c +++ b/drivers/tty/serial/xilinx_uartps.c @@ -1210,7 +1210,7 @@ OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_= console_setup); OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); - +OF_EARLYCON_DECLARE(cdns, "starfive,jh8100-uart", cdns_early_console_setup= ); =20 /* Static pointer to console port */ static struct uart_port *console_port; @@ -1448,6 +1448,7 @@ static const struct of_device_id cdns_uart_of_match[]= =3D { { .compatible =3D "cdns,uart-r1p8", }, { .compatible =3D "cdns,uart-r1p12", .data =3D &zynqmp_uart_def }, { .compatible =3D "xlnx,zynqmp-uart", .data =3D &zynqmp_uart_def }, + { .compatible =3D "starfive,jh8100-uart", }, {} }; MODULE_DEVICE_TABLE(of, cdns_uart_of_match); --=20 2.34.1 From nobody Wed Dec 17 12:17:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28012C07CA9 for ; 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Mon, 27 Nov 2023 09:36:38 +0800 From: Sia Jee Heng To: , , , , , , CC: , , , Subject: [PATCH 7/7] riscv: dts: starfive: Add initial StarFive JH8100 device tree Date: Mon, 27 Nov 2023 09:36:02 +0800 Message-ID: <20231127013602.253835-8-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> References: <20231127013602.253835-1-jeeheng.sia@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [202.188.176.82] X-ClientProxiedBy: EXCAS066.cuchost.com (172.16.6.26) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add initial device tree for the StarFive JH8100 RISC-V SoC Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- arch/riscv/boot/dts/starfive/Makefile | 1 + arch/riscv/boot/dts/starfive/jh8100-evb.dts | 42 +++ arch/riscv/boot/dts/starfive/jh8100.dtsi | 365 ++++++++++++++++++++ 3 files changed, 408 insertions(+) create mode 100644 arch/riscv/boot/dts/starfive/jh8100-evb.dts create mode 100644 arch/riscv/boot/dts/starfive/jh8100.dtsi diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/st= arfive/Makefile index 0141504c0f5c..fbb0dc619102 100644 --- a/arch/riscv/boot/dts/starfive/Makefile +++ b/arch/riscv/boot/dts/starfive/Makefile @@ -10,3 +10,4 @@ dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7100-starfive-visionfi= ve-v1.dtb =20 dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.2a.dtb dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh7110-starfive-visionfive-2-v1.3b.dtb +dtb-$(CONFIG_ARCH_STARFIVE) +=3D jh8100-evb.dtb diff --git a/arch/riscv/boot/dts/starfive/jh8100-evb.dts b/arch/riscv/boot/= dts/starfive/jh8100-evb.dts new file mode 100644 index 000000000000..67c4964a8773 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100-evb.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +#include "jh8100.dtsi" + +/ { + model =3D "StarFive JH8100 EVB"; + compatible =3D "starfive,jh8100-evb", "starfive,jh8100"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + cpus { + timebase-frequency =3D <4000000>; + + }; + + memory { + device_type =3D "memory"; + reg =3D <0x0 0x40000000 0x2 0x00000000>; /* 8GB */ + }; + + soc { + clk_uart: clk_uart { + compatible =3D "fixed-clock"; /* Initial clock handler for UART */ + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + }; +}; + +&uart0 { + status =3D "okay"; + clocks =3D <&clk_uart>, <&clk_uart>; +}; diff --git a/arch/riscv/boot/dts/starfive/jh8100.dtsi b/arch/riscv/boot/dts= /starfive/jh8100.dtsi new file mode 100644 index 000000000000..1b338d4cb985 --- /dev/null +++ b/arch/riscv/boot/dts/starfive/jh8100.dtsi @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (c) 2021-2023 StarFive Technology Co., Ltd. + */ + +/dts-v1/; + +/ { + compatible =3D "starfive,jh8100"; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz =3D <768>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <512>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c0>; + reg =3D <0x0>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu0_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu1: cpu@1 { + compatible =3D "starfive,dubhe-80", "riscv"; + capacity-dmips-mhz =3D <768>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <512>; + d-cache-size =3D <32768>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <512>; + i-cache-size =3D <32768>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c1>; + reg =3D <0x1>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu1_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu2: cpu@2 { + compatible =3D "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz =3D <1024>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <1024>; + d-cache-size =3D <65536>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <1024>; + i-cache-size =3D <65536>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + reg =3D <0x2>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu2_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu3: cpu@3 { + compatible =3D "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz =3D <1024>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <1024>; + d-cache-size =3D <65536>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <1024>; + i-cache-size =3D <65536>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + reg =3D <0x3>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu3_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu4: cpu@4 { + compatible =3D "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz =3D <1024>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <1024>; + d-cache-size =3D <65536>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <1024>; + i-cache-size =3D <65536>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + reg =3D <0x4>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu4_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu5: cpu@5 { + compatible =3D "starfive,dubhe-90", "riscv"; + capacity-dmips-mhz =3D <1024>; + d-cache-block-size =3D <64>; + d-cache-sets =3D <1024>; + d-cache-size =3D <65536>; + d-tlb-sets =3D <1>; + d-tlb-size =3D <48>; + device_type =3D "cpu"; + i-cache-block-size =3D <64>; + i-cache-sets =3D <1024>; + i-cache-size =3D <65536>; + i-tlb-sets =3D <1>; + i-tlb-size =3D <48>; + mmu-type =3D "riscv,sv48"; + next-level-cache =3D <&l2c2>; + reg =3D <0x5>; + riscv,isa =3D "rv64imafdch"; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "h", "zicntr", + "zicsr", "zifencei", "zihintpause", "zihpm", + "zba", "zbb", "zbs", "sscofpmf"; + tlb-split; + + cpu5_intc: interrupt-controller { + compatible =3D "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells =3D <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu1>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu2>; + }; + + core1 { + cpu =3D <&cpu3>; + }; + + core2 { + cpu =3D <&cpu4>; + }; + + core3 { + cpu =3D <&cpu5>; + }; + }; + }; + + l2c0: cache-controller-0 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <512>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2c1: cache-controller-1 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <512>; + cache-size =3D <0x40000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l2c2: cache-controller-2{ + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <4096>; + cache-size =3D <0x200000>; + cache-unified; + next-level-cache =3D <&l3_cache>; + }; + + l3_cache: cache-controller-3 { + compatible =3D "cache"; + cache-block-size =3D <64>; + cache-level =3D <3>; + cache-sets =3D <8192>; + cache-size =3D <0x400000>; + cache-unified; + }; + }; + + soc { + compatible =3D "simple-bus"; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + clint: clint@2000000 { + compatible =3D "starfive,jh8100-clint", "sifive,clint0"; + reg =3D <0x0 0x2000000 0x0 0x10000>; + interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>, + <&cpu5_intc 3>, <&cpu5_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells =3D <1>; + #address-cells =3D <0>; + compatible =3D "starfive,jh8100-plic", "sifive,plic-1.0.0"; + reg =3D <0x0 0x0c000000 0x0 0x4000000>; + riscv,ndev =3D <200>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu1_intc 11>, + <&cpu0_intc 9>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu3_intc 11>, + <&cpu4_intc 11>, <&cpu5_intc 11>, + <&cpu2_intc 9>, <&cpu3_intc 9>, + <&cpu4_intc 9>, <&cpu5_intc 9>; + }; + + uart0: serial@12160000 { + compatible =3D "starfive,jh8100-uart"; + reg =3D <0x0 0x12160000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + interrupts =3D <67>; + status =3D "disabled"; + }; + + uart1: serial@12170000 { + compatible =3D "starfive,jh8100-uart"; + reg =3D <0x0 0x12170000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + interrupts =3D <68>; + status =3D "disabled"; + }; + + uart2: serial@12180000 { + compatible =3D "starfive,jh8100-uart"; + reg =3D <0x0 0x12180000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + interrupts =3D <69>; + status =3D "disabled"; + }; + + uart3: serial@12190000 { + compatible =3D "starfive,jh8100-uart"; + reg =3D <0x0 0x12190000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + interrupts =3D <70>; + status =3D "disabled"; + }; + + uart4: serial@121a0000 { + compatible =3D "starfive,jh8100-uart"; + reg =3D <0x0 0x121a0000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + interrupts =3D <71>; + status =3D "disabled"; + }; + + uart5: serial@127d0000 { + compatible =3D "starfive,jh8100-uart"; + reg =3D <0x0 0x127d0000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + interrupts =3D <72>; + status =3D "disabled"; + }; + + uart6: serial@127e0000 { + compatible =3D "starfive,jh8100-uart"; + reg =3D <0x0 0x127e0000 0x0 0x10000>; + clock-names =3D "uart_clk", "pclk"; + interrupts =3D <73>; + status =3D "disabled"; + }; + + }; +}; --=20 2.34.1