From nobody Wed Dec 17 12:45:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 685B6C4167B for ; Mon, 27 Nov 2023 15:51:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234075AbjK0PvM (ORCPT ); Mon, 27 Nov 2023 10:51:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234066AbjK0PvB (ORCPT ); Mon, 27 Nov 2023 10:51:01 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36ABC19B for ; Mon, 27 Nov 2023 07:51:06 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-50aa8c0af41so5465430e87.1 for ; Mon, 27 Nov 2023 07:51:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701100264; x=1701705064; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=al9lFOlydTk3/Cb0OzlDFOlBidTusAIuSqJUpsvOncU=; b=Fenems54IJS3L6xsI1VYvQbJmk3XkUBVk5wF3NBHxYO27wedCDBwW+mXpo0223DM5B gJTaxzmJelBGgxQ2guCoclBNxUE+TRUXGoOsDMt2ybECfwCRQ0QIDC1v5j5ehnN/M8Bc PJbJHlf38+k4Ng7bgqhWkgQnEIf90IAbPjvqTXG2JmC93grBx+wSSlVztPf8Bg+U5hlL 8UCal6dmVZEBEZ4NPt/nobh626aP4QZvM+vM5wBIftaLCqooybFhIKT7XiRgNyogCUh3 Bx+VIvGE+HKiiK/Mj+M1ELOjPADmd+NDi7BKblsJtNgE8xJCkUxdMroeI34ZiAo9EUdZ Yb/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701100264; x=1701705064; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=al9lFOlydTk3/Cb0OzlDFOlBidTusAIuSqJUpsvOncU=; b=aLMPff3CKJ7hA9r3uQSQ6A1Xo0Pv9EDcY1yRji4jH6/1VHfgTcJ+a3egHQc4IIJHUK PNlEY7xbD6BRadQ6Ia2DBpNsMthFslNRt323G9dLfuTYDME5mq948zGQxNgS5oKpFM7r NwG6+yAnjZO8gDEpe0Mz+sgrJyNU+8rl0fpq4eBrJ0Xgm1tweezHwN5xaaU6i2LXlxo5 B5rI5IB3XN3JPf0O20307ZE2vymeSNJoCcu0P9lOACBei/LAHpB/b7G2NoPxqL60APh+ KF4AZG/V1tVUkyCKYZC5CmZ408ulGScQzHDRFrFfmN1LW3O8v0f8Zz7Njaw6MBbLTdjc rTdg== X-Gm-Message-State: AOJu0YyJokne9n4FOEALKnLIUbuFnbVYEUF2TxymV/mPWwfxCTnH5GWi 6C0XkR5usb/nOqrfKd6MYYYfsw== X-Google-Smtp-Source: AGHT+IENgdo6qOry7ehcllNmYeRTDO9MRi8GdqIZlB8DceVOm/g6uE+I18gI1O9zNUyQoEZAf8nCnQ== X-Received: by 2002:a19:8c42:0:b0:503:2879:567 with SMTP id i2-20020a198c42000000b0050328790567mr2713512lfj.28.1701100264455; Mon, 27 Nov 2023 07:51:04 -0800 (PST) Received: from [127.0.1.1] ([85.235.12.238]) by smtp.gmail.com with ESMTPSA id b16-20020ac25e90000000b0050a71df5d39sm1515787lfq.300.2023.11.27.07.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Nov 2023 07:51:03 -0800 (PST) From: Linus Walleij Date: Mon, 27 Nov 2023 16:51:01 +0100 Subject: [PATCH v9 2/3] ARM64: dts: marvell: Fix some common switch mistakes MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231127-mv88e6xxx-mvebu-fixes-v9-2-d19b963e81fb@linaro.org> References: <20231127-mv88e6xxx-mvebu-fixes-v9-0-d19b963e81fb@linaro.org> In-Reply-To: <20231127-mv88e6xxx-mvebu-fixes-v9-0-d19b963e81fb@linaro.org> To: Andrew Lunn , Gregory Clement , Sebastian Hesselbarth , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Russell King Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Linus Walleij , Florian Fainelli X-Mailer: b4 0.12.4 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Fix some errors in the Marvell MV88E6xxx switch descriptions: - The top node had no address size or cells. - switch0@0 is not OK, should be ethernet-switch@0. - ports should be ethernet-ports - port@0 should be ethernet-port@0 - PHYs should be named ethernet-phy@ Reviewed-by: Andrew Lunn Reviewed-by: Florian Fainelli Signed-off-by: Linus Walleij --- .../dts/marvell/armada-3720-espressobin-ultra.dts | 14 ++-- .../boot/dts/marvell/armada-3720-espressobin.dtsi | 20 +++-- .../boot/dts/marvell/armada-3720-gl-mv1000.dts | 20 +++-- .../boot/dts/marvell/armada-3720-turris-mox.dts | 85 ++++++++++++------= ---- .../boot/dts/marvell/armada-7040-mochabin.dts | 24 +++--- .../dts/marvell/armada-8040-clearfog-gt-8k.dts | 22 +++--- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 42 +++++------ 7 files changed, 115 insertions(+), 112 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts = b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index f9abef8dcc94..870bb380a40a 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -126,32 +126,32 @@ &switch0 { =20 reset-gpios =3D <&gpiosb 23 GPIO_ACTIVE_LOW>; =20 - ports { - switch0port1: port@1 { + ethernet-ports { + switch0port1: ethernet-port@1 { reg =3D <1>; label =3D "lan0"; phy-handle =3D <&switch0phy0>; }; =20 - switch0port2: port@2 { + switch0port2: ethernet-port@2 { reg =3D <2>; label =3D "lan1"; phy-handle =3D <&switch0phy1>; }; =20 - switch0port3: port@3 { + switch0port3: ethernet-port@3 { reg =3D <3>; label =3D "lan2"; phy-handle =3D <&switch0phy2>; }; =20 - switch0port4: port@4 { + switch0port4: ethernet-port@4 { reg =3D <4>; label =3D "lan3"; phy-handle =3D <&switch0phy3>; }; =20 - switch0port5: port@5 { + switch0port5: ethernet-port@5 { reg =3D <5>; label =3D "wan"; phy-handle =3D <&extphy>; @@ -160,7 +160,7 @@ switch0port5: port@5 { }; =20 mdio { - switch0phy3: switch0phy3@14 { + switch0phy3: ethernet-phy@14 { reg =3D <0x14>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arc= h/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index 49cbdb55b4b3..fed2dcecb323 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -145,19 +145,17 @@ &usb2 { }; =20 &mdio { - switch0: switch0@1 { + switch0: ethernet-switch@1 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <1>; =20 dsa,member =3D <0 0>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0port0: port@0 { + switch0port0: ethernet-port@0 { reg =3D <0>; label =3D "cpu"; ethernet =3D <ð0>; @@ -168,19 +166,19 @@ fixed-link { }; }; =20 - switch0port1: port@1 { + switch0port1: ethernet-port@1 { reg =3D <1>; label =3D "wan"; phy-handle =3D <&switch0phy0>; }; =20 - switch0port2: port@2 { + switch0port2: ethernet-port@2 { reg =3D <2>; label =3D "lan0"; phy-handle =3D <&switch0phy1>; }; =20 - switch0port3: port@3 { + switch0port3: ethernet-port@3 { reg =3D <3>; label =3D "lan1"; phy-handle =3D <&switch0phy2>; @@ -192,13 +190,13 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg =3D <0x11>; }; - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg =3D <0x12>; }; - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg =3D <0x13>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts b/arch/a= rm64/boot/dts/marvell/armada-3720-gl-mv1000.dts index b1b45b4fa9d4..63fbc8352161 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts @@ -152,31 +152,29 @@ &uart0 { }; =20 &mdio { - switch0: switch0@1 { + switch0: ethernet-switch@1 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <1>; =20 dsa,member =3D <0 0>; =20 - ports: ports { + ports: ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@0 { + ethernet-port@0 { reg =3D <0>; label =3D "cpu"; ethernet =3D <ð0>; }; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "wan"; phy-handle =3D <&switch0phy0>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan0"; phy-handle =3D <&switch0phy1>; @@ -185,7 +183,7 @@ port@2 { nvmem-cell-names =3D "mac-address"; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan1"; phy-handle =3D <&switch0phy2>; @@ -199,13 +197,13 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg =3D <0x11>; }; - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg =3D <0x12>; }; - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg =3D <0x13>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/= arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 9eab2bb22134..66cd98b67744 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -304,7 +304,13 @@ phy1: ethernet-phy@1 { reg =3D <1>; }; =20 - /* switch nodes are enabled by U-Boot if modules are present */ + /* + * NOTE: switch nodes are enabled by U-Boot if modules are present + * DO NOT change this node name (switch0@10) even if it is not following + * conventions! Deployed U-Boot binaries are explicitly looking for + * this node in order to augment the device tree! + * Also do not touch the "ports" or "port@n" nodes. These are also ABI. + */ switch0@10 { compatible =3D "marvell,mv88e6190"; reg =3D <0x10>; @@ -317,35 +323,35 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy1: switch0phy1@1 { + switch0phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch0phy2: switch0phy2@2 { + switch0phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch0phy3: switch0phy3@3 { + switch0phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch0phy4: switch0phy4@4 { + switch0phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch0phy5: switch0phy5@5 { + switch0phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch0phy6: switch0phy6@6 { + switch0phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch0phy7: switch0phy7@7 { + switch0phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch0phy8: switch0phy8@8 { + switch0phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; @@ -430,6 +436,7 @@ port-sfp@a { }; }; =20 + /* NOTE: this node name is ABI, don't change it! */ switch0@2 { compatible =3D "marvell,mv88e6085"; reg =3D <0x2>; @@ -442,19 +449,19 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy1_topaz: switch0phy1@11 { + switch0phy1_topaz: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch0phy2_topaz: switch0phy2@12 { + switch0phy2_topaz: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch0phy3_topaz: switch0phy3@13 { + switch0phy3_topaz: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch0phy4_topaz: switch0phy4@14 { + switch0phy4_topaz: ethernet-phy@14 { reg =3D <0x14>; }; }; @@ -497,6 +504,7 @@ port@5 { }; }; =20 + /* NOTE: this node name is ABI, don't change it! */ switch1@11 { compatible =3D "marvell,mv88e6190"; reg =3D <0x11>; @@ -509,35 +517,35 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch1phy1: switch1phy1@1 { + switch1phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch1phy2: switch1phy2@2 { + switch1phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch1phy3: switch1phy3@3 { + switch1phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch1phy4: switch1phy4@4 { + switch1phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch1phy5: switch1phy5@5 { + switch1phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch1phy6: switch1phy6@6 { + switch1phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch1phy7: switch1phy7@7 { + switch1phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch1phy8: switch1phy8@8 { + switch1phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; @@ -622,6 +630,7 @@ port-sfp@a { }; }; =20 + /* NOTE: this node name is ABI, don't change it! */ switch1@2 { compatible =3D "marvell,mv88e6085"; reg =3D <0x2>; @@ -634,19 +643,19 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch1phy1_topaz: switch1phy1@11 { + switch1phy1_topaz: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch1phy2_topaz: switch1phy2@12 { + switch1phy2_topaz: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch1phy3_topaz: switch1phy3@13 { + switch1phy3_topaz: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch1phy4_topaz: switch1phy4@14 { + switch1phy4_topaz: ethernet-phy@14 { reg =3D <0x14>; }; }; @@ -689,6 +698,7 @@ port@5 { }; }; =20 + /* NOTE: this node name is ABI, don't change it! */ switch2@12 { compatible =3D "marvell,mv88e6190"; reg =3D <0x12>; @@ -701,35 +711,35 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch2phy1: switch2phy1@1 { + switch2phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch2phy2: switch2phy2@2 { + switch2phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch2phy3: switch2phy3@3 { + switch2phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch2phy4: switch2phy4@4 { + switch2phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch2phy5: switch2phy5@5 { + switch2phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch2phy6: switch2phy6@6 { + switch2phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch2phy7: switch2phy7@7 { + switch2phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch2phy8: switch2phy8@8 { + switch2phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; @@ -805,6 +815,7 @@ port-sfp@a { }; }; =20 + /* NOTE: this node name is ABI, don't change it! */ switch2@2 { compatible =3D "marvell,mv88e6085"; reg =3D <0x2>; @@ -817,19 +828,19 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch2phy1_topaz: switch2phy1@11 { + switch2phy1_topaz: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch2phy2_topaz: switch2phy2@12 { + switch2phy2_topaz: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch2phy3_topaz: switch2phy3@13 { + switch2phy3_topaz: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch2phy4_topaz: switch2phy4@14 { + switch2phy4_topaz: ethernet-phy@14 { reg =3D <0x14>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/ar= m64/boot/dts/marvell/armada-7040-mochabin.dts index 48202810bf78..40b7ee7ead72 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -301,10 +301,8 @@ eth2phy: ethernet-phy@1 { }; =20 /* 88E6141 Topaz switch */ - switch: switch@3 { + switch: ethernet-switch@3 { compatible =3D "marvell,mv88e6085"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <3>; =20 pinctrl-names =3D "default"; @@ -314,35 +312,35 @@ switch: switch@3 { interrupt-parent =3D <&cp0_gpio1>; interrupts =3D <1 IRQ_TYPE_LEVEL_LOW>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - swport1: port@1 { + swport1: ethernet-port@1 { reg =3D <1>; label =3D "lan0"; phy-handle =3D <&swphy1>; }; =20 - swport2: port@2 { + swport2: ethernet-port@2 { reg =3D <2>; label =3D "lan1"; phy-handle =3D <&swphy2>; }; =20 - swport3: port@3 { + swport3: ethernet-port@3 { reg =3D <3>; label =3D "lan2"; phy-handle =3D <&swphy3>; }; =20 - swport4: port@4 { + swport4: ethernet-port@4 { reg =3D <4>; label =3D "lan3"; phy-handle =3D <&swphy4>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "cpu"; ethernet =3D <&cp0_eth1>; @@ -355,19 +353,19 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - swphy1: swphy1@17 { + swphy1: ethernet-phy@17 { reg =3D <17>; }; =20 - swphy2: swphy2@18 { + swphy2: ethernet-phy@18 { reg =3D <18>; }; =20 - swphy3: swphy3@19 { + swphy3: ethernet-phy@19 { reg =3D <19>; }; =20 - swphy4: swphy4@20 { + swphy4: ethernet-phy@20 { reg =3D <20>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/a= rch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 4125202028c8..67892f0d2863 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -497,42 +497,42 @@ ge_phy: ethernet-phy@0 { reset-deassert-us =3D <10000>; }; =20 - switch0: switch0@4 { + switch0: ethernet-switch@4 { compatible =3D "marvell,mv88e6085"; reg =3D <4>; pinctrl-names =3D "default"; pinctrl-0 =3D <&cp1_switch_reset_pins>; reset-gpios =3D <&cp1_gpio1 24 GPIO_ACTIVE_LOW>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "lan2"; phy-handle =3D <&switch0phy0>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "lan1"; phy-handle =3D <&switch0phy1>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "lan4"; phy-handle =3D <&switch0phy2>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "lan3"; phy-handle =3D <&switch0phy3>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "cpu"; ethernet =3D <&cp1_eth2>; @@ -545,19 +545,19 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy0: switch0phy0@11 { + switch0phy0: ethernet-phy@11 { reg =3D <0x11>; }; =20 - switch0phy1: switch0phy1@12 { + switch0phy1: ethernet-phy@12 { reg =3D <0x12>; }; =20 - switch0phy2: switch0phy2@13 { + switch0phy2: ethernet-phy@13 { reg =3D <0x13>; }; =20 - switch0phy3: switch0phy3@14 { + switch0phy3: ethernet-phy@14 { reg =3D <0x14>; }; }; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/= dts/marvell/cn9130-crb.dtsi index 47d45ff3d6f5..6fcc34f7b464 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -207,11 +207,9 @@ phy0: ethernet-phy@0 { reg =3D <0>; }; =20 - switch6: switch0@6 { + switch6: ethernet-switch@6 { /* Actual device is MV88E6393X */ compatible =3D "marvell,mv88e6190"; - #address-cells =3D <1>; - #size-cells =3D <0>; reg =3D <6>; interrupt-parent =3D <&cp0_gpio1>; interrupts =3D <28 IRQ_TYPE_LEVEL_LOW>; @@ -220,59 +218,59 @@ switch6: switch0@6 { =20 dsa,member =3D <0 0>; =20 - ports { + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; =20 - port@1 { + ethernet-port@1 { reg =3D <1>; label =3D "p1"; phy-handle =3D <&switch0phy1>; }; =20 - port@2 { + ethernet-port@2 { reg =3D <2>; label =3D "p2"; phy-handle =3D <&switch0phy2>; }; =20 - port@3 { + ethernet-port@3 { reg =3D <3>; label =3D "p3"; phy-handle =3D <&switch0phy3>; }; =20 - port@4 { + ethernet-port@4 { reg =3D <4>; label =3D "p4"; phy-handle =3D <&switch0phy4>; }; =20 - port@5 { + ethernet-port@5 { reg =3D <5>; label =3D "p5"; phy-handle =3D <&switch0phy5>; }; =20 - port@6 { + ethernet-port@6 { reg =3D <6>; label =3D "p6"; phy-handle =3D <&switch0phy6>; }; =20 - port@7 { + ethernet-port@7 { reg =3D <7>; label =3D "p7"; phy-handle =3D <&switch0phy7>; }; =20 - port@8 { + ethernet-port@8 { reg =3D <8>; label =3D "p8"; phy-handle =3D <&switch0phy8>; }; =20 - port@9 { + ethernet-port@9 { reg =3D <9>; label =3D "p9"; phy-mode =3D "10gbase-r"; @@ -280,7 +278,7 @@ port@9 { managed =3D "in-band-status"; }; =20 - port@a { + ethernet-port@a { reg =3D <10>; ethernet =3D <&cp0_eth0>; phy-mode =3D "10gbase-r"; @@ -293,35 +291,35 @@ mdio { #address-cells =3D <1>; #size-cells =3D <0>; =20 - switch0phy1: switch0phy1@1 { + switch0phy1: ethernet-phy@1 { reg =3D <0x1>; }; =20 - switch0phy2: switch0phy2@2 { + switch0phy2: ethernet-phy@2 { reg =3D <0x2>; }; =20 - switch0phy3: switch0phy3@3 { + switch0phy3: ethernet-phy@3 { reg =3D <0x3>; }; =20 - switch0phy4: switch0phy4@4 { + switch0phy4: ethernet-phy@4 { reg =3D <0x4>; }; =20 - switch0phy5: switch0phy5@5 { + switch0phy5: ethernet-phy@5 { reg =3D <0x5>; }; =20 - switch0phy6: switch0phy6@6 { + switch0phy6: ethernet-phy@6 { reg =3D <0x6>; }; =20 - switch0phy7: switch0phy7@7 { + switch0phy7: ethernet-phy@7 { reg =3D <0x7>; }; =20 - switch0phy8: switch0phy8@8 { + switch0phy8: ethernet-phy@8 { reg =3D <0x8>; }; }; --=20 2.34.1