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([80.71.140.73]) by smtp.gmail.com with ESMTPSA id y10-20020a170902b48a00b001cfb52ebffesm3123853plr.147.2023.11.26.15.28.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 15:28:24 -0800 (PST) From: Emil Renner Berthing To: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Paul Walmsley , Palmer Dabbelt , Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Cristian Ciocaltea Subject: [PATCH v1 4/8] riscv: dts: starfive: Add JH7100 cache controller Date: Mon, 27 Nov 2023 00:27:42 +0100 Message-Id: <20231126232746.264302-5-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231126232746.264302-1-emil.renner.berthing@canonical.com> References: <20231126232746.264302-1-emil.renner.berthing@canonical.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The StarFive JH7100 SoC also features the SiFive L2 cache controller. This SoC has non-coherent DMAs, but predate the RISC-V Zicbom extension, so we need the sifive,cache-ops property to use the cache controller for cache flushing operations instead. Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/starfive/jh7100.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts= /starfive/jh7100.dtsi index 7c1009428c1f..0cafac437746 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -32,6 +32,7 @@ U74_0: cpu@0 { i-tlb-sets =3D <1>; i-tlb-size =3D <32>; mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&ccache>; riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", @@ -60,6 +61,7 @@ U74_1: cpu@1 { i-tlb-sets =3D <1>; i-tlb-size =3D <32>; mmu-type =3D "riscv,sv39"; + next-level-cache =3D <&ccache>; riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", @@ -154,6 +156,17 @@ clint: clint@2000000 { <&cpu1_intc 3>, <&cpu1_intc 7>; }; =20 + ccache: cache-controller@2010000 { + compatible =3D "starfive,jh7100-ccache", "sifive,ccache0", "cache"; + reg =3D <0x0 0x2010000 0x0 0x1000>; + interrupts =3D <128>, <130>, <131>, <129>; + cache-block-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <2097152>; + cache-unified; + }; + plic: interrupt-controller@c000000 { compatible =3D "starfive,jh7100-plic", "sifive,plic-1.0.0"; reg =3D <0x0 0xc000000 0x0 0x4000000>; --=20 2.40.1