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[95.244.100.54]) by smtp.gmail.com with ESMTPSA id h24-20020a170906591800b009fdc684a79esm4656158ejq.124.2023.11.26.07.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Nov 2023 07:46:58 -0800 (PST) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Amarula patchwork , michael@amarulasolutions.com, Dario Binacchi , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , NXP Linux Team , Peng Fan , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 11/11] arm64: dts: imx8mn-bsh-smm-s2/pro: add display setup Date: Sun, 26 Nov 2023 16:45:03 +0100 Message-ID: <20231126154605.15767-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231126154605.15767-1-dario.binacchi@amarulasolutions.com> References: <20231126154605.15767-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Michael Trimarchi Add the display and nodes required for its operation. Signed-off-by: Michael Trimarchi Signed-off-by: Dario Binacchi --- Changes in v2: - Adjust the mipi_dsi node based on the latest patches merged into the mainline in the dtsi files it includes. - Added to the series the following patches: - 0001 drm/bridge: Fix bridge disable logic - 0002 drm/bridge: Fix a use case in the bridge disable logic - 0003 samsung-dsim: enter display mode in the enable() callback - 0004 drm: bridge: samsung-dsim: complete the CLKLANE_STOP setting .../freescale/imx8mn-bsh-smm-s2-common.dtsi | 1 + .../freescale/imx8mn-bsh-smm-s2-display.dtsi | 121 ++++++++++++++++++ 2 files changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display= .dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/= arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi index 22a754d438f1..bbb07c650da9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -7,6 +7,7 @@ /dts-v1/; =20 #include "imx8mn.dtsi" +#include "imx8mn-bsh-smm-s2-display.dtsi" =20 / { chosen { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi b= /arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi new file mode 100644 index 000000000000..08f173b15495 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 BSH + */ + +/ { + backlight: backlight { + compatible =3D "pwm-backlight"; + pwms =3D <&pwm1 0 700000 0>; /* 700000 ns =3D 1337Hz */ + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <50>; + status =3D "okay"; + }; + + reg_3v3_dvdd: regulator-3v3-O3 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_dvdd>; + regulator-name =3D "3v3-dvdd-supply"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + reg_v3v3_avdd: regulator-3v3-O2 { + compatible =3D "regulator-fixed"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_avdd>; + regulator-name =3D "3v3-avdd-supply"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + gpio =3D <&gpio1 5 GPIO_ACTIVE_LOW>; + }; +}; + +&pwm1 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_bl>; +}; + +&lcdif { + status =3D "okay"; + assigned-clocks =3D <&clk IMX8MN_VIDEO_PLL1>; + assigned-clock-rates =3D <594000000>; +}; + +&pgc_dispmix { + assigned-clocks =3D <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB= >; + assigned-clock-parents =3D <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS= _PLL1_800M>; + assigned-clock-rates =3D <500000000>, <200000000>; +}; + +&mipi_dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + samsung,esc-clock-frequency =3D <20000000>; + samsung,pll-clock-frequency =3D <12000000>; + + panel@0 { + compatible =3D "sharp,ls068b3sx02", "synaptics,r63353"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_panel>; + reg =3D <0>; + + backlight =3D <&backlight>; + dvdd-supply =3D <®_3v3_dvdd>; + avdd-supply =3D <®_v3v3_avdd>; + reset-gpios =3D <&gpio4 29 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mipi_dsi_out>; + }; + }; + + }; + + ports { + port@1 { + reg =3D <1>; + mipi_dsi_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; +}; + +&gpu { + status =3D "okay"; +}; + +&iomuxc { + + /* This is for both PWM and voltage regulators for display */ + pinctrl_bl: pwm1grp { + fsl,pins =3D < + MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins =3D < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */ + >; + }; + + pinctrl_dvdd: dvddgrp { + fsl,pins =3D < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */ + >; + }; + + pinctrl_avdd: avddgrp { + fsl,pins =3D < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */ + >; + }; +}; --=20 2.42.0