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([79.115.63.75]) by smtp.gmail.com with ESMTPSA id lv23-20020a170906bc9700b009f28db2b702sm3390163ejb.209.2023.11.25.04.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 04:35:51 -0800 (PST) From: Tudor Ambarus To: pratyush@kernel.org, michael@walle.cc, fastevam@denx.de Cc: linux-mtd@lists.infradead.org, takahiro.kuwano@infineon.com, bacem.daassi@infineon.com, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 4/5] mtd: spi-nor: remove NO_CHIP_ERASE flag Date: Sat, 25 Nov 2023 14:35:28 +0200 Message-Id: <20231125123529.55686-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231125123529.55686-1-tudor.ambarus@linaro.org> References: <20231125123529.55686-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1896; i=tudor.ambarus@linaro.org; h=from:subject; bh=CCp3s597dd2N34pcvWqlxQ50V8OYh2tnaQCvSzFKDOc=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlYeoRHtkHuEy/gG4P7KkUgLRNHmTbUGbxJBrYu JpjuIMIeFqJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZWHqEQAKCRBLVU9HpY0U 6U8EB/4isL9ZPOAlY3kE68x1LosSOh7Ai80yt+wDjJVDB5heW0xOuYMbkEfIwfpIYuDCHR+GYnd XgA5CiKFrqLiHwBMwRJWKYVHby+AfwdlgJ1D8m+gCeW/8a1KAeBHGDYm3Wt85AoEV+yiFFvDEV+ b+PQX+WSWDVPCX9DrygJ+S5Wy5ddhid7ZoZXrrI84jOjOgC50BUQqEiCRoMLN3GI/L6WSvCeHgp 827qSsTa2taSWG8HocFv0Q/I257SwmQzNUJxGEUPTL8drbtu6if3yd49etgNoooeQiVn/hfS7zK iDgH8EbbhaZDpYO9+qKUoKhnFSDuV2LhYd3AD6zPqPXutGN6 X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There's no flash using it and we'd like to rely instead on SFDP data, thus remove it. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 --- drivers/mtd/spi-nor/core.h | 8 +++----- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 52e5b569ddfd..503fed90c2fa 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2888,9 +2888,6 @@ static void spi_nor_init_flags(struct spi_nor *nor) nor->flags |=3D SNOR_F_HAS_SR_BP3_BIT6; } =20 - if (flags & NO_CHIP_ERASE) - nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE; - if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && !nor->controller_ops) nor->flags |=3D SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index b43ea2d49e74..29ed67725b18 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -489,7 +489,6 @@ struct spi_nor_id { * Usually these will power-up in a write-prote= cted * state. * SPI_NOR_NO_ERASE: no erase command needed. - * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. @@ -539,10 +538,9 @@ struct flash_info { #define SPI_NOR_BP3_SR_BIT6 BIT(4) #define SPI_NOR_SWP_IS_VOLATILE BIT(5) #define SPI_NOR_NO_ERASE BIT(6) -#define NO_CHIP_ERASE BIT(7) -#define SPI_NOR_NO_FR BIT(8) -#define SPI_NOR_QUAD_PP BIT(9) -#define SPI_NOR_RWW BIT(10) +#define SPI_NOR_NO_FR BIT(7) +#define SPI_NOR_QUAD_PP BIT(8) +#define SPI_NOR_RWW BIT(9) =20 u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) --=20 2.34.1