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([79.115.63.75]) by smtp.gmail.com with ESMTPSA id lv23-20020a170906bc9700b009f28db2b702sm3390163ejb.209.2023.11.25.04.35.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 04:35:43 -0800 (PST) From: Tudor Ambarus To: pratyush@kernel.org, michael@walle.cc, fastevam@denx.de Cc: linux-mtd@lists.infradead.org, takahiro.kuwano@infineon.com, bacem.daassi@infineon.com, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 1/5] mtd: spi-nor: add erase die (chip) capability Date: Sat, 25 Nov 2023 14:35:25 +0200 Message-Id: <20231125123529.55686-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231125123529.55686-1-tudor.ambarus@linaro.org> References: <20231125123529.55686-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=8121; i=tudor.ambarus@linaro.org; h=from:subject; bh=uU48oE12zCECngrtZ3sUBC2BQtjDfvVFXHi6d9CaOqQ=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlYeoQhHeDSJc4wiPTk6XJTim0AsXkv6rjkK0Cp YDgSMagl5KJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZWHqEAAKCRBLVU9HpY0U 6eCHCACrxWZqJGEc+n/OAVwbhdvsO1HgFyeZOf1qnlAeawV/pFBqiN8ur0ubOchAOvmGC1GoZY3 ekciT8gDpgHU5yGQek3Zkz0aS4gWQG91a7Xy7Pmr/SLSV49mciQTWe8c7S4GbKWIiDk3PshiyJV ymrVUoQIN2+qRJS4DDPzeljInD2YjGoWSNc3xRbStozqffIymYNv0uhj++jUnBIXPAXzp9H9fiS NYt36qSTZTGJtZlNxda+oaR9B351q6ssUkaAAC2fi8rdXEjsoNjq70IMGQU2qKjSl1sp6IZJsQ9 ai8WEzvGWc9DbTVLwqYDR4OzyRGR/7gIcr1MwYZHo0pTgzS3 X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" JESD216 mentions die erase, but does not provide an opcode for it. Check BFPT dword 11, bits 30:24, "Chip Erase, Typical time", it says: "Typical time to erase one chip (die). User must poll device busy to determine if the operation has completed. For a device consisting of multiple dies, that are individually accessed, the time is for each die to which a chip erase command is applied." So when a flash consists of a single die, this is the erase time for the full chip (die) erase, and when it consists of multiple dies, it's the die erase time. Chip and die are the same thing. Add support for die erase. For now, benefit of the die erase when addr and len are aligned with die size. This could be improved however for the uniform and non-uniform erases cases to use the die erase when possible. For example if one requests that an erase of a 2 die device starting from the last 64KB of the first die to the end of the flash size, we could use just 2 commands, a 64KB erase and a die erase. This improvement is left as an exercise for the reader. Signed-off-by: Tudor Ambarus Tested-by: Fabio Estevam --- drivers/mtd/spi-nor/core.c | 108 +++++++++++++++++++++++----------- drivers/mtd/spi-nor/core.h | 8 ++- drivers/mtd/spi-nor/debugfs.c | 2 +- 3 files changed, 81 insertions(+), 37 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 25a64c65717d..479494cf00c9 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -1060,24 +1060,32 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8= *sr2) } =20 /** - * spi_nor_erase_chip() - Erase the entire flash memory. + * spi_nor_erase_die() - Erase the entire die. * @nor: pointer to 'struct spi_nor'. + * @addr: address of the die. + * @die_size: size of the die. * * Return: 0 on success, -errno otherwise. */ -static int spi_nor_erase_chip(struct spi_nor *nor) +static int spi_nor_erase_die(struct spi_nor *nor, loff_t addr, size_t die_= size) { + bool multi_die =3D nor->mtd.size !=3D die_size; int ret; =20 - dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10)); + dev_dbg(nor->dev, " %lldKiB\n", (long long)(die_size >> 10)); =20 if (nor->spimem) { - struct spi_mem_op op =3D SPI_NOR_CHIP_ERASE_OP; + struct spi_mem_op op =3D + SPI_NOR_DIE_ERASE_OP(nor->params->die_erase_opcode, + nor->addr_nbytes, addr, multi_die); =20 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); =20 ret =3D spi_mem_exec_op(nor->spimem, &op); } else { + if (multi_die) + return -EOPNOTSUPP; + ret =3D spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0); @@ -1792,6 +1800,51 @@ static int spi_nor_erase_multi_sectors(struct spi_no= r *nor, u64 addr, u32 len) return ret; } =20 +static int spi_nor_erase_dice(struct spi_nor *nor, loff_t addr, + size_t len, size_t die_size) +{ + unsigned long timeout; + int ret; + + /* + * Scale the timeout linearly with the size of the flash, with + * a minimum calibrated to an old 2MB flash. We could try to + * pull these from CFI/SFDP, but these values should be good + * enough for now. + */ + timeout =3D max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, + CHIP_ERASE_2MB_READY_WAIT_JIFFIES * + (unsigned long)(nor->mtd.size / SZ_2M)); + + do { + ret =3D spi_nor_lock_device(nor); + if (ret) + return ret; + + ret =3D spi_nor_write_enable(nor); + if (ret) { + spi_nor_unlock_device(nor); + return ret; + } + + ret =3D spi_nor_erase_die(nor, addr, die_size); + + spi_nor_unlock_device(nor); + if (ret) + return ret; + + ret =3D spi_nor_wait_till_ready_with_timeout(nor, timeout); + if (ret) + return ret; + + addr +=3D die_size; + len -=3D die_size; + + } while (len); + + return 0; +} + /* * Erase an address range on the nor chip. The address range may extend * one or more erase sectors. Return an error if there is a problem erasin= g. @@ -1799,7 +1852,10 @@ static int spi_nor_erase_multi_sectors(struct spi_no= r *nor, u64 addr, u32 len) static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr) { struct spi_nor *nor =3D mtd_to_spi_nor(mtd); + u8 n_dice =3D nor->params->n_dice; + bool multi_die_erase =3D false; u32 addr, len, rem; + size_t die_size; int ret; =20 dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr, @@ -1814,39 +1870,22 @@ static int spi_nor_erase(struct mtd_info *mtd, stru= ct erase_info *instr) addr =3D instr->addr; len =3D instr->len; =20 + if (n_dice) { + die_size =3D div_u64(mtd->size, n_dice); + if (!(len & (die_size - 1)) && !(addr & (die_size - 1))) + multi_die_erase =3D true; + } else { + die_size =3D mtd->size; + } + ret =3D spi_nor_prep_and_lock_pe(nor, instr->addr, instr->len); if (ret) return ret; =20 - /* whole-chip erase? */ - if (len =3D=3D mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { - unsigned long timeout; - - ret =3D spi_nor_lock_device(nor); - if (ret) - goto erase_err; - - ret =3D spi_nor_write_enable(nor); - if (ret) { - spi_nor_unlock_device(nor); - goto erase_err; - } - - ret =3D spi_nor_erase_chip(nor); - spi_nor_unlock_device(nor); - if (ret) - goto erase_err; - - /* - * Scale the timeout linearly with the size of the flash, with - * a minimum calibrated to an old 2MB flash. We could try to - * pull these from CFI/SFDP, but these values should be good - * enough for now. - */ - timeout =3D max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES, - CHIP_ERASE_2MB_READY_WAIT_JIFFIES * - (unsigned long)(mtd->size / SZ_2M)); - ret =3D spi_nor_wait_till_ready_with_timeout(nor, timeout); + /* chip (die) erase? */ + if ((len =3D=3D mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) || + multi_die_erase) { + ret =3D spi_nor_erase_dice(nor, addr, len, die_size); if (ret) goto erase_err; =20 @@ -2902,6 +2941,9 @@ static int spi_nor_late_init_params(struct spi_nor *n= or) return ret; } =20 + if (!nor->params->die_erase_opcode) + nor->params->die_erase_opcode =3D SPINOR_OP_CHIP_ERASE; + /* Default method kept for backward compatibility. */ if (!params->set_4byte_addr_mode) params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index a456042379ee..b43ea2d49e74 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -85,9 +85,9 @@ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) =20 -#define SPI_NOR_CHIP_ERASE_OP \ - SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CHIP_ERASE, 0), \ - SPI_MEM_OP_NO_ADDR, \ +#define SPI_NOR_DIE_ERASE_OP(opcode, addr_nbytes, addr, dice) \ + SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \ + SPI_MEM_OP_ADDR(dice ? addr_nbytes : 0, addr, 0), \ SPI_MEM_OP_NO_DUMMY, \ SPI_MEM_OP_NO_DATA) =20 @@ -362,6 +362,7 @@ struct spi_nor_otp { * command in octal DTR mode. * @n_banks: number of banks. * @n_dice: number of dice in the flash memory. + * @die_erase_opcode: die erase opcode. Defaults to SPINOR_OP_CHIP_ERASE. * @vreg_offset: volatile register offset for each die. * @hwcaps: describes the read and page program hardware * capabilities. @@ -399,6 +400,7 @@ struct spi_nor_flash_parameter { u8 rdsr_addr_nbytes; u8 n_banks; u8 n_dice; + u8 die_erase_opcode; u32 *vreg_offset; =20 struct spi_nor_hwcaps hwcaps; diff --git a/drivers/mtd/spi-nor/debugfs.c b/drivers/mtd/spi-nor/debugfs.c index 6e163cb5b478..2dbda6b6938a 100644 --- a/drivers/mtd/spi-nor/debugfs.c +++ b/drivers/mtd/spi-nor/debugfs.c @@ -138,7 +138,7 @@ static int spi_nor_params_show(struct seq_file *s, void= *data) =20 if (!(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) { string_get_size(params->size, 1, STRING_UNITS_2, buf, sizeof(buf)); - seq_printf(s, " %02x (%s)\n", SPINOR_OP_CHIP_ERASE, buf); + seq_printf(s, " %02x (%s)\n", nor->params->die_erase_opcode, buf); } =20 seq_puts(s, "\nsector map\n"); --=20 2.34.1 From nobody Wed Dec 17 13:53:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 726A5C61D9D for ; Sat, 25 Nov 2023 12:35:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232082AbjKYMfo (ORCPT ); Sat, 25 Nov 2023 07:35:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232023AbjKYMfm (ORCPT ); Sat, 25 Nov 2023 07:35:42 -0500 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A595E19D for ; Sat, 25 Nov 2023 04:35:48 -0800 (PST) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-a049d19b63bso383653966b.2 for ; Sat, 25 Nov 2023 04:35:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700915747; x=1701520547; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dRVqX+0ahP3hP/THbaHoTXImqdkW4hzKFigoAdVJ+tc=; b=PB5ovGiV2y7YQkgEsNP1DbR1KEROfEDC/jQvRmGBBSZMwFGIKNKSoLbURHArrWMk7Z uN0NT/AMETmdjpKV6BZOneRAqxwialECSRf56OVaccvah0j0FxFoRzzBJ+OMIh4tpHw4 K4qAXluYUjbElfFMrqs1pTaEHDnNus39urW3eB9zxYmprNTnHxSpdtPAxePKItMxJI2O rq0APR3HwVYQSqUSuOZTcd/VSusWbuA3Ypc3PZVS83QEUgkgxSkQTm7oDWjv4ZHygJpV CM/7UWkQrHjOcEBkhr6kmNSNc3VpU9ZsNHy83NRVCCnR/D5rY3GUfmSE3MNFp4TmLbaX jkyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700915747; x=1701520547; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dRVqX+0ahP3hP/THbaHoTXImqdkW4hzKFigoAdVJ+tc=; b=UZitGJYXMU6U4zLVJJl2dKgeylDKq7RmMMKV9roJIE2kDWR82g71m+FVDkdinI0smB SoG3gLr1SCEZ7tcwrYbsJ5L09useA64IttqWJC/4n8NVezwjYsVAX8ziV4r3342vPokI Me1RV9tmz3s3BIQCJpbEKnHaV6NZrN7dZWg1Kx2LiH6TQyeKGgshaMfvH2k3x3o07WzZ JhdD7bmhYP0+SHaGqzBe/9oD8UwNe2H07LHEGvPIiZ3greTkXaCOt9iN8yyJnnrRScm7 xbaLr0nurdhv1ZkWbEuIUOLyCNVuR9ZiFRON1cPANKEiR59djtBWMCbqaMQ1xfyOoV8/ 6+jw== X-Gm-Message-State: AOJu0Ywl4as9msGLRNGPZVH76Q8h8OGIkFRtbNwWscienZAlLbA7itYv xQrXOKzp4iDMpaWR5kzMhN6HPQ== X-Google-Smtp-Source: AGHT+IGCzZkHJ01zddYYZyY7G1FynXO7V/Sr1FyMQrUeiJnGt2U+RhocZAE4ny7OjDOfx0vGfKUaBQ== X-Received: by 2002:a17:906:583:b0:9d3:ccf0:761e with SMTP id 3-20020a170906058300b009d3ccf0761emr4438046ejn.49.1700915747228; Sat, 25 Nov 2023 04:35:47 -0800 (PST) Received: from 1.. ([79.115.63.75]) by smtp.gmail.com with ESMTPSA id lv23-20020a170906bc9700b009f28db2b702sm3390163ejb.209.2023.11.25.04.35.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 04:35:46 -0800 (PST) From: Tudor Ambarus To: pratyush@kernel.org, michael@walle.cc, fastevam@denx.de Cc: linux-mtd@lists.infradead.org, takahiro.kuwano@infineon.com, bacem.daassi@infineon.com, linux-kernel@vger.kernel.org, Tudor Ambarus , Takahiro Kuwano Subject: [PATCH v3 2/5] mtd: spi-nor: spansion: enable die erase for multi die flashes Date: Sat, 25 Nov 2023 14:35:26 +0200 Message-Id: <20231125123529.55686-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231125123529.55686-1-tudor.ambarus@linaro.org> References: <20231125123529.55686-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1697; i=tudor.ambarus@linaro.org; h=from:subject; bh=2CCTjENYaOp4KjdgQLpG9dbq/tdNpT2/M9c0IJnNCs4=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlYeoRWECU8zlwpkWjK8Gxq1ZVckDE6TznyRPi0 dovpaLFBOuJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZWHqEQAKCRBLVU9HpY0U 6XxvCAC5nwYsSD43zvsYNX9DI8fXGcVIgYDaFnE7sgVaKHBcsP+navdzFbNzaixLSs6xu3Razg2 fipVsEMjGz1hx2pZHh5zNksOAw/nrpFelt4ZyGA/6jCsdK6OVBinSAxb76HheGfKfvlBsEXrSc9 TzNNwHdUvz1VmjF4SY27xBNk+9np0pGbvjdCJgt+0xzfWlLjHqqjiUqqEdu9Q3mKtg1i2hmItb3 S4qQ+7r6farjgZkubIIsIKqKJBustVSGU98TS6vuQnsFUuPxsRSr1fLxIQruNI46y1GdbH1DFEf IF72cHhC2L3vf9xnBeXqmI3xhoj/sRuz1H+zBDldgyAsHdMX X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable die erase for spansion multi die flashes. Signed-off-by: Tudor Ambarus Tested-by: Takahiro Kuwano Tested-by: Fabio Estevam --- drivers/mtd/spi-nor/spansion.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c index 12921344373d..6cc237c24e07 100644 --- a/drivers/mtd/spi-nor/spansion.c +++ b/drivers/mtd/spi-nor/spansion.c @@ -17,6 +17,7 @@ =20 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */ +#define SPINOR_OP_CYPRESS_DIE_ERASE 0x61 /* Chip (die) erase */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ #define SPINOR_REG_CYPRESS_VREG 0x00800000 @@ -644,6 +645,7 @@ static int s25hx_t_late_init(struct spi_nor *nor) params->ready =3D cypress_nor_sr_ready_and_clear; cypress_nor_ecc_init(nor); =20 + params->die_erase_opcode =3D SPINOR_OP_CYPRESS_DIE_ERASE; return 0; } =20 @@ -933,7 +935,6 @@ static const struct flash_info spansion_nor_parts[] =3D= { .id =3D SNOR_ID(0x34, 0x2a, 0x1c, 0x0f, 0x00, 0x90), .name =3D "s25hl02gt", .mfr_flags =3D USE_CLPEF, - .flags =3D NO_CHIP_ERASE, .fixups =3D &s25hx_t_fixups }, { .id =3D SNOR_ID(0x34, 0x2b, 0x19, 0x0f, 0x08, 0x90), @@ -954,7 +955,6 @@ static const struct flash_info spansion_nor_parts[] =3D= { .id =3D SNOR_ID(0x34, 0x2b, 0x1c, 0x0f, 0x00, 0x90), .name =3D "s25hs02gt", .mfr_flags =3D USE_CLPEF, - .flags =3D NO_CHIP_ERASE, .fixups =3D &s25hx_t_fixups }, { .id =3D SNOR_ID(0x34, 0x5a, 0x1a), --=20 2.34.1 From nobody Wed Dec 17 13:53:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43DCEC636CB for ; Sat, 25 Nov 2023 12:36:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232182AbjKYMfz (ORCPT ); Sat, 25 Nov 2023 07:35:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232095AbjKYMfv (ORCPT ); Sat, 25 Nov 2023 07:35:51 -0500 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5440310C3 for ; Sat, 25 Nov 2023 04:35:51 -0800 (PST) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2c4fdf94666so33785631fa.2 for ; Sat, 25 Nov 2023 04:35:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700915749; x=1701520549; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=F6SZmI3Pvpo+nrX5dodxgt+vurPd9z+DUMvPpLGMSBc=; b=FsYfrmmvj7bHR8ZD+BHJdpcEFRmc06RsFM3Mx2LCDFKld0rNZcpDEY5M1QVVGqVYHa k9NYgU2liUZ/qfj9dRI5oQOJK2mwPUMJQnbyFAMi+xnfAzQ9hxBoWQjTnPln6pz4NhEW oeFhSS/vx6Shq2m/eQrFoeWDAEenpBwI6BEqBGuKtWK4/ZAkaCcd60pRc7IBakSYAF/Q f9ZFh2Gt1gZ4TCyO1sBwMwrdSrV4/ozLyw4Vcek18iRvY18Xq7mddqrhYY5uM03jLZKS mgE1Qh4YDNWpvMDQK+aj7ZlWo3XZO+2px77v1KkvA8ZtDvB9G4TsCjjzE83I3RV4eD/z H9Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700915749; x=1701520549; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=F6SZmI3Pvpo+nrX5dodxgt+vurPd9z+DUMvPpLGMSBc=; b=jRT974UPG9+bB5i8Ecw7Dy02yB3NnAWOC1b14uqJ7daRPTIN9eYp0iaXaF0EeRIpBN Ou2l88CdWFi4NABibva0o3fg0pK6d2P/bpI4iOj5yb/RTKfI8rOUP7KXGG5l3iAPwhhk 9wU9+jFOM5M6Q1fjZj4U8jwFWhyfb5GpcDDRrelCt5NGsjOQICru+w0EYqAxzQcArhyf n5CQGyffPDbDX9hI79LIBW4wTY8TUPID2M1WKEZ3EF0fiGE8ts5kyL7YPd5jhFFTsjtc 8IJ+Idt985xedDUdniTbpYwDv/6ZmuZIm9PiVGkYgf+6EgDkreqVLU49lIcH7gxKD7GK 63ug== X-Gm-Message-State: AOJu0YzBeZEL0eV7Ro5gO6RANHZV7QpMl078xynk0GcU7w/s0s7WJ/nz eL/LQqeoCajInZjS3DoRCvtjRg== X-Google-Smtp-Source: AGHT+IFnlUNbv1bzqaYWlHJAnWS/4VIO5P4jsKT4o64p9qsT9PebV/XdwK9R3AlLMTWb39ivK7Wbcw== X-Received: by 2002:a2e:8811:0:b0:2c0:20c4:925a with SMTP id x17-20020a2e8811000000b002c020c4925amr3819642ljh.26.1700915749523; Sat, 25 Nov 2023 04:35:49 -0800 (PST) Received: from 1.. ([79.115.63.75]) by smtp.gmail.com with ESMTPSA id lv23-20020a170906bc9700b009f28db2b702sm3390163ejb.209.2023.11.25.04.35.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 04:35:49 -0800 (PST) From: Tudor Ambarus To: pratyush@kernel.org, michael@walle.cc, fastevam@denx.de Cc: linux-mtd@lists.infradead.org, takahiro.kuwano@infineon.com, bacem.daassi@infineon.com, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 3/5] mtd: spi-nor: micron-st: enable die erase for multi die flashes Date: Sat, 25 Nov 2023 14:35:27 +0200 Message-Id: <20231125123529.55686-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231125123529.55686-1-tudor.ambarus@linaro.org> References: <20231125123529.55686-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=15251; i=tudor.ambarus@linaro.org; h=from:subject; bh=mUCYe9d/EUp4D3V/P7y4Cpq/h/1M8gZWgBseZTqz10w=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlYeoRAV2gAmwDVCEJKBJpMuDSYjhIomMvFwzRf cji/nZYFNWJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZWHqEQAKCRBLVU9HpY0U 6Xp6B/9AcftybY10gH+pn84gJURdIKDUeClcf6ZVdr1zzEpxhQ1MRZGhRNWC+D6hTw1M7GWSTsD gpMCUzvSK15HuWriGB2r/VdXHMp/hQerZ+Vq27nsAmEbiHmbvhPuu/Wqq60bx7Djvpbuqa8UVaJ 6mep/lMKGbjlLkPPwpO7F98HS2UWEGGrs//x6ZVob7Yx+OmnCysBROTNXycUlT0XDjn8cUmDfR3 IgfGYLko2VL6dyoxrmwHYhv5kblKZ0IEucnzEPHQqF/uiCSDsCOu+mMjMZhwMpMr5IJGZgoHATQ OTJRNDKEIlFBIRwnZtqM8mLEJPeUmASaiXSZ+KuX8dnY6aWy X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable die erase for multi die flashes, it will speed the erase time. Unfortunately, Micron does not provide a 4-byte opcode equivalent for the die erase. The SFDP 4BAIT table fails to consider the die erase too, the standard can be improved. Thus we're forced to enter in the 4 byte address mode in order to benefit of the die erase. Tested on n25q00. This flash defines the 4BAIT SFDP table, thus it will use the 4BAIT opcodes for reads, page programs or erases, with the exception that it will use the die erase command in the 4 byte address mode. Link: https://media-www.micron.com/-/media/client/global/documents/products= /data-sheet/nor-flash/serial-nor/n25q/n25q_1gb_3v_65nm.pdf?rev=3Db6eba74759= 984f749f8c039bc5bc47b7 Link: https://media-www.micron.com/-/media/client/global/documents/products= /data-sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_l_02g_cbb_0.pdf= ?rev=3D43f7f66fc8da4d7d901b35fa51284c8f Signed-off-by: Tudor Ambarus Tested-by: Fabio Estevam --- Tested on sama5d2_xplained using the "atmel,sama5d2-qspi" spi controller and by operating the flash at 80MHz. root@sama5d2-xplained-emmc:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/partn= ame n25q00 root@sama5d2-xplained-emmc:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/jedec= _id=20 20ba21 root@sama5d2-xplained-emmc:~# cat /sys/bus/spi/devices/spi1.0/spi-nor/manuf= acturer=20 st root@sama5d2-xplained-emmc:~# xxd -p /sys/bus/spi/devices/spi1.0/spi-nor/sf= dp =20 53464450060101ff00060110300000ff84000102800000ffffffffffffff ffffffffffffffffffffffffffffffffffffe520fbffffffff3f29eb276b 273b27bbffffffffffff27bbffff29eb0c2010d80f520000244a99008b8e 03e1ac0127387a757a75fbbdd55c4a0f82ff81bd3d36ffffffffffffffff ffffffffffffffffffe7ffff21dcffff root@sama5d2-xplained-emmc:~# sha256sum /sys/bus/spi/devices/spi1.0/spi-nor= /sfdp e49dfee6eeb73c55e94c07a8c7d352dd7d8774b830a64ed1059ef6e7bc833668 /sys/bus/= spi/devices/spi1.0/spi-nor/sfdp root@sama5d2-xplained-emmc:~# cat /sys/kernel/debug/spi-nor/spi1.0/capabili= ties Supported read modes by the flash 1S-1S-1S opcode 0x13 mode cycles 0 dummy cycles 0 1S-1S-1S (fast read) opcode 0x0c mode cycles 0 dummy cycles 8 1S-1S-2S opcode 0x3c mode cycles 1 dummy cycles 7 1S-2S-2S opcode 0xbc mode cycles 1 dummy cycles 7 2S-2S-2S opcode 0xbc mode cycles 1 dummy cycles 7 1S-1S-4S opcode 0x6c mode cycles 1 dummy cycles 7 1S-4S-4S opcode 0xec mode cycles 1 dummy cycles 9 4S-4S-4S opcode 0xec mode cycles 1 dummy cycles 9 Supported page program modes by the flash 1S-1S-1S opcode 0x12 1S-1S-4S opcode 0x34 1S-4S-4S opcode 0x3e root@sama5d2-xplained-emmc:~# cat /sys/kernel/debug/spi-nor/spi1.0/params name n25q00 id 20 ba 21 10 40 00 size 128 MiB write size 1 page size 256 address nbytes 4 flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_4BIT_BP | HAS_SR= _BP3_BIT6 | SOFT_RESET opcodes read 0xec dummy cycles 10 erase 0x21 program 0x3e 8D extension none protocols read 1S-4S-4S write 1S-4S-4S register 1S-1S-1S erase commands 21 (4.00 KiB) [1] dc (64.0 KiB) [3] c4 (128 MiB) sector map region (in hex) | erase mask | flags ------------------+------------+---------- 00000000-07ffffff | [ 123] |=20 =20 root@sama5d2-xplained-emmc:~# dd if=3D/dev/urandom of=3D./spi_test bs=3D1M = count=3D2 2+0 records in 2+0 records out 2097152 bytes (2.1 MB, 2.0 MiB) copied, 1.40662 s, 1.5 MB/s root@sama5d2-xplained-emmc:~# mtd_debug erase /dev/mtd1 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read root@sama5d2-xplained-emmc:~# hexdump spi_read 0000000 ffff ffff ffff ffff ffff ffff ffff ffff * 0200000 root@sama5d2-xplained-emmc:~# sha256sum spi_read 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 0 2097152 spi_test Copied 2097152 bytes from spi_test to address 0x00000000 in flash root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read root@sama5d2-xplained-emmc:~# sha256sum spi* 15608dfc2a8ef8352c1ec18863592002d8bb54195f0163794ac78c8599496808 spi_read 15608dfc2a8ef8352c1ec18863592002d8bb54195f0163794ac78c8599496808 spi_test root@sama5d2-xplained-emmc:~# mtd_debug erase /dev/mtd1 0 2097152 Erased 2097152 bytes from address 0x00000000 in flash root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 2097152 spi_read Copied 2097152 bytes from address 0x00000000 in flash to spi_read root@sama5d2-xplained-emmc:~# sha256sum spi* 4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read 15608dfc2a8ef8352c1ec18863592002d8bb54195f0163794ac78c8599496808 spi_test root@sama5d2-xplained-emmc:~# mtd_debug info /dev/mtd1 mtd.type =3D MTD_NORFLASH mtd.flags =3D MTD_CAP_NORFLASH mtd.size =3D 134217728 (128M) mtd.erasesize =3D 4096 (4K) mtd.writesize =3D 1=20 mtd.oobsize =3D 0=20 regions =3D 0 root@sama5d2-xplained-emmc:~# time mtd_debug erase /dev/mtd1 0 134217728 Erased 134217728 bytes from address 0x00000000 in flash real 0m6.900s user 0m0.000s sys 0m6.899s root@sama5d2-xplained-emmc:~# echo "ta writes something into the first die"= > firstdie root@sama5d2-xplained-emmc:~# echo "ta writes something into the second die= " > seconddie root@sama5d2-xplained-emmc:~# echo "ta writes something into the 3rd die 33= 333" > thirddie root@sama5d2-xplained-emmc:~# echo "ta writes something into the 4th die 44= 4444" > fourthdie root@sama5d2-xplained-emmc:~# ls -al total 176168 drwx------ 3 root root 4096 Apr 29 00:48 . drwxr-xr-x 3 root root 4096 Mar 9 2018 .. -rw-r--r-- 1 root root 39 Apr 29 00:45 firstdie -rw-r--r-- 1 root root 44 Apr 29 00:48 fourthdie -rw-r--r-- 1 root root 40 Apr 29 00:45 seconddie -rw-r--r-- 1 root root 2097152 Apr 29 00:42 spi_read -rw-r--r-- 1 root root 2097152 Apr 29 00:40 spi_test -rw-r--r-- 1 root root 43 Apr 29 00:47 thirddie root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 0 39 firstdie Copied 39 bytes from firstdie to address 0x00000000 in flash root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 33554432 40 secondd= ie=20 Copied 40 bytes from seconddie to address 0x02000000 in flash root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 67108864 43 thirddi= e=20 Copied 43 bytes from thirddie to address 0x04000000 in flash root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 100663296 44 fourth= die=20 Copied 44 bytes from fourthdie to address 0x06000000 in flash root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 134217728 read Copied 134217728 bytes from address 0x00000000 in flash to read root@sama5d2-xplained-emmc:~# hexdump -C read 00000000 74 61 20 77 72 69 74 65 73 20 73 6f 6d 65 74 68 |ta writes some= th| 00000010 69 6e 67 20 69 6e 74 6f 20 74 68 65 20 66 69 72 |ing into the f= ir| 00000020 73 74 20 64 69 65 0a ff ff ff ff ff ff ff ff ff |st die........= ..| 00000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |..............= ..| * 02000000 74 61 20 77 72 69 74 65 73 20 73 6f 6d 65 74 68 |ta writes some= th| 02000010 69 6e 67 20 69 6e 74 6f 20 74 68 65 20 73 65 63 |ing into the s= ec| 02000020 6f 6e 64 20 64 69 65 0a ff ff ff ff ff ff ff ff |ond die.......= ..| 02000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |..............= ..| * 04000000 74 61 20 77 72 69 74 65 73 20 73 6f 6d 65 74 68 |ta writes some= th| 04000010 69 6e 67 20 69 6e 74 6f 20 74 68 65 20 33 72 64 |ing into the 3= rd| 04000020 20 64 69 65 20 33 33 33 33 33 0a ff ff ff ff ff | die 33333....= ..| 04000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |..............= ..| * 06000000 74 61 20 77 72 69 74 65 73 20 73 6f 6d 65 74 68 |ta writes some= th| 06000010 69 6e 67 20 69 6e 74 6f 20 74 68 65 20 34 74 68 |ing into the 4= th| 06000020 20 64 69 65 20 34 34 34 34 34 34 0a ff ff ff ff | die 444444...= ..| 06000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |..............= ..| * 08000000 root@sama5d2-xplained-emmc:~# time mtd_debug erase /dev/mtd1 0 134217728 Erased 134217728 bytes from address 0x00000000 in flash real 0m3.800s user 0m0.001s sys 0m3.751s root@sama5d2-xplained-emmc:~# echo "ta writes a something crossing the dice= " > cross-dice root@sama5d2-xplained-emmc:~# ls -al total 176172 drwx------ 3 root root 4096 Apr 29 00:54 . drwxr-xr-x 3 root root 4096 Mar 9 2018 .. -rw-r--r-- 1 root root 40 Apr 29 00:54 cross-dice root@sama5d2-xplained-emmc:~# mtd_debug write /dev/mtd1 67108857 40 cross-d= ice=20 Copied 40 bytes from cross-dice to address 0x03fffff9 in flash root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 0 134217728 read Copied 134217728 bytes from address 0x00000000 in flash to read root@sama5d2-xplained-emmc:~# hexdump -C read 00000000 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |..............= ..| * 03fffff0 ff ff ff ff ff ff ff ff ff 74 61 20 77 72 69 74 |.........ta wr= it| 04000000 65 73 20 61 20 73 6f 6d 65 74 68 69 6e 67 20 63 |es a something= c| 04000010 72 6f 73 73 69 6e 67 20 74 68 65 20 64 69 63 65 |rossing the di= ce| 04000020 0a ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |..............= ..| 04000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |..............= ..| * 08000000 root@sama5d2-xplained-emmc:~# mtd_debug read /dev/mtd1 67108857 40 read = =20 Copied 40 bytes from address 0x03fffff9 in flash to read root@sama5d2-xplained-emmc:~# hexdump -C read 00000000 74 61 20 77 72 69 74 65 73 20 61 20 73 6f 6d 65 |ta writes a so= me| 00000010 74 68 69 6e 67 20 63 72 6f 73 73 69 6e 67 20 74 |thing crossing= t| 00000020 68 65 20 64 69 63 65 0a |he dice.| 00000028 root@sama5d2-xplained-emmc:~#=20 drivers/mtd/spi-nor/core.c | 32 ++++++++++++++++--------------- drivers/mtd/spi-nor/micron-st.c | 34 +++++++++++++++++++++++++++++---- 2 files changed, 47 insertions(+), 19 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 479494cf00c9..52e5b569ddfd 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2935,6 +2935,9 @@ static int spi_nor_late_init_params(struct spi_nor *n= or) return ret; } =20 + /* Needed by some flashes late_init hooks. */ + spi_nor_init_flags(nor); + if (nor->info->fixups && nor->info->fixups->late_init) { ret =3D nor->info->fixups->late_init(nor); if (ret) @@ -2948,7 +2951,6 @@ static int spi_nor_late_init_params(struct spi_nor *n= or) if (!params->set_4byte_addr_mode) params->set_4byte_addr_mode =3D spi_nor_set_4byte_addr_mode_brwr; =20 - spi_nor_init_flags(nor); spi_nor_init_fixup_flags(nor); =20 /* @@ -3186,6 +3188,18 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor,= bool enable) struct spi_nor_flash_parameter *params =3D nor->params; int ret; =20 + if (enable) { + /* + * If the RESET# pin isn't hooked up properly, or the system + * otherwise doesn't perform a reset command in the boot + * sequence, it's impossible to 100% protect against unexpected + * reboots (e.g., crashes). Warn the user (or hopefully, system + * designer) that this is bad. + */ + WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, + "enabling reset hack; may not recover from unexpected reboots\n"); + } + ret =3D params->set_4byte_addr_mode(nor, enable); if (ret && ret !=3D -ENOTSUPP) return ret; @@ -3234,20 +3248,8 @@ static int spi_nor_init(struct spi_nor *nor) =20 if (nor->addr_nbytes =3D=3D 4 && nor->read_proto !=3D SNOR_PROTO_8_8_8_DTR && - !(nor->flags & SNOR_F_4B_OPCODES)) { - /* - * If the RESET# pin isn't hooked up properly, or the system - * otherwise doesn't perform a reset command in the boot - * sequence, it's impossible to 100% protect against unexpected - * reboots (e.g., crashes). Warn the user (or hopefully, system - * designer) that this is bad. - */ - WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET, - "enabling reset hack; may not recover from unexpected reboots\n"); - err =3D spi_nor_set_4byte_addr_mode(nor, true); - if (err) - return err; - } + !(nor->flags & SNOR_F_4B_OPCODES)) + return spi_nor_set_4byte_addr_mode(nor, true); =20 return 0; } diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index 8920547c12bf..b63f1e9b97d0 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -11,6 +11,7 @@ /* flash_info mfr_flag. Used to read proprietary FSR register. */ #define USE_FSR BIT(0) =20 +#define SPINOR_OP_MT_DIE_ERASE 0xc4 /* Chip (die) erase opcode */ #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */ #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */ #define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */ @@ -192,6 +193,30 @@ static struct spi_nor_fixups mt25qu512a_fixups =3D { .post_bfpt =3D mt25qu512a_post_bfpt_fixup, }; =20 +static int st_nor_four_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params =3D nor->params; + + params->die_erase_opcode =3D SPINOR_OP_MT_DIE_ERASE; + params->n_dice =3D 4; + + /* + * Unfortunately the die erase opcode does not have a 4-byte opcode + * correspondent for these flashes. The SFDP 4BAIT table fails to + * consider the die erase too. We're forced to enter in the 4 byte + * address mode in order to benefit of the die erase. + */ + return spi_nor_set_4byte_addr_mode(nor, true); +} + +static struct spi_nor_fixups n25q00_fixups =3D { + .late_init =3D st_nor_four_die_late_init, +}; + +static struct spi_nor_fixups mt25q02_fixups =3D { + .late_init =3D st_nor_four_die_late_init, +}; + static const struct flash_info st_nor_parts[] =3D { { .name =3D "m25p05-nonjedec", @@ -366,16 +391,17 @@ static const struct flash_info st_nor_parts[] =3D { .name =3D "n25q00", .size =3D SZ_128M, .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_4BIT_BP | - SPI_NOR_BP3_SR_BIT6 | NO_CHIP_ERASE, + SPI_NOR_BP3_SR_BIT6, .no_sfdp_flags =3D SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags =3D USE_FSR, + .fixups =3D &n25q00_fixups, }, { .id =3D SNOR_ID(0x20, 0xba, 0x22), .name =3D "mt25ql02g", .size =3D SZ_256M, - .flags =3D NO_CHIP_ERASE, .no_sfdp_flags =3D SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags =3D USE_FSR, + .fixups =3D &mt25q02_fixups, }, { .id =3D SNOR_ID(0x20, 0xbb, 0x15), .name =3D "n25q016a", @@ -433,16 +459,16 @@ static const struct flash_info st_nor_parts[] =3D { .id =3D SNOR_ID(0x20, 0xbb, 0x21), .name =3D "n25q00a", .size =3D SZ_128M, - .flags =3D NO_CHIP_ERASE, .no_sfdp_flags =3D SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags =3D USE_FSR, + .fixups =3D &n25q00_fixups, }, { .id =3D SNOR_ID(0x20, 0xbb, 0x22), .name =3D "mt25qu02g", .size =3D SZ_256M, - .flags =3D NO_CHIP_ERASE, .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, .mfr_flags =3D USE_FSR, + .fixups =3D &mt25q02_fixups, } }; =20 --=20 2.34.1 From nobody Wed Dec 17 13:53:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B544C61D9D for ; Sat, 25 Nov 2023 12:36:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232099AbjKYMf5 (ORCPT ); Sat, 25 Nov 2023 07:35:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232117AbjKYMfw (ORCPT ); Sat, 25 Nov 2023 07:35:52 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98E7019A2 for ; Sat, 25 Nov 2023 04:35:53 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-a04196fc957so400375966b.2 for ; Sat, 25 Nov 2023 04:35:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700915752; x=1701520552; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=txTWULb3qOMaVJaVM0srxekYyIAj97clVpD1wkCUdRs=; b=EWPRE/vfl+RmfjK20cXi9hFsk188ZxF6ccY/qTb73etgm1jvHEt5POQmimUde9A/Y5 IdCMqBIsGH1JXEuBbulmhReOmpDv9oIlVdAnrEusnTp++iADI898Dn+m160uUaVzX4y1 +FNGjCLURqJDBmnwN5oUh9/EIizXnZRZ6FeGtHobFOopnfF/n9vlS0uao3Y/PtsgjzxM sfhUAbU98c9ziJ/5OwyM+YGk7oYeyvUqIGiB72VeJVEwjoXZ6fzE46eNIDPW+pJ65WY/ dCo24w0ZyuD0v+IEx83Zkvr5ATsLAs1UQJj538L+fGglFA/HhFDEpyc4s2B6fTclH3sA ZmNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700915752; x=1701520552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=txTWULb3qOMaVJaVM0srxekYyIAj97clVpD1wkCUdRs=; b=gtGQo8myPnK2Jpgcx1u9JW1mkEjCso9EXj6jdekPlD8WJa3ZO0S4EmmHONE33S7ryS 5t0yqE+lCPfaKDZP5xdVjhSxwXgP+F2cXlq55prmaEErZe4tMMmQQw+Pj1zFHG5zx4B5 oQUovMUHzcPvy9KW7nn6T8/di7cxhKM1ip7d0Oj5X0ljrF28kltTSiBTrJ+kFs0l4DnC XHUpFBKajLZZWh6+6BQWapMFkazrS8YBIdjsyMwW50ozEFcObgs08ceHHubFKSOxsg6q T/CpO3aUuD+3aZ6rV3BCLKo0jeGq2d6VdwrAfvDwO2zYiUdxRRYkdu6UZ3vAaIH2gkFe rpuQ== X-Gm-Message-State: AOJu0YzQn7H25hUtQJ8m42H4Q2i1gWCFSjMA+nMKjPTXyp9jAztB3svH Qs6ag9qo0bBNAuHDfUDjlwkciQ== X-Google-Smtp-Source: AGHT+IHjGaQJjZMvJEp2O+E3VbE3I7/oZ2yVxz1hpulXF7qjWb1sTM6BVp4MjQScsWOTjZslEF2t5g== X-Received: by 2002:a17:906:d2:b0:9e2:af56:c380 with SMTP id 18-20020a17090600d200b009e2af56c380mr4056526eji.6.1700915752219; Sat, 25 Nov 2023 04:35:52 -0800 (PST) Received: from 1.. ([79.115.63.75]) by smtp.gmail.com with ESMTPSA id lv23-20020a170906bc9700b009f28db2b702sm3390163ejb.209.2023.11.25.04.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 04:35:51 -0800 (PST) From: Tudor Ambarus To: pratyush@kernel.org, michael@walle.cc, fastevam@denx.de Cc: linux-mtd@lists.infradead.org, takahiro.kuwano@infineon.com, bacem.daassi@infineon.com, linux-kernel@vger.kernel.org, Tudor Ambarus Subject: [PATCH v3 4/5] mtd: spi-nor: remove NO_CHIP_ERASE flag Date: Sat, 25 Nov 2023 14:35:28 +0200 Message-Id: <20231125123529.55686-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231125123529.55686-1-tudor.ambarus@linaro.org> References: <20231125123529.55686-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1896; i=tudor.ambarus@linaro.org; h=from:subject; bh=CCp3s597dd2N34pcvWqlxQ50V8OYh2tnaQCvSzFKDOc=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlYeoRHtkHuEy/gG4P7KkUgLRNHmTbUGbxJBrYu JpjuIMIeFqJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZWHqEQAKCRBLVU9HpY0U 6U8EB/4isL9ZPOAlY3kE68x1LosSOh7Ai80yt+wDjJVDB5heW0xOuYMbkEfIwfpIYuDCHR+GYnd XgA5CiKFrqLiHwBMwRJWKYVHby+AfwdlgJ1D8m+gCeW/8a1KAeBHGDYm3Wt85AoEV+yiFFvDEV+ b+PQX+WSWDVPCX9DrygJ+S5Wy5ddhid7ZoZXrrI84jOjOgC50BUQqEiCRoMLN3GI/L6WSvCeHgp 827qSsTa2taSWG8HocFv0Q/I257SwmQzNUJxGEUPTL8drbtu6if3yd49etgNoooeQiVn/hfS7zK iDgH8EbbhaZDpYO9+qKUoKhnFSDuV2LhYd3AD6zPqPXutGN6 X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" There's no flash using it and we'd like to rely instead on SFDP data, thus remove it. Signed-off-by: Tudor Ambarus Tested-by: Fabio Estevam --- drivers/mtd/spi-nor/core.c | 3 --- drivers/mtd/spi-nor/core.h | 8 +++----- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 52e5b569ddfd..503fed90c2fa 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2888,9 +2888,6 @@ static void spi_nor_init_flags(struct spi_nor *nor) nor->flags |=3D SNOR_F_HAS_SR_BP3_BIT6; } =20 - if (flags & NO_CHIP_ERASE) - nor->flags |=3D SNOR_F_NO_OP_CHIP_ERASE; - if (flags & SPI_NOR_RWW && nor->params->n_banks > 1 && !nor->controller_ops) nor->flags |=3D SNOR_F_RWW; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index b43ea2d49e74..29ed67725b18 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -489,7 +489,6 @@ struct spi_nor_id { * Usually these will power-up in a write-prote= cted * state. * SPI_NOR_NO_ERASE: no erase command needed. - * NO_CHIP_ERASE: chip does not support chip erase. * SPI_NOR_NO_FR: can't do fastread. * SPI_NOR_QUAD_PP: flash supports Quad Input Page Program. * SPI_NOR_RWW: flash supports reads while write. @@ -539,10 +538,9 @@ struct flash_info { #define SPI_NOR_BP3_SR_BIT6 BIT(4) #define SPI_NOR_SWP_IS_VOLATILE BIT(5) #define SPI_NOR_NO_ERASE BIT(6) -#define NO_CHIP_ERASE BIT(7) -#define SPI_NOR_NO_FR BIT(8) -#define SPI_NOR_QUAD_PP BIT(9) -#define SPI_NOR_RWW BIT(10) +#define SPI_NOR_NO_FR BIT(7) +#define SPI_NOR_QUAD_PP BIT(8) +#define SPI_NOR_RWW BIT(9) =20 u8 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) --=20 2.34.1 From nobody Wed Dec 17 13:53:07 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94D01C61DF4 for ; Sat, 25 Nov 2023 12:36:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232169AbjKYMgB (ORCPT ); Sat, 25 Nov 2023 07:36:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59196 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232137AbjKYMfx (ORCPT ); Sat, 25 Nov 2023 07:35:53 -0500 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E0BB19B6 for ; Sat, 25 Nov 2023 04:35:56 -0800 (PST) Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-54afdbdb7d2so1762719a12.3 for ; Sat, 25 Nov 2023 04:35:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700915754; x=1701520554; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TcXs8DG65Rtg58oE+up88Lq4hTYhaQzAZwdBNatPv3E=; b=c82j5qXo0XNniDBJR6Fr9PNjZPHTPVqanITi0G8ofo2YiiEvE3ESlb3N1IIf1WHFc6 1wBplVZgQIaWMYrceTyBcRtoVgm+505sArBWzydXLltvTwnyD0+AO2MbB5CnvSJCZPqi aoEFPDk0F736uVqx1JTlHXn7dKY/5RVRjx3R/LwTm/9clYJpsIjOk+kGlbtuhTimQmPJ XfHKEvDc7Op7Y1pYT1T9OYKVUzecmg9CwQNEOHOt6ShSHY0k1tg52gBj9+XcmHaaSUOt pP4sRT6oaeGpUBCuefaJ0FTBBcGJxppUKVzzbzYhjbShJGItavfZBqvQwS0gx3lUQP7b BvXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700915755; x=1701520555; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TcXs8DG65Rtg58oE+up88Lq4hTYhaQzAZwdBNatPv3E=; b=mKWEcLY9LAIxwBYxKJdk3SD8HvXjylmG6LDrzC0FOKVwWnmm7FSiUprj7lJlpbocLM c8VoBKTcZWntPVEFzZL33ADs6OAyNyf4cW0zkAoa/qnSSBVHw3Xh0g8/cHrl24SgHmsD 9a7vpVI3GRVrebOEx+ZEQte7V/6CcEJsuU8Z1fW29CClHlJxm8//qTT62AniOhIvU3Ha UFhGw/7eonP5AoWG53Pdr9LvdZHYK1wlRqbi0RxW0uGrvm921CI2+Fi9j+E/4PSjNtaM N15SFdPX9sOOLIfR+XhiCrPAqPGhCV6HC1swJ18MEIMTBgoAehtMvHUXKohJrd76GJj3 rLKw== X-Gm-Message-State: AOJu0YxTM4RhK1X4Cy6Xo/t9kvsgFChb4c0q14u+/AAtVhOFK4TrJTLK GyqUCJN1vlJdCuK7xEOhpLJKfQ== X-Google-Smtp-Source: AGHT+IHdeYl/OJTLXATqbQBrqR9h57XosEk+PYRoSMKkDelPWWmhTNWK1ojD/74xFrBnLuDA9IZh0Q== X-Received: by 2002:a17:906:9e08:b0:a03:4acd:750f with SMTP id fp8-20020a1709069e0800b00a034acd750fmr3994977ejc.20.1700915754802; Sat, 25 Nov 2023 04:35:54 -0800 (PST) Received: from 1.. ([79.115.63.75]) by smtp.gmail.com with ESMTPSA id lv23-20020a170906bc9700b009f28db2b702sm3390163ejb.209.2023.11.25.04.35.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 04:35:54 -0800 (PST) From: Tudor Ambarus To: pratyush@kernel.org, michael@walle.cc, fastevam@denx.de Cc: linux-mtd@lists.infradead.org, takahiro.kuwano@infineon.com, bacem.daassi@infineon.com, linux-kernel@vger.kernel.org, Fabio Estevam , Tudor Ambarus Subject: [PATCH v3 5/5] mtd: spi-nor: micron-st: Add support for mt25qu01g Date: Sat, 25 Nov 2023 14:35:29 +0200 Message-Id: <20231125123529.55686-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231125123529.55686-1-tudor.ambarus@linaro.org> References: <20231125123529.55686-1-tudor.ambarus@linaro.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2040; i=tudor.ambarus@linaro.org; h=from:subject; bh=qdPCdEgUWxvGLhVyUwHlXAj47Qi5sR15BlnuG/9ieeo=; b=owEBbQGS/pANAwAKAUtVT0eljRTpAcsmYgBlYeoRDj5E4PFoxCRL/3RvCsy7w+UgyF0bJ7L0g GgDTQENszOJATMEAAEKAB0WIQQdQirKzw7IbV4d/t9LVU9HpY0U6QUCZWHqEQAKCRBLVU9HpY0U 6UMzCACZkv+KkQDtK9Sp9Q28aV734tjYoM3xi8jyX50siPTnkCfEL7b16dE+YjCIpq/pamgVI87 oVbj35cv+nkAsguGeV7t2csTEZhL3G8YtjYgQjBsm5wT4a7fw/G23sVMJVmCOGm5Cdm8IfTp1rI U/8W06YQXPHySueKChRgJetNWByFKjcrqe7Ud387Mj+LnffKk30aPwYZTTtIy4Ymgxk6OVHdxRV l9LaSKQ91etjOk8ixjOa7GFgRdbwKTsPnJaa9KpUx9VYyfXspK7Y7PuXWLtTAR/RCHpJz97yfGO j9awPMW/+e4gBGRVcUoixIICbiTJOztAepE9gV8yE6CKDlrz X-Developer-Key: i=tudor.ambarus@linaro.org; a=openpgp; fpr=280B06FD4CAAD2980C46DDDF4DB1B079AD29CF3D Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Fabio Estevam Add support for the MT25QU01G 128MB Micron Serial NOR Flash Memory model. Link: https://www.micron.com/-/media/client/global/documents/products/data-= sheet/nor-flash/serial-nor/mt25q/die-rev-b/mt25q_qlkt_u_01g_bbb_0.pdf Signed-off-by: Fabio Estevam [ta: introduce die erase] Signed-off-by: Tudor Ambarus Tested-by: Fabio Estevam --- drivers/mtd/spi-nor/micron-st.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-s= t.c index b63f1e9b97d0..3c6499fdb712 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -209,10 +209,30 @@ static int st_nor_four_die_late_init(struct spi_nor *= nor) return spi_nor_set_4byte_addr_mode(nor, true); } =20 +static int st_nor_two_die_late_init(struct spi_nor *nor) +{ + struct spi_nor_flash_parameter *params =3D nor->params; + + params->die_erase_opcode =3D SPINOR_OP_MT_DIE_ERASE; + params->n_dice =3D 2; + + /* + * Unfortunately the die erase opcode does not have a 4-byte opcode + * correspondent for these flashes. The SFDP 4BAIT table fails to + * consider the die erase too. We're forced to enter in the 4 byte + * address mode in order to benefit of the die erase. + */ + return spi_nor_set_4byte_addr_mode(nor, true); +} + static struct spi_nor_fixups n25q00_fixups =3D { .late_init =3D st_nor_four_die_late_init, }; =20 +static struct spi_nor_fixups mt25q01_fixups =3D { + .late_init =3D st_nor_two_die_late_init, +}; + static struct spi_nor_fixups mt25q02_fixups =3D { .late_init =3D st_nor_four_die_late_init, }; @@ -455,6 +475,11 @@ static const struct flash_info st_nor_parts[] =3D { SPI_NOR_BP3_SR_BIT6, .no_sfdp_flags =3D SECT_4K | SPI_NOR_QUAD_READ, .mfr_flags =3D USE_FSR, + }, { + .id =3D SNOR_ID(0x20, 0xbb, 0x21, 0x10, 0x44, 0x00), + .name =3D "mt25qu01g", + .mfr_flags =3D USE_FSR, + .fixups =3D &mt25q01_fixups, }, { .id =3D SNOR_ID(0x20, 0xbb, 0x21), .name =3D "n25q00a", --=20 2.34.1