From nobody Wed Dec 17 15:31:16 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56615C61D9D for ; Sat, 25 Nov 2023 08:34:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231804AbjKYIe0 (ORCPT ); Sat, 25 Nov 2023 03:34:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231820AbjKYIeF (ORCPT ); Sat, 25 Nov 2023 03:34:05 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05C71E6 for ; Sat, 25 Nov 2023 00:34:11 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7FFC4C433C8; Sat, 25 Nov 2023 08:34:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1700901250; bh=f5wYmmEc/6YNMD4xeSRCsSaZscE5Ri2p04isx1ogm+s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kgagQ40xuACQ9F/M71fFeTEUd/FiPgKGt+n61Bi5CgIuS/oGuUgESREinPeSmS7SY 4VYKpfyLTnWO2UvHFr2I93eTpClr7YgMYA9UG/8e2kLqDfXaoQn6+t1YjnagmomCvd 4h7VVrBlVC6EgbE6vnlgT3epFhtQHP36aiCNQJfSBCxEPYLv3XHwPhUsDVZ8ti0wyh AWDR1IjFmfKsIo/wf0CmJ8aJ4rZxM6TACXKKb8YiiFIO9Uu9GD1OakQvfTMoHsgEms WYhEQwW7l16E+TUhhZwkokQKShO6/fMe/HPqoGUzYh9I/hzgUi7rxlLgdEv7F/eyZC 5+McLgb7GFhvw== From: Jisheng Zhang To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] riscv: cmpxchg: implement arch_cmpxchg64_{relaxed|acquire|release} Date: Sat, 25 Nov 2023 16:21:44 +0800 Message-Id: <20231125082144.311-3-jszhang@kernel.org> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20231125082144.311-1-jszhang@kernel.org> References: <20231125082144.311-1-jszhang@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" After selecting ARCH_USE_CMPXCHG_LOCKREF, one straight futher optimization is implementing the arch_cmpxchg64_relaxed() because the lockref code does not need the cmpxchg to have barrier semantics. At the same time, implement arch_cmpxchg64_acquire and arch_cmpxchg64_release as well. However, on both TH1520 and JH7110 platforms, I didn't see obvious performance improvement with Linus' test case [1]. IMHO, this may be related with the fence and lr.d/sc.d hw implementations. In theory, lr/sc without fence could give performance improvement over lr/sc plus fence, so add the code here to leave performance improvement room on newer HW platforms. Link: http://marc.info/?l=3Dlinux-fsdevel&m=3D137782380714721&w=3D4 [1] Signed-off-by: Jisheng Zhang --- arch/riscv/include/asm/cmpxchg.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 2f4726d3cfcc..6318187f426f 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -360,4 +360,22 @@ arch_cmpxchg_relaxed((ptr), (o), (n)); \ }) =20 +#define arch_cmpxchg64_relaxed(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_relaxed((ptr), (o), (n)); \ +}) + +#define arch_cmpxchg64_acquire(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_acquire((ptr), (o), (n)); \ +}) + +#define arch_cmpxchg64_release(ptr, o, n) \ +({ \ + BUILD_BUG_ON(sizeof(*(ptr)) !=3D 8); \ + arch_cmpxchg_release((ptr), (o), (n)); \ +}) + #endif /* _ASM_RISCV_CMPXCHG_H */ --=20 2.42.0