From nobody Wed Dec 17 13:54:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 428B7C07CA9 for ; Sat, 25 Nov 2023 15:59:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232302AbjKYP7e (ORCPT ); Sat, 25 Nov 2023 10:59:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232240AbjKYP7a (ORCPT ); Sat, 25 Nov 2023 10:59:30 -0500 Received: from mail-ed1-x52d.google.com (mail-ed1-x52d.google.com [IPv6:2a00:1450:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7762B102 for ; Sat, 25 Nov 2023 07:59:35 -0800 (PST) Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-54af61f2a40so2000134a12.3 for ; Sat, 25 Nov 2023 07:59:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1700927974; x=1701532774; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=O4pElWqIqFlDp024Egrl//ZXJVOtayIEughV58ltSNs=; b=AOzxvlOoAn2Voj9wMRMfosgDumXRbDGMnCGjDhMRhF31Y0MxkLhVdrANH8dDsn0G/P 4BDHJ9jntDUJPukFNdY/CnZmHKifwECaXpwe5+mqh4+NixWlKMe/9xAgpbPxoJ4evnRk iGQBnzZFJCbufZpfXtza1Vqxkcc56H/vhEkNpfQl0zFNCiUI6nsgybhFAih1kYG94Yyl dmo8A7tFa+AQ3iKE8N6E++fZ+au6iNawuzD7Oe0jouAteWSmYagc6jTUYu7i469T9jAA +bED0rk9BJvwtj9V0rP3ZjYw0I6O1pdCeD8HKfPeiElyA+YYpCb9Y0q6Ql4MX1bN/K7J 85bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700927974; x=1701532774; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=O4pElWqIqFlDp024Egrl//ZXJVOtayIEughV58ltSNs=; b=Pviae33eG4WHTlel5wmnAthIwLZkx8LhAN6nKa1ZnygKj9bhU1I3z2hvqXEZ7KUjmg DNAh/TePB1+fY+OPGTaayWmlCY3FrjnHSjcDv+AQEh8v+gKBDXLeKv7sr8DFU4dsexVV NV39pOHh0jtleDaG4aWBa/TkFjI1VsvdjmtCQW58s1RK34whwsk0g7mWMEsh38OWwDqE a2Ytu9FSahUdJtOTetJP6vuHuiVsy77+Df9Pmcr9wJMNhKnXSBC13KmOrkh63INC7ZhK r5YZYe10oKeMTwVDQjC67UmqJUULZoexnQ+fYFPhFVhq83U4vkuYNoZGPSf0qIKvJ6EJ rMpQ== X-Gm-Message-State: AOJu0YwsL6cf991ff1X+UB2bMCJtJRAvyv8cx3j8WYk3s0+Wxv5EY7EA zcM7egjdP5Ya1ALDgInQP8xVSg== X-Google-Smtp-Source: AGHT+IERUPipftf6Z8yVowNVxHWMCmh8DdvUCCWtATFnKnNPA3PcNujFW9WhoSzz+UPDsL6xL1PviQ== X-Received: by 2002:a05:6402:2207:b0:54b:25e8:c009 with SMTP id cq7-20020a056402220700b0054b25e8c009mr1268269edb.0.1700927973897; Sat, 25 Nov 2023 07:59:33 -0800 (PST) Received: from [10.167.154.1] (178235187180.dynamic-4-waw-k-2-3-0.vectranet.pl. [178.235.187.180]) by smtp.gmail.com with ESMTPSA id g22-20020aa7c856000000b005489e55d95esm3185813edt.22.2023.11.25.07.59.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 07:59:33 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 16:59:26 +0100 Subject: [PATCH 1/2] dt-bindings: interconnect: Add Qualcomm SM6115 NoC MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231125-topic-6115icc-v1-1-fa51c0b556c9@linaro.org> References: <20231125-topic-6115icc-v1-0-fa51c0b556c9@linaro.org> In-Reply-To: <20231125-topic-6115icc-v1-0-fa51c0b556c9@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700927971; l=7174; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=SR2D/NQeXM9MiBX3FvKHFpXDhU7PzkpdRumhNfcMHAQ=; b=0BiKVcZJa37PJ9XC1RbzgyjS7oHwg5j+du7ayLevPHj47k/AeVuG7HJYrer9gWvAeJsD1hojV kjjLNCbCsaPDJXBM8A5So5zHl6V436PDkg++EdllLdy4t8cyJqhSoIS X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for Qualcomm SM6115 Network-On-Chip interconnect. Signed-off-by: Konrad Dybcio --- .../bindings/interconnect/qcom,sm6115.yaml | 128 +++++++++++++++++= ++++ include/dt-bindings/interconnect/qcom,sm6115.h | 111 ++++++++++++++++++ 2 files changed, 239 insertions(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yam= l b/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml new file mode 100644 index 000000000000..8908946eb391 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm6115.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6115 Network-On-Chip interconnect + +maintainers: + - Konrad Dybcio + +description: | + The Qualcomm SM6115 interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + reg: + maxItems: 1 + + compatible: + enum: + - qcom,sm6115-bimc + - qcom,sm6115-cnoc + - qcom,sm6115-snoc + +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + allOf: + - $ref: qcom,rpm-common.yaml# + + properties: + compatible: + enum: + - qcom,sm6115-clk-virt + - qcom,sm6115-mmrt-virt + - qcom,sm6115-mmnrt-virt + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +allOf: + - $ref: qcom,rpm-common.yaml# + - if: + properties: + compatible: + const: qcom,sm6115-cnoc + + then: + properties: + clocks: + items: + - description: USB-NoC AXI clock + + clock-names: + items: + - const: usb_axi + + - if: + properties: + compatible: + const: qcom,sm6115-snoc + + then: + properties: + clocks: + items: + - description: CPU-NoC AXI clock. + - description: UFS-NoC AXI clock. + - description: USB-NoC AXI clock. + - description: IPA clock. + + clock-names: + items: + - const: cpu_axi + - const: ufs_axi + - const: usb_axi + - const: ipa + +examples: + - | + #include + + snoc: interconnect@1880000 { + compatible =3D "qcom,sm6115-snoc"; + reg =3D <0x01880000 0x60200>; + #interconnect-cells =3D <1>; + + qup_virt: interconnect-qup { + compatible =3D "qcom,sm6115-qup-virt"; + #interconnect-cells =3D <1>; + }; + + mmnrt_virt: interconnect-mmnrt { + compatible =3D "qcom,sm6115-mmnrt-virt"; + #interconnect-cells =3D <1>; + }; + + mmrt_virt: interconnect-mmrt { + compatible =3D "qcom,sm6115-mmrt-virt"; + #interconnect-cells =3D <1>; + }; + }; + + cnoc: interconnect@1900000 { + compatible =3D "qcom,sm6115-cnoc"; + reg =3D <0x01900000 0x8200>; + #interconnect-cells =3D <1>; + }; + + bimc: interconnect@4480000 { + compatible =3D "qcom,sm6115-bimc"; + reg =3D <0x04480000 0x80000>; + #interconnect-cells =3D <1>; + }; diff --git a/include/dt-bindings/interconnect/qcom,sm6115.h b/include/dt-bi= ndings/interconnect/qcom,sm6115.h new file mode 100644 index 000000000000..21090e585f05 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,sm6115.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_SM6115_H + +/* BIMC */ +#define MASTER_AMPSS_M0 0 +#define MASTER_SNOC_BIMC_RT 1 +#define MASTER_SNOC_BIMC_NRT 2 +#define SNOC_BIMC_MAS 3 +#define MASTER_GRAPHICS_3D 4 +#define MASTER_TCU_0 5 +#define SLAVE_EBI_CH0 6 +#define BIMC_SNOC_SLV 7 + +/* CNOC */ +#define SNOC_CNOC_MAS 0 +#define MASTER_QDSS_DAP 1 +#define SLAVE_AHB2PHY_USB 2 +#define SLAVE_APSS_THROTTLE_CFG 3 +#define SLAVE_BIMC_CFG 4 +#define SLAVE_BOOT_ROM 5 +#define SLAVE_CAMERA_NRT_THROTTLE_CFG 6 +#define SLAVE_CAMERA_RT_THROTTLE_CFG 7 +#define SLAVE_CAMERA_CFG 8 +#define SLAVE_CLK_CTL 9 +#define SLAVE_RBCPR_CX_CFG 10 +#define SLAVE_RBCPR_MX_CFG 11 +#define SLAVE_CRYPTO_0_CFG 12 +#define SLAVE_DCC_CFG 13 +#define SLAVE_DDR_PHY_CFG 14 +#define SLAVE_DDR_SS_CFG 15 +#define SLAVE_DISPLAY_CFG 16 +#define SLAVE_DISPLAY_THROTTLE_CFG 17 +#define SLAVE_GPU_CFG 18 +#define SLAVE_GPU_THROTTLE_CFG 19 +#define SLAVE_HWKM_CORE 20 +#define SLAVE_IMEM_CFG 21 +#define SLAVE_IPA_CFG 22 +#define SLAVE_LPASS 23 +#define SLAVE_MAPSS 24 +#define SLAVE_MDSP_MPU_CFG 25 +#define SLAVE_MESSAGE_RAM 26 +#define SLAVE_CNOC_MSS 27 +#define SLAVE_PDM 28 +#define SLAVE_PIMEM_CFG 29 +#define SLAVE_PKA_CORE 30 +#define SLAVE_PMIC_ARB 31 +#define SLAVE_QDSS_CFG 32 +#define SLAVE_QM_CFG 33 +#define SLAVE_QM_MPU_CFG 34 +#define SLAVE_QPIC 35 +#define SLAVE_QUP_0 36 +#define SLAVE_RPM 37 +#define SLAVE_SDCC_1 38 +#define SLAVE_SDCC_2 39 +#define SLAVE_SECURITY 40 +#define SLAVE_SNOC_CFG 41 +#define SLAVE_TCSR 42 +#define SLAVE_TLMM 43 +#define SLAVE_USB3 44 +#define SLAVE_VENUS_CFG 45 +#define SLAVE_VENUS_THROTTLE_CFG 46 +#define SLAVE_VSENSE_CTRL_CFG 47 +#define SLAVE_SERVICE_CNOC 48 + +/* SNOC */ +#define MASTER_CRYPTO_CORE0 0 +#define MASTER_SNOC_CFG 1 +#define MASTER_TIC 2 +#define MASTER_ANOC_SNOC 3 +#define BIMC_SNOC_MAS 4 +#define MASTER_PIMEM 5 +#define MASTER_QDSS_BAM 6 +#define MASTER_QPIC 7 +#define MASTER_QUP_0 8 +#define MASTER_IPA 9 +#define MASTER_QDSS_ETR 10 +#define MASTER_SDCC_1 11 +#define MASTER_SDCC_2 12 +#define MASTER_USB3 13 +#define SLAVE_APPSS 14 +#define SNOC_CNOC_SLV 15 +#define SLAVE_OCIMEM 16 +#define SLAVE_PIMEM 17 +#define SNOC_BIMC_SLV 18 +#define SLAVE_SERVICE_SNOC 19 +#define SLAVE_QDSS_STM 20 +#define SLAVE_TCU 21 +#define SLAVE_ANOC_SNOC 22 + +/* CLK Virtual */ +#define MASTER_QUP_CORE_0 0 +#define SLAVE_QUP_CORE_0 1 + +/* MMRT Virtual */ +#define MASTER_CAMNOC_HF 0 +#define MASTER_MDP_PORT0 1 +#define SLAVE_SNOC_BIMC_RT 2 + +/* MMNRT Virtual */ +#define MASTER_CAMNOC_SF 0 +#define MASTER_VIDEO_P0 1 +#define MASTER_VIDEO_PROC 2 +#define SLAVE_SNOC_BIMC_NRT 3 + +#endif --=20 2.43.0 From nobody Wed Dec 17 13:54:31 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7935DC4167B for ; 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[178.235.187.180]) by smtp.gmail.com with ESMTPSA id g22-20020aa7c856000000b005489e55d95esm3185813edt.22.2023.11.25.07.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 25 Nov 2023 07:59:35 -0800 (PST) From: Konrad Dybcio Date: Sat, 25 Nov 2023 16:59:27 +0100 Subject: [PATCH 2/2] interconnect: qcom: Add SM6115 interconnect provider driver MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231125-topic-6115icc-v1-2-fa51c0b556c9@linaro.org> References: <20231125-topic-6115icc-v1-0-fa51c0b556c9@linaro.org> In-Reply-To: <20231125-topic-6115icc-v1-0-fa51c0b556c9@linaro.org> To: Andy Gross , Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Marijn Suijten , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1700927971; l=37787; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Ou2SXxyldAGZxRoCSNYxhGfmcJhpeKdxh9XfF5e/icg=; b=G3Pu94jrUWp6m7k9ltH9obQTWJ6rEQQEeEcpE+7xIDEoE6ehRQTbmYZIIwb8e34KIS7Oz4K1p cLgCxToR/QLCyhnhCFLM6of8/95pWZRhtPiJnPdPBgW4kbSanrnDQ7R X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a driver for managing NoC providers on SM6115. Signed-off-by: Konrad Dybcio --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/sm6115.c | 1427 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1438 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 4d15ce2dab16..697f96c49f6f 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -191,6 +191,15 @@ config INTERCONNECT_QCOM_SDX75 This is a driver for the Qualcomm Network-on-Chip on sdx75-based platforms. =20 +config INTERCONNECT_QCOM_SM6115 + tristate "Qualcomm SM6115 interconnect driver" + depends on INTERCONNECT_QCOM + depends on QCOM_SMD_RPM + select INTERCONNECT_QCOM_SMD_RPM + help + This is a driver for the Qualcomm Network-on-Chip on sm6115-based + platforms. + config INTERCONNECT_QCOM_SM6350 tristate "Qualcomm SM6350 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 3a8a6ef67543..704846165022 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -24,6 +24,7 @@ qnoc-sdm845-objs :=3D sdm845.o qnoc-sdx55-objs :=3D sdx55.o qnoc-sdx65-objs :=3D sdx65.o qnoc-sdx75-objs :=3D sdx75.o +qnoc-sm6115-objs :=3D sm6115.o qnoc-sm6350-objs :=3D sm6350.o qnoc-sm8150-objs :=3D sm8150.o qnoc-sm8250-objs :=3D sm8250.o @@ -55,6 +56,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) +=3D qnoc-sdm845.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) +=3D qnoc-sdx55.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) +=3D qnoc-sdx65.o obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) +=3D qnoc-sdx75.o +obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) +=3D qnoc-sm6115.o obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) +=3D qnoc-sm6350.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) +=3D qnoc-sm8150.o obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) +=3D qnoc-sm8250.o diff --git a/drivers/interconnect/qcom/sm6115.c b/drivers/interconnect/qcom= /sm6115.c new file mode 100644 index 000000000000..c0ec20862bd3 --- /dev/null +++ b/drivers/interconnect/qcom/sm6115.c @@ -0,0 +1,1427 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "icc-rpm.h" + +static const char * const snoc_intf_clocks[] =3D { + "cpu_axi", + "ufs_axi", + "usb_axi", + "ipa", /* Required by qxm_ipa */ +}; + +static const char * const cnoc_intf_clocks[] =3D { + "usb_axi", +}; + +enum { + SM6115_MASTER_AMPSS_M0, + SM6115_MASTER_ANOC_SNOC, + SM6115_MASTER_BIMC_SNOC, + SM6115_MASTER_CAMNOC_HF, + SM6115_MASTER_CAMNOC_SF, + SM6115_MASTER_CRYPTO_CORE0, + SM6115_MASTER_GRAPHICS_3D, + SM6115_MASTER_IPA, + SM6115_MASTER_MDP_PORT0, + SM6115_MASTER_PIMEM, + SM6115_MASTER_QDSS_BAM, + SM6115_MASTER_QDSS_DAP, + SM6115_MASTER_QDSS_ETR, + SM6115_MASTER_QPIC, + SM6115_MASTER_QUP_0, + SM6115_MASTER_QUP_CORE_0, + SM6115_MASTER_SDCC_1, + SM6115_MASTER_SDCC_2, + SM6115_MASTER_SNOC_BIMC_NRT, + SM6115_MASTER_SNOC_BIMC_RT, + SM6115_MASTER_SNOC_BIMC, + SM6115_MASTER_SNOC_CFG, + SM6115_MASTER_SNOC_CNOC, + SM6115_MASTER_TCU_0, + SM6115_MASTER_TIC, + SM6115_MASTER_USB3, + SM6115_MASTER_VIDEO_P0, + SM6115_MASTER_VIDEO_PROC, + + SM6115_SLAVE_AHB2PHY_USB, + SM6115_SLAVE_ANOC_SNOC, + SM6115_SLAVE_APPSS, + SM6115_SLAVE_APSS_THROTTLE_CFG, + SM6115_SLAVE_BIMC_CFG, + SM6115_SLAVE_BIMC_SNOC, + SM6115_SLAVE_BOOT_ROM, + SM6115_SLAVE_CAMERA_CFG, + SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6115_SLAVE_CLK_CTL, + SM6115_SLAVE_CNOC_MSS, + SM6115_SLAVE_CRYPTO_0_CFG, + SM6115_SLAVE_DCC_CFG, + SM6115_SLAVE_DDR_PHY_CFG, + SM6115_SLAVE_DDR_SS_CFG, + SM6115_SLAVE_DISPLAY_CFG, + SM6115_SLAVE_DISPLAY_THROTTLE_CFG, + SM6115_SLAVE_EBI_CH0, + SM6115_SLAVE_GPU_CFG, + SM6115_SLAVE_GPU_THROTTLE_CFG, + SM6115_SLAVE_HWKM_CORE, + SM6115_SLAVE_IMEM_CFG, + SM6115_SLAVE_IPA_CFG, + SM6115_SLAVE_LPASS, + SM6115_SLAVE_MAPSS, + SM6115_SLAVE_MDSP_MPU_CFG, + SM6115_SLAVE_MESSAGE_RAM, + SM6115_SLAVE_OCIMEM, + SM6115_SLAVE_PDM, + SM6115_SLAVE_PIMEM_CFG, + SM6115_SLAVE_PIMEM, + SM6115_SLAVE_PKA_CORE, + SM6115_SLAVE_PMIC_ARB, + SM6115_SLAVE_QDSS_CFG, + SM6115_SLAVE_QDSS_STM, + SM6115_SLAVE_QM_CFG, + SM6115_SLAVE_QM_MPU_CFG, + SM6115_SLAVE_QPIC, + SM6115_SLAVE_QUP_0, + SM6115_SLAVE_QUP_CORE_0, + SM6115_SLAVE_RBCPR_CX_CFG, + SM6115_SLAVE_RBCPR_MX_CFG, + SM6115_SLAVE_RPM, + SM6115_SLAVE_SDCC_1, + SM6115_SLAVE_SDCC_2, + SM6115_SLAVE_SECURITY, + SM6115_SLAVE_SERVICE_CNOC, + SM6115_SLAVE_SERVICE_SNOC, + SM6115_SLAVE_SNOC_BIMC_NRT, + SM6115_SLAVE_SNOC_BIMC_RT, + SM6115_SLAVE_SNOC_BIMC, + SM6115_SLAVE_SNOC_CFG, + SM6115_SLAVE_SNOC_CNOC, + SM6115_SLAVE_TCSR, + SM6115_SLAVE_TCU, + SM6115_SLAVE_TLMM, + SM6115_SLAVE_USB3, + SM6115_SLAVE_VENUS_CFG, + SM6115_SLAVE_VENUS_THROTTLE_CFG, + SM6115_SLAVE_VSENSE_CTRL_CFG, +}; + +static const u16 slv_ebi_slv_bimc_snoc_links[] =3D { + SM6115_SLAVE_EBI_CH0, + SM6115_SLAVE_BIMC_SNOC, +}; + +static struct qcom_icc_node apps_proc =3D { + .name =3D "apps_proc", + .id =3D SM6115_MASTER_AMPSS_M0, + .channels =3D 1, + .buswidth =3D 16, + .qos.qos_port =3D 0, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.prio_level =3D 0, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D 0, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), + .links =3D slv_ebi_slv_bimc_snoc_links, +}; + +static const u16 link_slv_ebi[] =3D { + SM6115_SLAVE_EBI_CH0, +}; + +static struct qcom_icc_node mas_snoc_bimc_rt =3D { + .name =3D "mas_snoc_bimc_rt", + .id =3D SM6115_MASTER_SNOC_BIMC_RT, + .channels =3D 1, + .buswidth =3D 16, + .qos.qos_port =3D 2, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_ebi), + .links =3D link_slv_ebi, +}; + +static struct qcom_icc_node mas_snoc_bimc_nrt =3D { + .name =3D "mas_snoc_bimc_nrt", + .id =3D SM6115_MASTER_SNOC_BIMC_NRT, + .channels =3D 1, + .buswidth =3D 16, + .qos.qos_port =3D 3, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_ebi), + .links =3D link_slv_ebi, +}; + +static struct qcom_icc_node mas_snoc_bimc =3D { + .name =3D "mas_snoc_bimc", + .id =3D SM6115_MASTER_SNOC_BIMC, + .channels =3D 1, + .buswidth =3D 16, + .qos.qos_port =3D 6, + .qos.qos_mode =3D NOC_QOS_MODE_BYPASS, + .qos.areq_prio =3D 0, + .qos.prio_level =3D 0, + .mas_rpm_id =3D 3, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_ebi), + .links =3D link_slv_ebi, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .id =3D SM6115_MASTER_GRAPHICS_3D, + .channels =3D 1, + .buswidth =3D 32, + .qos.qos_port =3D 1, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.prio_level =3D 0, + .qos.areq_prio =3D 0, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), + .links =3D slv_ebi_slv_bimc_snoc_links, +}; + +static struct qcom_icc_node tcu_0 =3D { + .name =3D "tcu_0", + .id =3D SM6115_MASTER_TCU_0, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 4, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.prio_level =3D 6, + .qos.areq_prio =3D 6, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(slv_ebi_slv_bimc_snoc_links), + .links =3D slv_ebi_slv_bimc_snoc_links, +}; + +static const u16 qup_core_0_links[] =3D { + SM6115_SLAVE_QUP_CORE_0, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .id =3D SM6115_MASTER_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D 170, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(qup_core_0_links), + .links =3D qup_core_0_links, +}; + +static const u16 link_slv_anoc_snoc[] =3D { + SM6115_SLAVE_ANOC_SNOC, +}; + +static struct qcom_icc_node crypto_c0 =3D { + .name =3D "crypto_c0", + .id =3D SM6115_MASTER_CRYPTO_CORE0, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 43, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D 23, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static const u16 mas_snoc_cnoc_links[] =3D { + SM6115_SLAVE_AHB2PHY_USB, + SM6115_SLAVE_APSS_THROTTLE_CFG, + SM6115_SLAVE_BIMC_CFG, + SM6115_SLAVE_BOOT_ROM, + SM6115_SLAVE_CAMERA_CFG, + SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, + SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, + SM6115_SLAVE_CLK_CTL, + SM6115_SLAVE_CNOC_MSS, + SM6115_SLAVE_CRYPTO_0_CFG, + SM6115_SLAVE_DCC_CFG, + SM6115_SLAVE_DDR_PHY_CFG, + SM6115_SLAVE_DDR_SS_CFG, + SM6115_SLAVE_DISPLAY_CFG, + SM6115_SLAVE_DISPLAY_THROTTLE_CFG, + SM6115_SLAVE_GPU_CFG, + SM6115_SLAVE_GPU_THROTTLE_CFG, + SM6115_SLAVE_HWKM_CORE, + SM6115_SLAVE_IMEM_CFG, + SM6115_SLAVE_IPA_CFG, + SM6115_SLAVE_LPASS, + SM6115_SLAVE_MAPSS, + SM6115_SLAVE_MDSP_MPU_CFG, + SM6115_SLAVE_MESSAGE_RAM, + SM6115_SLAVE_PDM, + SM6115_SLAVE_PIMEM_CFG, + SM6115_SLAVE_PKA_CORE, + SM6115_SLAVE_PMIC_ARB, + SM6115_SLAVE_QDSS_CFG, + SM6115_SLAVE_QM_CFG, + SM6115_SLAVE_QM_MPU_CFG, + SM6115_SLAVE_QPIC, + SM6115_SLAVE_QUP_0, + SM6115_SLAVE_RBCPR_CX_CFG, + SM6115_SLAVE_RBCPR_MX_CFG, + SM6115_SLAVE_RPM, + SM6115_SLAVE_SDCC_1, + SM6115_SLAVE_SDCC_2, + SM6115_SLAVE_SECURITY, + SM6115_SLAVE_SERVICE_CNOC, + SM6115_SLAVE_SNOC_CFG, + SM6115_SLAVE_TCSR, + SM6115_SLAVE_TLMM, + SM6115_SLAVE_USB3, + SM6115_SLAVE_VENUS_CFG, + SM6115_SLAVE_VENUS_THROTTLE_CFG, + SM6115_SLAVE_VSENSE_CTRL_CFG, +}; + +static struct qcom_icc_node mas_snoc_cnoc =3D { + .name =3D "mas_snoc_cnoc", + .id =3D SM6115_MASTER_SNOC_CNOC, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_snoc_cnoc_links), + .links =3D mas_snoc_cnoc_links, +}; + +static struct qcom_icc_node xm_dap =3D { + .name =3D "xm_dap", + .id =3D SM6115_MASTER_QDSS_DAP, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_snoc_cnoc_links), + .links =3D mas_snoc_cnoc_links, +}; + +static const u16 link_slv_snoc_bimc_nrt[] =3D { + SM6115_SLAVE_SNOC_BIMC_NRT, +}; + +static struct qcom_icc_node qnm_camera_nrt =3D { + .name =3D "qnm_camera_nrt", + .id =3D SM6115_MASTER_CAMNOC_SF, + .channels =3D 1, + .buswidth =3D 32, + .qos.qos_port =3D 25, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 3, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_snoc_bimc_nrt), + .links =3D link_slv_snoc_bimc_nrt, +}; + +static struct qcom_icc_node qxm_venus0 =3D { + .name =3D "qxm_venus0", + .id =3D SM6115_MASTER_VIDEO_P0, + .channels =3D 1, + .buswidth =3D 16, + .qos.qos_port =3D 30, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 3, + .qos.urg_fwd_en =3D true, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_snoc_bimc_nrt), + .links =3D link_slv_snoc_bimc_nrt, +}; + +static struct qcom_icc_node qxm_venus_cpu =3D { + .name =3D "qxm_venus_cpu", + .id =3D SM6115_MASTER_VIDEO_PROC, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 34, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_snoc_bimc_nrt), + .links =3D link_slv_snoc_bimc_nrt, +}; + +static const u16 link_slv_snoc_bimc_rt[] =3D { + SM6115_SLAVE_SNOC_BIMC_RT, +}; + +static struct qcom_icc_node qnm_camera_rt =3D { + .name =3D "qnm_camera_rt", + .id =3D SM6115_MASTER_CAMNOC_HF, + .channels =3D 1, + .buswidth =3D 32, + .qos.qos_port =3D 31, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 3, + .qos.urg_fwd_en =3D true, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_snoc_bimc_rt), + .links =3D link_slv_snoc_bimc_rt, +}; + +static struct qcom_icc_node qxm_mdp0 =3D { + .name =3D "qxm_mdp0", + .id =3D SM6115_MASTER_MDP_PORT0, + .channels =3D 1, + .buswidth =3D 16, + .qos.qos_port =3D 26, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 3, + .qos.urg_fwd_en =3D true, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_snoc_bimc_rt), + .links =3D link_slv_snoc_bimc_rt, +}; + +static const u16 slv_service_snoc_links[] =3D { + SM6115_SLAVE_SERVICE_SNOC, +}; + +static struct qcom_icc_node qhm_snoc_cfg =3D { + .name =3D "qhm_snoc_cfg", + .id =3D SM6115_MASTER_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(slv_service_snoc_links), + .links =3D slv_service_snoc_links, +}; + +static const u16 mas_tic_links[] =3D { + SM6115_SLAVE_APPSS, + SM6115_SLAVE_OCIMEM, + SM6115_SLAVE_PIMEM, + SM6115_SLAVE_QDSS_STM, + SM6115_SLAVE_TCU, + SM6115_SLAVE_SNOC_BIMC, + SM6115_SLAVE_SNOC_CNOC, +}; + +static struct qcom_icc_node qhm_tic =3D { + .name =3D "qhm_tic", + .id =3D SM6115_MASTER_TIC, + .channels =3D 1, + .buswidth =3D 4, + .qos.qos_port =3D 29, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_tic_links), + .links =3D mas_tic_links, +}; + +static struct qcom_icc_node mas_anoc_snoc =3D { + .name =3D "mas_anoc_snoc", + .id =3D SM6115_MASTER_ANOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_tic_links), + .links =3D mas_tic_links, +}; + +static const u16 mas_bimc_snoc_links[] =3D { + SM6115_SLAVE_APPSS, + SM6115_SLAVE_SNOC_CNOC, + SM6115_SLAVE_OCIMEM, + SM6115_SLAVE_PIMEM, + SM6115_SLAVE_QDSS_STM, + SM6115_SLAVE_TCU, +}; + +static struct qcom_icc_node mas_bimc_snoc =3D { + .name =3D "mas_bimc_snoc", + .id =3D SM6115_MASTER_BIMC_SNOC, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D 21, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_bimc_snoc_links), + .links =3D mas_bimc_snoc_links, +}; + +static const u16 mas_pimem_links[] =3D { + SM6115_SLAVE_OCIMEM, + SM6115_SLAVE_SNOC_BIMC, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .id =3D SM6115_MASTER_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 41, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(mas_pimem_links), + .links =3D mas_pimem_links, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .id =3D SM6115_MASTER_QDSS_BAM, + .channels =3D 1, + .buswidth =3D 4, + .qos.qos_port =3D 23, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static struct qcom_icc_node qhm_qpic =3D { + .name =3D "qhm_qpic", + .id =3D SM6115_MASTER_QPIC, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .id =3D SM6115_MASTER_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .qos.qos_port =3D 21, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D 166, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .id =3D SM6115_MASTER_IPA, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 24, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D 59, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static struct qcom_icc_node xm_qdss_etr =3D { + .name =3D "xm_qdss_etr", + .id =3D SM6115_MASTER_QDSS_ETR, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 33, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static struct qcom_icc_node xm_sdc1 =3D { + .name =3D "xm_sdc1", + .id =3D SM6115_MASTER_SDCC_1, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 38, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D 33, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .id =3D SM6115_MASTER_SDCC_2, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 44, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D 35, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .id =3D SM6115_MASTER_USB3, + .channels =3D 1, + .buswidth =3D 8, + .qos.qos_port =3D 45, + .qos.qos_mode =3D NOC_QOS_MODE_FIXED, + .qos.areq_prio =3D 2, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(link_slv_anoc_snoc), + .links =3D link_slv_anoc_snoc, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .id =3D SM6115_SLAVE_EBI_CH0, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 0, +}; + +static const u16 slv_bimc_snoc_links[] =3D { + SM6115_MASTER_BIMC_SNOC, +}; + +static struct qcom_icc_node slv_bimc_snoc =3D { + .name =3D "slv_bimc_snoc", + .id =3D SM6115_SLAVE_BIMC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 2, + .num_links =3D ARRAY_SIZE(slv_bimc_snoc_links), + .links =3D slv_bimc_snoc_links, +}; + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .id =3D SM6115_SLAVE_QUP_CORE_0, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_ahb2phy_usb =3D { + .name =3D "qhs_ahb2phy_usb", + .id =3D SM6115_SLAVE_AHB2PHY_USB, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_apss_throttle_cfg =3D { + .name =3D "qhs_apss_throttle_cfg", + .id =3D SM6115_SLAVE_APSS_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_bimc_cfg =3D { + .name =3D "qhs_bimc_cfg", + .id =3D SM6115_SLAVE_BIMC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_boot_rom =3D { + .name =3D "qhs_boot_rom", + .id =3D SM6115_SLAVE_BOOT_ROM, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_camera_nrt_throttle_cfg =3D { + .name =3D "qhs_camera_nrt_throttle_cfg", + .id =3D SM6115_SLAVE_CAMERA_NRT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_camera_rt_throttle_cfg =3D { + .name =3D "qhs_camera_rt_throttle_cfg", + .id =3D SM6115_SLAVE_CAMERA_RT_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_camera_ss_cfg =3D { + .name =3D "qhs_camera_ss_cfg", + .id =3D SM6115_SLAVE_CAMERA_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .id =3D SM6115_SLAVE_CLK_CTL, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .id =3D SM6115_SLAVE_RBCPR_CX_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_cpr_mx =3D { + .name =3D "qhs_cpr_mx", + .id =3D SM6115_SLAVE_RBCPR_MX_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .id =3D SM6115_SLAVE_CRYPTO_0_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_dcc_cfg =3D { + .name =3D "qhs_dcc_cfg", + .id =3D SM6115_SLAVE_DCC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_ddr_phy_cfg =3D { + .name =3D "qhs_ddr_phy_cfg", + .id =3D SM6115_SLAVE_DDR_PHY_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_ddr_ss_cfg =3D { + .name =3D "qhs_ddr_ss_cfg", + .id =3D SM6115_SLAVE_DDR_SS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_disp_ss_cfg =3D { + .name =3D "qhs_disp_ss_cfg", + .id =3D SM6115_SLAVE_DISPLAY_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_display_throttle_cfg =3D { + .name =3D "qhs_display_throttle_cfg", + .id =3D SM6115_SLAVE_DISPLAY_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_gpu_cfg =3D { + .name =3D "qhs_gpu_cfg", + .id =3D SM6115_SLAVE_GPU_CFG, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_gpu_throttle_cfg =3D { + .name =3D "qhs_gpu_throttle_cfg", + .id =3D SM6115_SLAVE_GPU_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_hwkm =3D { + .name =3D "qhs_hwkm", + .id =3D SM6115_SLAVE_HWKM_CORE, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .id =3D SM6115_SLAVE_IMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_ipa_cfg =3D { + .name =3D "qhs_ipa_cfg", + .id =3D SM6115_SLAVE_IPA_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_lpass =3D { + .name =3D "qhs_lpass", + .id =3D SM6115_SLAVE_LPASS, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mapss =3D { + .name =3D "qhs_mapss", + .id =3D SM6115_SLAVE_MAPSS, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mdsp_mpu_cfg =3D { + .name =3D "qhs_mdsp_mpu_cfg", + .id =3D SM6115_SLAVE_MDSP_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mesg_ram =3D { + .name =3D "qhs_mesg_ram", + .id =3D SM6115_SLAVE_MESSAGE_RAM, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_mss =3D { + .name =3D "qhs_mss", + .id =3D SM6115_SLAVE_CNOC_MSS, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .id =3D SM6115_SLAVE_PDM, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pimem_cfg =3D { + .name =3D "qhs_pimem_cfg", + .id =3D SM6115_SLAVE_PIMEM_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pka_wrapper =3D { + .name =3D "qhs_pka_wrapper", + .id =3D SM6115_SLAVE_PKA_CORE, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_pmic_arb =3D { + .name =3D "qhs_pmic_arb", + .id =3D SM6115_SLAVE_PMIC_ARB, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .id =3D SM6115_SLAVE_QDSS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qm_cfg =3D { + .name =3D "qhs_qm_cfg", + .id =3D SM6115_SLAVE_QM_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qm_mpu_cfg =3D { + .name =3D "qhs_qm_mpu_cfg", + .id =3D SM6115_SLAVE_QM_MPU_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qpic =3D { + .name =3D "qhs_qpic", + .id =3D SM6115_SLAVE_QPIC, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .id =3D SM6115_SLAVE_QUP_0, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_rpm =3D { + .name =3D "qhs_rpm", + .id =3D SM6115_SLAVE_RPM, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_sdc1 =3D { + .name =3D "qhs_sdc1", + .id =3D SM6115_SLAVE_SDCC_1, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .id =3D SM6115_SLAVE_SDCC_2, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_security =3D { + .name =3D "qhs_security", + .id =3D SM6115_SLAVE_SECURITY, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static const u16 slv_snoc_cfg_links[] =3D { + SM6115_MASTER_SNOC_CFG, +}; + +static struct qcom_icc_node qhs_snoc_cfg =3D { + .name =3D "qhs_snoc_cfg", + .id =3D SM6115_SLAVE_SNOC_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(slv_snoc_cfg_links), + .links =3D slv_snoc_cfg_links, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .id =3D SM6115_SLAVE_TCSR, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .id =3D SM6115_SLAVE_TLMM, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_usb3 =3D { + .name =3D "qhs_usb3", + .id =3D SM6115_SLAVE_USB3, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .id =3D SM6115_SLAVE_VENUS_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_venus_throttle_cfg =3D { + .name =3D "qhs_venus_throttle_cfg", + .id =3D SM6115_SLAVE_VENUS_THROTTLE_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .id =3D SM6115_SLAVE_VSENSE_CTRL_CFG, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node srvc_cnoc =3D { + .name =3D "srvc_cnoc", + .id =3D SM6115_SLAVE_SERVICE_CNOC, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static const u16 slv_snoc_bimc_nrt_links[] =3D { + SM6115_MASTER_SNOC_BIMC_NRT, +}; + +static struct qcom_icc_node slv_snoc_bimc_nrt =3D { + .name =3D "slv_snoc_bimc_nrt", + .id =3D SM6115_SLAVE_SNOC_BIMC_NRT, + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_nrt_links), + .links =3D slv_snoc_bimc_nrt_links, +}; + +static const u16 slv_snoc_bimc_rt_links[] =3D { + SM6115_MASTER_SNOC_BIMC_RT, +}; + +static struct qcom_icc_node slv_snoc_bimc_rt =3D { + .name =3D "slv_snoc_bimc_rt", + .id =3D SM6115_SLAVE_SNOC_BIMC_RT, + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_rt_links), + .links =3D slv_snoc_bimc_rt_links, +}; + +static struct qcom_icc_node qhs_apss =3D { + .name =3D "qhs_apss", + .id =3D SM6115_SLAVE_APPSS, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static const u16 slv_snoc_cnoc_links[] =3D { + SM6115_MASTER_SNOC_CNOC +}; + +static struct qcom_icc_node slv_snoc_cnoc =3D { + .name =3D "slv_snoc_cnoc", + .id =3D SM6115_SLAVE_SNOC_CNOC, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 25, + .num_links =3D ARRAY_SIZE(slv_snoc_cnoc_links), + .links =3D slv_snoc_cnoc_links, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .id =3D SM6115_SLAVE_OCIMEM, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 26, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .id =3D SM6115_SLAVE_PIMEM, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static const u16 slv_snoc_bimc_links[] =3D { + SM6115_MASTER_SNOC_BIMC, +}; + +static struct qcom_icc_node slv_snoc_bimc =3D { + .name =3D "slv_snoc_bimc", + .id =3D SM6115_SLAVE_SNOC_BIMC, + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 24, + .num_links =3D ARRAY_SIZE(slv_snoc_bimc_links), + .links =3D slv_snoc_bimc_links, +}; + +static struct qcom_icc_node srvc_snoc =3D { + .name =3D "srvc_snoc", + .id =3D SM6115_SLAVE_SERVICE_SNOC, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .id =3D SM6115_SLAVE_QDSS_STM, + .channels =3D 1, + .buswidth =3D 4, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D 30, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .id =3D SM6115_SLAVE_TCU, + .channels =3D 1, + .buswidth =3D 8, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, +}; + +static const u16 slv_anoc_snoc_links[] =3D { + SM6115_MASTER_ANOC_SNOC, +}; + +static struct qcom_icc_node slv_anoc_snoc =3D { + .name =3D "slv_anoc_snoc", + .id =3D SM6115_SLAVE_ANOC_SNOC, + .channels =3D 1, + .buswidth =3D 16, + .mas_rpm_id =3D -1, + .slv_rpm_id =3D -1, + .num_links =3D ARRAY_SIZE(slv_anoc_snoc_links), + .links =3D slv_anoc_snoc_links, +}; + +static struct qcom_icc_node *bimc_nodes[] =3D { + [MASTER_AMPSS_M0] =3D &apps_proc, + [MASTER_SNOC_BIMC_RT] =3D &mas_snoc_bimc_rt, + [MASTER_SNOC_BIMC_NRT] =3D &mas_snoc_bimc_nrt, + [SNOC_BIMC_MAS] =3D &mas_snoc_bimc, + [MASTER_GRAPHICS_3D] =3D &qnm_gpu, + [MASTER_TCU_0] =3D &tcu_0, + [SLAVE_EBI_CH0] =3D &ebi, + [BIMC_SNOC_SLV] =3D &slv_bimc_snoc, +}; + +static const struct regmap_config bimc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x80000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc sm6115_bimc =3D { + .type =3D QCOM_ICC_BIMC, + .nodes =3D bimc_nodes, + .num_nodes =3D ARRAY_SIZE(bimc_nodes), + .regmap_cfg =3D &bimc_regmap_config, + .bus_clk_desc =3D &bimc_clk, + .keep_alive =3D true, + .qos_offset =3D 0x8000, + .ab_coeff =3D 153, +}; + +static struct qcom_icc_node *config_noc_nodes[] =3D { + [SNOC_CNOC_MAS] =3D &mas_snoc_cnoc, + [MASTER_QDSS_DAP] =3D &xm_dap, + [SLAVE_AHB2PHY_USB] =3D &qhs_ahb2phy_usb, + [SLAVE_APSS_THROTTLE_CFG] =3D &qhs_apss_throttle_cfg, + [SLAVE_BIMC_CFG] =3D &qhs_bimc_cfg, + [SLAVE_BOOT_ROM] =3D &qhs_boot_rom, + [SLAVE_CAMERA_NRT_THROTTLE_CFG] =3D &qhs_camera_nrt_throttle_cfg, + [SLAVE_CAMERA_RT_THROTTLE_CFG] =3D &qhs_camera_rt_throttle_cfg, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_ss_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] =3D &qhs_cpr_cx, + [SLAVE_RBCPR_MX_CFG] =3D &qhs_cpr_mx, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_DCC_CFG] =3D &qhs_dcc_cfg, + [SLAVE_DDR_PHY_CFG] =3D &qhs_ddr_phy_cfg, + [SLAVE_DDR_SS_CFG] =3D &qhs_ddr_ss_cfg, + [SLAVE_DISPLAY_CFG] =3D &qhs_disp_ss_cfg, + [SLAVE_DISPLAY_THROTTLE_CFG] =3D &qhs_display_throttle_cfg, + [SLAVE_GPU_CFG] =3D &qhs_gpu_cfg, + [SLAVE_GPU_THROTTLE_CFG] =3D &qhs_gpu_throttle_cfg, + [SLAVE_HWKM_CORE] =3D &qhs_hwkm, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_IPA_CFG] =3D &qhs_ipa_cfg, + [SLAVE_LPASS] =3D &qhs_lpass, + [SLAVE_MAPSS] =3D &qhs_mapss, + [SLAVE_MDSP_MPU_CFG] =3D &qhs_mdsp_mpu_cfg, + [SLAVE_MESSAGE_RAM] =3D &qhs_mesg_ram, + [SLAVE_CNOC_MSS] =3D &qhs_mss, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_PIMEM_CFG] =3D &qhs_pimem_cfg, + [SLAVE_PKA_CORE] =3D &qhs_pka_wrapper, + [SLAVE_PMIC_ARB] =3D &qhs_pmic_arb, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QM_CFG] =3D &qhs_qm_cfg, + [SLAVE_QM_MPU_CFG] =3D &qhs_qm_mpu_cfg, + [SLAVE_QPIC] =3D &qhs_qpic, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_RPM] =3D &qhs_rpm, + [SLAVE_SDCC_1] =3D &qhs_sdc1, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_SECURITY] =3D &qhs_security, + [SLAVE_SNOC_CFG] =3D &qhs_snoc_cfg, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_USB3] =3D &qhs_usb3, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_VENUS_THROTTLE_CFG] =3D &qhs_venus_throttle_cfg, + [SLAVE_VSENSE_CTRL_CFG] =3D &qhs_vsense_ctrl_cfg, + [SLAVE_SERVICE_CNOC] =3D &srvc_cnoc, +}; + +static const struct regmap_config cnoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x6200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc sm6115_config_noc =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D config_noc_nodes, + .num_nodes =3D ARRAY_SIZE(config_noc_nodes), + .regmap_cfg =3D &cnoc_regmap_config, + .intf_clocks =3D cnoc_intf_clocks, + .num_intf_clocks =3D ARRAY_SIZE(cnoc_intf_clocks), + .bus_clk_desc =3D &bus_1_clk, + .keep_alive =3D true, +}; + +static struct qcom_icc_node *sys_noc_nodes[] =3D { + [MASTER_CRYPTO_CORE0] =3D &crypto_c0, + [MASTER_SNOC_CFG] =3D &qhm_snoc_cfg, + [MASTER_TIC] =3D &qhm_tic, + [MASTER_ANOC_SNOC] =3D &mas_anoc_snoc, + [BIMC_SNOC_MAS] =3D &mas_bimc_snoc, + [MASTER_PIMEM] =3D &qxm_pimem, + [MASTER_QDSS_BAM] =3D &qhm_qdss_bam, + [MASTER_QPIC] =3D &qhm_qpic, + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr, + [MASTER_SDCC_1] =3D &xm_sdc1, + [MASTER_SDCC_2] =3D &xm_sdc2, + [MASTER_USB3] =3D &xm_usb3_0, + [SLAVE_APPSS] =3D &qhs_apss, + [SNOC_CNOC_SLV] =3D &slv_snoc_cnoc, + [SLAVE_OCIMEM] =3D &qxs_imem, + [SLAVE_PIMEM] =3D &qxs_pimem, + [SNOC_BIMC_SLV] =3D &slv_snoc_bimc, + [SLAVE_SERVICE_SNOC] =3D &srvc_snoc, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, + [SLAVE_ANOC_SNOC] =3D &slv_anoc_snoc, +}; + +static const struct regmap_config sys_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x5f080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc sm6115_sys_noc =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D sys_noc_nodes, + .num_nodes =3D ARRAY_SIZE(sys_noc_nodes), + .regmap_cfg =3D &sys_noc_regmap_config, + .intf_clocks =3D snoc_intf_clocks, + .num_intf_clocks =3D ARRAY_SIZE(snoc_intf_clocks), + .bus_clk_desc =3D &bus_2_clk, + .keep_alive =3D true, +}; + +static struct qcom_icc_node *clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, +}; + +static const struct qcom_icc_desc sm6115_clk_virt =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .regmap_cfg =3D &sys_noc_regmap_config, + .bus_clk_desc =3D &qup_clk, + .keep_alive =3D true, +}; + +static struct qcom_icc_node *mmnrt_virt_nodes[] =3D { + [MASTER_CAMNOC_SF] =3D &qnm_camera_nrt, + [MASTER_VIDEO_P0] =3D &qxm_venus0, + [MASTER_VIDEO_PROC] =3D &qxm_venus_cpu, + [SLAVE_SNOC_BIMC_NRT] =3D &slv_snoc_bimc_nrt, +}; + +static const struct qcom_icc_desc sm6115_mmnrt_virt =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D mmnrt_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mmnrt_virt_nodes), + .regmap_cfg =3D &sys_noc_regmap_config, + .bus_clk_desc =3D &mmaxi_0_clk, + .keep_alive =3D true, + .ab_coeff =3D 142, +}; + +static struct qcom_icc_node *mmrt_virt_nodes[] =3D { + [MASTER_CAMNOC_HF] =3D &qnm_camera_rt, + [MASTER_MDP_PORT0] =3D &qxm_mdp0, + [SLAVE_SNOC_BIMC_RT] =3D &slv_snoc_bimc_rt, +}; + +static const struct qcom_icc_desc sm6115_mmrt_virt =3D { + .type =3D QCOM_ICC_QNOC, + .nodes =3D mmrt_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mmrt_virt_nodes), + .regmap_cfg =3D &sys_noc_regmap_config, + .bus_clk_desc =3D &mmaxi_1_clk, + .keep_alive =3D true, + .ab_coeff =3D 139, +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,sm6115-bimc", .data =3D &sm6115_bimc }, + { .compatible =3D "qcom,sm6115-clk-virt", .data =3D &sm6115_clk_virt }, + { .compatible =3D "qcom,sm6115-cnoc", .data =3D &sm6115_config_noc }, + { .compatible =3D "qcom,sm6115-mmrt-virt", .data =3D &sm6115_mmrt_virt }, + { .compatible =3D "qcom,sm6115-mmnrt-virt", .data =3D &sm6115_mmnrt_virt = }, + { .compatible =3D "qcom,sm6115-snoc", .data =3D &sm6115_sys_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qnoc_probe, + .remove_new =3D qnoc_remove, + .driver =3D { + .name =3D "qnoc-sm6115", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("SM6115 NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0