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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id q18-20020a1709060e5200b00992f2befcbcsm1709930eji.180.2023.11.23.23.22.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 23:22:05 -0800 (PST) From: Christoph Muellner To: linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Andrew Morton , Shuah Khan , Jonathan Corbet , Anup Patel , Philipp Tomsich , Andrew Jones , Guo Ren , Daniel Henrique Barboza , Conor Dooley , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Alan Stern , Andrea Parri , Will Deacon , Daniel Lustig , Peter Zijlstra Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH 1/5] RISC-V: Add basic Ssdtso support Date: Fri, 24 Nov 2023 08:21:38 +0100 Message-ID: <20231124072142.2786653-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124072142.2786653-1-christoph.muellner@vrull.eu> References: <20231124072142.2786653-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoph M=C3=BCllner Ssdtso is a RISC-V ISA extension, which allows to switch the memory consistency model from RVWMO to TSO (and back) at runtime. The active model is controlled by a DTSO bit in the {m,h,s}envcfg CSRs (per-hart state). TSO is a stronger memory ordering than RVWMO, which means that executing software that was written for RVWMO can also run under TSO without causing memory consistency issues. Since RVWMO is the default model, switching to TSO is safe. The patch introduces Ssdtso basic support: * define the relevant bits * register the the extension in hwcap/cpufeatures * extend thread_struct to keep the state across context switches * add the relevant code to store/restore the DTSO state Following the pattern of existing code, this patch also introduces a Kconfig symbol ('RISCV_ISA_SSDTSO') to disable Ssdtso support. Signed-off-by: Christoph M=C3=BCllner --- arch/riscv/Kconfig | 10 ++++ arch/riscv/include/asm/csr.h | 1 + arch/riscv/include/asm/dtso.h | 74 ++++++++++++++++++++++++++++++ arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/switch_to.h | 3 ++ arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/process.c | 4 ++ 8 files changed, 95 insertions(+) create mode 100644 arch/riscv/include/asm/dtso.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 95a2a06acc6a..c62718fa8e7f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -457,6 +457,16 @@ config RISCV_ISA_C =20 If you don't know what to do here, say Y. =20 +config RISCV_ISA_SSDTSO + bool "Ssdtso extension support for dynamic TSO memory ordering" + default y + help + Adds support to dynamically detect the presence of the Ssdtso + ISA-extension and allows user-space processes to activate/deactivate + the TSO memory ordering model at run-time. + + If you don't know what to do here, say Y. + config RISCV_ISA_SVNAPOT bool "Svnapot extension support for supervisor mode NAPOT pages" depends on 64BIT && MMU diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 306a19a5509c..2689ad6b2b60 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -194,6 +194,7 @@ /* xENVCFG flags */ #define ENVCFG_STCE (_AC(1, ULL) << 63) #define ENVCFG_PBMTE (_AC(1, ULL) << 62) +#define ENVCFG_DTSO (_AC(1, UL) << 8) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) #define ENVCFG_CBIE_SHIFT 4 diff --git a/arch/riscv/include/asm/dtso.h b/arch/riscv/include/asm/dtso.h new file mode 100644 index 000000000000..f8a758c45e05 --- /dev/null +++ b/arch/riscv/include/asm/dtso.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023 Christoph Muellner + */ + +#ifndef __ASM_RISCV_DTSO_H +#define __ASM_RISCV_DTSO_H + +#ifdef CONFIG_RISCV_ISA_SSDTSO + +#include +#include +#include + +static __always_inline bool has_dtso(void) +{ + return riscv_has_extension_unlikely(RISCV_ISA_EXT_SSDTSO); +} + +static inline bool dtso_is_enabled(void) +{ + if (has_dtso()) + return csr_read(CSR_SENVCFG) & ENVCFG_DTSO; + return 0; +} + +static inline void dtso_disable(void) +{ + if (has_dtso()) + csr_clear(CSR_SENVCFG, ENVCFG_DTSO); +} + +static inline void dtso_enable(void) +{ + if (has_dtso()) + csr_set(CSR_SENVCFG, ENVCFG_DTSO); +} + +static inline void dtso_save(struct task_struct *task) +{ + task->thread.dtso_ena =3D dtso_is_enabled(); +} + +static inline void dtso_restore(struct task_struct *task) +{ + if (task->thread.dtso_ena) + dtso_enable(); + else + dtso_disable(); +} + +static inline void __switch_to_dtso(struct task_struct *prev, + struct task_struct *next) +{ + struct pt_regs *regs; + + regs =3D task_pt_regs(prev); + dtso_save(prev); + dtso_restore(next); +} + +#else /* ! CONFIG_RISCV_ISA_SSDTSO */ + +static __always_inline bool has_dtso(void) { return false; } +static __always_inline bool dtso_is_enabled(void) { return false; } +#define dtso_disable() do { } while (0) +#define dtso_enable() do { } while (0) +#define dtso_save(task) do { } while (0) +#define dtso_restore(task) do { } while (0) +#define __switch_to_dtso(prev, next) do { } while (0) + +#endif /* CONFIG_RISCV_ISA_SSDTSO */ + +#endif /* ! __ASM_RISCV_DTSO_H */ diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 06d30526ef3b..cbf924d6dfb7 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -57,6 +57,7 @@ #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 #define RISCV_ISA_EXT_ZICOND 44 +#define RISCV_ISA_EXT_SSDTSO 45 =20 #define RISCV_ISA_EXT_MAX 64 =20 diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index f19f861cda54..79cc5e6377b8 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -84,6 +84,7 @@ struct thread_struct { unsigned long vstate_ctrl; struct __riscv_v_ext_state vstate; unsigned long align_ctl; + bool dtso_ena; /* Dynamic TSO enable */ }; =20 /* Whitelist the fstate from the task_struct for hardened usercopy */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index f90d8e42f3c7..f07180a3b533 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -81,6 +82,8 @@ do { \ __switch_to_fpu(__prev, __next); \ if (has_vector()) \ __switch_to_vector(__prev, __next); \ + if (has_dtso()) \ + __switch_to_dtso(__prev, __next); \ ((last) =3D __switch_to(__prev, __next)); \ } while (0) =20 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b3785ffc1570..381ba02689ca 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -181,6 +181,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN), __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), + __RISCV_ISA_EXT_DATA(ssdtso, RISCV_ISA_EXT_SSDTSO), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 4f21d970a129..65462b675740 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -172,6 +172,10 @@ void flush_thread(void) kfree(current->thread.vstate.datap); memset(¤t->thread.vstate, 0, sizeof(struct __riscv_v_ext_state)); #endif +#ifdef CONFIG_RISCV_ISA_SSDTSO + /* Reset DTSO state */ + current->thread.dtso_ena =3D false; +#endif } =20 void arch_release_task_struct(struct task_struct *tsk) --=20 2.41.0 From nobody Wed Dec 17 15:41:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAE84C61D97 for ; Fri, 24 Nov 2023 07:22:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343940AbjKXHWL (ORCPT ); Fri, 24 Nov 2023 02:22:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229485AbjKXHWE (ORCPT ); Fri, 24 Nov 2023 02:22:04 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 496D6D72 for ; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id q18-20020a1709060e5200b00992f2befcbcsm1709930eji.180.2023.11.23.23.22.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 23:22:07 -0800 (PST) From: Christoph Muellner To: linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Andrew Morton , Shuah Khan , Jonathan Corbet , Anup Patel , Philipp Tomsich , Andrew Jones , Guo Ren , Daniel Henrique Barboza , Conor Dooley , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Alan Stern , Andrea Parri , Will Deacon , Daniel Lustig , Peter Zijlstra Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH 2/5] RISC-V: Expose Ssdtso via hwprobe API Date: Fri, 24 Nov 2023 08:21:39 +0100 Message-ID: <20231124072142.2786653-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124072142.2786653-1-christoph.muellner@vrull.eu> References: <20231124072142.2786653-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoph M=C3=BCllner This patch adds Ssdtso to the list of extensions which are announced to user-space using te hwprobe API. Signed-off-by: Christoph M=C3=BCllner --- Documentation/arch/riscv/hwprobe.rst | 3 +++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 5 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/risc= v/hwprobe.rst index 7b2384de471f..8de3349e0ca2 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -80,6 +80,9 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported= , as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMO= s. =20 + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Ssdtso extension is supported= , as + in version v1.0-draft2 of the corresponding extension. + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performa= nce information about the selected set of processors. =20 diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uap= i/asm/hwprobe.h index b659ffcfcdb4..ed450c64e6b2 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -30,6 +30,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZBB (1 << 4) #define RISCV_HWPROBE_EXT_ZBS (1 << 5) #define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6) +#define RISCV_HWPROBE_EXT_SSDTSO (1 << 7) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index c712037dbe10..c654f43b9699 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -162,6 +162,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZBB); EXT_KEY(ZBS); EXT_KEY(ZICBOZ); + EXT_KEY(SSDTSO); #undef EXT_KEY } =20 --=20 2.41.0 From nobody Wed Dec 17 15:41:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45BB1C636CB for ; Fri, 24 Nov 2023 07:22:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344592AbjKXHWR (ORCPT ); Fri, 24 Nov 2023 02:22:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230245AbjKXHWG (ORCPT ); Fri, 24 Nov 2023 02:22:06 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 10906D7D for ; Thu, 23 Nov 2023 23:22:12 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-548d60a4d60so2107429a12.2 for ; Thu, 23 Nov 2023 23:22:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1700810530; x=1701415330; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FdW6KLqAappiJz7t43GP8yDkVw3RQUH/PCIQaxhT8io=; b=JaPG6M2A4IEO0kpsTn/OdpW3CBtu0kKymdbEzEUJ17k7UPsFaeNZ5vas5OzpzFEUaG Z9ZWJRGTX2sMXdJBTk7F97cyCdXgiB4g0ZNijBATG6qcxICsJko2DK0ge/n9ikm/DgPB pGKgufgdJjgtkqlGVsTVEHfKoR1Cxsqnrr7Q5mzyTc3LGVbTpFuoW7z/EjjXP2n6iSP0 sdGGmPiXSxVkgOTsnVJ80krylqCfLad/1UQgBlb7l1jlyM2NHF/HJTriQepxlJbAEpvH DOWWOP6XSqHBYbSLeUyFr7N53w4/VojNknqswRVKiejbEj1OxlbYojhuHwn8+/p8Ynvs li8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700810530; x=1701415330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FdW6KLqAappiJz7t43GP8yDkVw3RQUH/PCIQaxhT8io=; b=KnoNbyZIUiN+Djh0fMoQWN2gZkdghmyK3U9UnwcFqxaS6NuUI+AeTagRe22kP71mHs nRmpmOwyK12fn4W2vudaGs+WrbRdah3ptk4la8EE2BSPX7DkNZJ1JflgZ9sNhkr8N1HD puGTIdrykWHvy0wCl8l+C76biPXLgzjacc3pixR4fmqt2Zrx2M9qRqso4fyLrIjrZL3v h1Yiz9rmvTWF8LG9vyWR3ju8TWzuuATb4KcLsMxsAWb/uIY88HpX4/fsn0E5uP8RANiW f6g7Bzl9kxuHLaOLfbyMg2C7+0XFQTrDNbOn9h5+2yc18UdTkxj/GHGAwz1U3GHy0vL4 Rw2g== X-Gm-Message-State: AOJu0Yx27ty7aqQIqmT8749Lrmh0p9S1uZdUc03XnXvmP5As6tKs5P1E IhtwuE0inJyXFhShiJM1N42xEQ== X-Google-Smtp-Source: AGHT+IH6YJTwKcWKKY/43rAcT0UuuNs5BImrDdkrAupQGRjsaG9PttQVyjsPB2Eshk3SwrOXEogoeQ== X-Received: by 2002:a17:906:220c:b0:a09:e716:5ea8 with SMTP id s12-20020a170906220c00b00a09e7165ea8mr121667ejs.18.1700810530557; Thu, 23 Nov 2023 23:22:10 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id q18-20020a1709060e5200b00992f2befcbcsm1709930eji.180.2023.11.23.23.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 23:22:10 -0800 (PST) From: Christoph Muellner To: linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Andrew Morton , Shuah Khan , Jonathan Corbet , Anup Patel , Philipp Tomsich , Andrew Jones , Guo Ren , Daniel Henrique Barboza , Conor Dooley , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Alan Stern , Andrea Parri , Will Deacon , Daniel Lustig , Peter Zijlstra Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH 3/5] uapi: prctl: Add new prctl call to set/get the memory consistency model Date: Fri, 24 Nov 2023 08:21:40 +0100 Message-ID: <20231124072142.2786653-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124072142.2786653-1-christoph.muellner@vrull.eu> References: <20231124072142.2786653-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoph M=C3=BCllner Some ISAs have a weak default memory consistency model and allow to switch to a more strict model at runtime. This patch adds calls to the prctl interface which allow to get and set the current memory consistency model. The implementation follows the way other prctl calls are implemented by disabling them unless arch-specific code provides the relevant macros. Signed-off-by: Christoph M=C3=BCllner --- .../mm/dynamic-memory-consistency-model.rst | 58 +++++++++++++++++++ include/uapi/linux/prctl.h | 3 + kernel/sys.c | 12 ++++ 3 files changed, 73 insertions(+) create mode 100644 Documentation/mm/dynamic-memory-consistency-model.rst diff --git a/Documentation/mm/dynamic-memory-consistency-model.rst b/Docume= ntation/mm/dynamic-memory-consistency-model.rst new file mode 100644 index 000000000000..21675b41ec84 --- /dev/null +++ b/Documentation/mm/dynamic-memory-consistency-model.rst @@ -0,0 +1,58 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D +Dynamic memory consistency model +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D + +This document gives an overview of the userspace interface to change memory +consistency model at run-time. + + +What is a memory consistency model? +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The memory consistency model is a set of guarantees a CPU architecture +provides about (re-)ordering memory accesses. Each architecture defines +its own model and set of rules within that, which are carefully specified. +The provided guarantees have consequences for the microarchitectures (e.g., +some memory consistency models allow reordering stores after loads) and +the software executed within this model (memory consistency models that +allow reordering memory accesses provide memory barrier instructions +to enforce additional guarantees when needed explicitly). + +Details about the architecture-independent memory consistency model abstra= ction +in the Linux kernel and the use of the different types of memory barriers +can be found here: + + Documentation/memory-barriers.txt + +Two models can be in a weaker/stronger relation. I.e., a consistency +model A is weaker/stronger than another model B if A provides a subset/sup= erset +of the constraints that B provides. + +Some architectures define more than one memory consistency model. +On such architectures, switching the memory consistency model at run-time +to a stronger one is possible because software written for the weaker mode= l is +compatible with the constraints of the stronger model. + +If two models are not in a weaker/stronger relation, switching between +them will violate the consistency assumptions that the software was +written under (i.e., causing subtle bugs that are very hard to debug). + +User API via prctl +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Two prctl calls are defined to get/set the active memory consistency model: + +* prctl(PR_GET_MEMORY_CONSISTENCY_MODEL) + + Returns the active memory consistency model for the calling process/th= read. + If the architecture does not support dynamic memory consistency models, + then -1 is returned, and errno is set to EINVAL. + +* prctl(PR_SET_MEMORY_CONSISTENCY_MODEL, unsigned long new_model) + + Switches the memory consistency model for the calling process/thread + to the given model. If the architecture does not support dynamic + memory consistency models or does not support the provided model, then + -1 is returned, and errno is set to EINVAL. diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 370ed14b1ae0..579662731eaa 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -306,4 +306,7 @@ struct prctl_mm_map { # define PR_RISCV_V_VSTATE_CTRL_NEXT_MASK 0xc # define PR_RISCV_V_VSTATE_CTRL_MASK 0x1f =20 +#define PR_SET_MEMORY_CONSISTENCY_MODEL 71 +#define PR_GET_MEMORY_CONSISTENCY_MODEL 72 + #endif /* _LINUX_PRCTL_H */ diff --git a/kernel/sys.c b/kernel/sys.c index e219fcfa112d..a8a217a10767 100644 --- a/kernel/sys.c +++ b/kernel/sys.c @@ -146,6 +146,12 @@ #ifndef RISCV_V_GET_CONTROL # define RISCV_V_GET_CONTROL() (-EINVAL) #endif +#ifndef SET_MEMORY_CONSISTENCY_MODEL +# define SET_MEMORY_CONSISTENCY_MODEL (-EINVAL) +#endif +#ifndef GET_MEMORY_CONSISTENCY_MODEL +# define GET_MEMORY_CONSISTENCY_MODEL (-EINVAL) +#endif =20 /* * this is where the system-wide overflow UID and GID are defined, for @@ -2743,6 +2749,12 @@ SYSCALL_DEFINE5(prctl, int, option, unsigned long, a= rg2, unsigned long, arg3, case PR_RISCV_V_GET_CONTROL: error =3D RISCV_V_GET_CONTROL(); break; + case PR_SET_MEMORY_CONSISTENCY_MODEL: + error =3D SET_MEMORY_CONSISTENCY_MODEL(arg2); + break; + case PR_GET_MEMORY_CONSISTENCY_MODEL: + error =3D GET_MEMORY_CONSISTENCY_MODEL(); + break; default: error =3D -EINVAL; break; --=20 2.41.0 From nobody Wed Dec 17 15:41:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 926A4C61D97 for ; Fri, 24 Nov 2023 07:22:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344603AbjKXHWY (ORCPT ); Fri, 24 Nov 2023 02:22:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42912 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231283AbjKXHWH (ORCPT ); Fri, 24 Nov 2023 02:22:07 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 152F5D6C for ; Thu, 23 Nov 2023 23:22:14 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-a00a9c6f283so221572866b.0 for ; Thu, 23 Nov 2023 23:22:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; t=1700810532; x=1701415332; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SyHjshVZY4a+CzgGKu86RdRFHE9Gyk/gNKjRroh1RbA=; b=ETzqhdXi3jJHeyflpyjXWZAHLbBIRj36vUutURfKifa/kwoAXFwgtv+yC9zbisCQsu o3hrVZuZmXin6GgNe1n4+3opXe1XMa/QbFn/YGgxX+6ES3TIV3Gfv5ru9IbvsUY7cFvt weAtYQLrkywn5zcn43OUW0efN4lGfPrRIP4yVUFBh3iuCDwEdv2koR7jWTGV35vpsYB+ IxGEet++UtXe8D4UPmCXmhqgzQzUQ2slfJDZ7P11TM/5T9JSxtsbdEkom4HOuDfDnbGB axTTYKX7O9q52CqggSd25tvGUX4miqMQXdJEso7ewU17FE7UxNlLSRdTDyDEpStA9Miw XILA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700810532; x=1701415332; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SyHjshVZY4a+CzgGKu86RdRFHE9Gyk/gNKjRroh1RbA=; b=C3B/0aMKs1GpYQUDpcydTgCvDYb6ZBj6pAG1jQwLuC5WvFU4nA7ZFg8S2LRGRbXN0R B5l4rKV5yDtVtxz9bVlsk0ztbAgn9ML0HGW2waxM3irW3phmI46RAON5SOd8+RvltS8a 817XfZh5L95iu60OY8SdNNjZW+s0YCZ47BJAgV07xRzLxgdrvS2kdcQCQCCrKLJnghND emV0SCZYceEzYKArJed90MUKSy/a1cUe1GFDDDXtdS0WTnZuYgpdSiXJf9SqRhyexjp5 MU7z5h7yUlQaQm82xRTbJtPcXiZS9pTILdlVyfsD04znYLb+ffI+vOnkIhsVfkgIrpGF 0wpA== X-Gm-Message-State: AOJu0Yzd8I/SupHQYDiBA2w+KruxLadbxpD+w5ZHGEQ8An0cSUcKyvqa sg8JeXxCdPT4ub7AhKGIpC/D3c/vtFnJqjCkUxrDOC53 X-Google-Smtp-Source: AGHT+IEeR8RiraoHcQMfKVQPMc/bI/tKyEPjsNFqwM2sa2syPi4of5FlqT3IwZAKP2ce7aPUm/rHLQ== X-Received: by 2002:a17:906:651:b0:9fe:81a:c258 with SMTP id t17-20020a170906065100b009fe081ac258mr1199022ejb.26.1700810532654; Thu, 23 Nov 2023 23:22:12 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id q18-20020a1709060e5200b00992f2befcbcsm1709930eji.180.2023.11.23.23.22.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 23:22:12 -0800 (PST) From: Christoph Muellner To: linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Andrew Morton , Shuah Khan , Jonathan Corbet , Anup Patel , Philipp Tomsich , Andrew Jones , Guo Ren , Daniel Henrique Barboza , Conor Dooley , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Alan Stern , Andrea Parri , Will Deacon , Daniel Lustig , Peter Zijlstra Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH 4/5] RISC-V: Implement prctl call to set/get the memory consistency model Date: Fri, 24 Nov 2023 08:21:41 +0100 Message-ID: <20231124072142.2786653-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124072142.2786653-1-christoph.muellner@vrull.eu> References: <20231124072142.2786653-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoph M=C3=BCllner We can use the PR_{S,G}ET_MEMORY_CONSISTENCY_MODEL prctl calls to change the memory consistency model at run-time if we have Ssdtso. This patch registers RISCV_WMO and RISCV_TSO as valid arguments for these prctl calls and implements the glue code to switch between these. Signed-off-by: Christoph M=C3=BCllner --- .../mm/dynamic-memory-consistency-model.rst | 18 ++++++++++ arch/riscv/include/asm/processor.h | 7 ++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/dtso.c | 33 +++++++++++++++++++ include/uapi/linux/prctl.h | 2 ++ 5 files changed, 61 insertions(+) create mode 100644 arch/riscv/kernel/dtso.c diff --git a/Documentation/mm/dynamic-memory-consistency-model.rst b/Docume= ntation/mm/dynamic-memory-consistency-model.rst index 21675b41ec84..4a6107a4b71f 100644 --- a/Documentation/mm/dynamic-memory-consistency-model.rst +++ b/Documentation/mm/dynamic-memory-consistency-model.rst @@ -56,3 +56,21 @@ Two prctl calls are defined to get/set the active memory= consistency model: to the given model. If the architecture does not support dynamic memory consistency models or does not support the provided model, then -1 is returned, and errno is set to EINVAL. + +Supported memory consistency models +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +This section defines the memory consistency models which are supported +by the prctl interface. + +RISC-V +------ + +RISC-V uses RVWMO (RISC-V weak memory ordering) as default memory consiste= ncy +model. TSO (total store ordering) is another specified model and provides +additional ordering guarantees. Switching from RVWMO to TSO (and back) is +possible when the Ssdtso extension is available. + +* :c:macro:`PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO`: RISC-V weak memory ord= ering (default). + +* :c:macro:`PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO`: RISC-V total store ord= ering. diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 79cc5e6377b8..b0c19ddb2cfb 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -146,6 +146,13 @@ extern int set_unalign_ctl(struct task_struct *tsk, un= signed int val); #define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) #define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) =20 +#ifdef CONFIG_RISCV_ISA_SSDTSO +#define SET_MEMORY_CONSISTENCY_MODEL(arg) dtso_set_memory_ordering(arg) +#define GET_MEMORY_CONSISTENCY_MODEL() dtso_get_memory_ordering() +extern int dtso_set_memory_consistency_model(unsigned long arg); +extern int dtso_get_memory_consistency_model(void); +#endif /* CONIG_RISCV_ISA_SSDTSO */ + #endif /* __ASSEMBLY__ */ =20 #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fee22a3d1b53..17cf74ac8e21 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -63,6 +63,7 @@ obj-$(CONFIG_MMU) +=3D vdso.o vdso/ obj-$(CONFIG_RISCV_MISALIGNED) +=3D traps_misaligned.o obj-$(CONFIG_FPU) +=3D fpu.o obj-$(CONFIG_RISCV_ISA_V) +=3D vector.o +obj-$(CONFIG_RISCV_ISA_SSDTSO) +=3D dtso.o obj-$(CONFIG_SMP) +=3D smpboot.o obj-$(CONFIG_SMP) +=3D smp.o obj-$(CONFIG_SMP) +=3D cpu_ops.o diff --git a/arch/riscv/kernel/dtso.c b/arch/riscv/kernel/dtso.c new file mode 100644 index 000000000000..fcf7e2e80362 --- /dev/null +++ b/arch/riscv/kernel/dtso.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 2023 Christoph Muellner + */ + +#include +#include +#include + +int riscv_set_memory_consistency_model(unsigned long arg) +{ + switch (arg) { + case PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO: + dtso_disable(); + break; + case PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO: + if (!has_dtso()) + return -EINVAL; + dtso_enable(); + break; + default: + return -EINVAL; + } + + return 0; +} + +int riscv_get_memory_consistency_model(void) +{ + if (has_dtso() && dtso_is_enabled()) + return PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO; + return PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO; +} diff --git a/include/uapi/linux/prctl.h b/include/uapi/linux/prctl.h index 579662731eaa..20264bdc3092 100644 --- a/include/uapi/linux/prctl.h +++ b/include/uapi/linux/prctl.h @@ -308,5 +308,7 @@ struct prctl_mm_map { =20 #define PR_SET_MEMORY_CONSISTENCY_MODEL 71 #define PR_GET_MEMORY_CONSISTENCY_MODEL 72 +# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO 1 +# define PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO 2 =20 #endif /* _LINUX_PRCTL_H */ --=20 2.41.0 From nobody Wed Dec 17 15:41:09 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D545C61D97 for ; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id q18-20020a1709060e5200b00992f2befcbcsm1709930eji.180.2023.11.23.23.22.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Nov 2023 23:22:14 -0800 (PST) From: Christoph Muellner To: linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Andrew Morton , Shuah Khan , Jonathan Corbet , Anup Patel , Philipp Tomsich , Andrew Jones , Guo Ren , Daniel Henrique Barboza , Conor Dooley , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , Alan Stern , Andrea Parri , Will Deacon , Daniel Lustig , Peter Zijlstra Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [RFC PATCH 5/5] RISC-V: selftests: Add DTSO tests Date: Fri, 24 Nov 2023 08:21:42 +0100 Message-ID: <20231124072142.2786653-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231124072142.2786653-1-christoph.muellner@vrull.eu> References: <20231124072142.2786653-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Christoph M=C3=BCllner This patch tests the dynamic memory consistency model prctl() behaviour on RISC-V. It does not depend on CONFIG_RISCV_ISA_SSDTSO or the availability of Ssdtso, but will test other aspects if these are not given. Signed-off-by: Christoph M=C3=BCllner --- tools/testing/selftests/riscv/Makefile | 2 +- tools/testing/selftests/riscv/dtso/.gitignore | 1 + tools/testing/selftests/riscv/dtso/Makefile | 11 +++ tools/testing/selftests/riscv/dtso/dtso.c | 77 +++++++++++++++++++ 4 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 tools/testing/selftests/riscv/dtso/.gitignore create mode 100644 tools/testing/selftests/riscv/dtso/Makefile create mode 100644 tools/testing/selftests/riscv/dtso/dtso.c diff --git a/tools/testing/selftests/riscv/Makefile b/tools/testing/selftes= ts/riscv/Makefile index 4a9ff515a3a0..1421c21841f9 100644 --- a/tools/testing/selftests/riscv/Makefile +++ b/tools/testing/selftests/riscv/Makefile @@ -5,7 +5,7 @@ ARCH ?=3D $(shell uname -m 2>/dev/null || echo not) =20 ifneq (,$(filter $(ARCH),riscv)) -RISCV_SUBTARGETS ?=3D hwprobe vector mm +RISCV_SUBTARGETS ?=3D dtso hwprobe vector mm else RISCV_SUBTARGETS :=3D endif diff --git a/tools/testing/selftests/riscv/dtso/.gitignore b/tools/testing/= selftests/riscv/dtso/.gitignore new file mode 100644 index 000000000000..217d01679115 --- /dev/null +++ b/tools/testing/selftests/riscv/dtso/.gitignore @@ -0,0 +1 @@ +dtso diff --git a/tools/testing/selftests/riscv/dtso/Makefile b/tools/testing/se= lftests/riscv/dtso/Makefile new file mode 100644 index 000000000000..a1ffbdd3da85 --- /dev/null +++ b/tools/testing/selftests/riscv/dtso/Makefile @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (C) 2023 VRULL + +CFLAGS +=3D -I$(top_srcdir)/tools/include + +TEST_GEN_PROGS :=3D dtso + +include ../../lib.mk + +$(OUTPUT)/dtso: dtso.c ../hwprobe/sys_hwprobe.S + $(CC) -static -o$@ $(CFLAGS) $(LDFLAGS) $^ diff --git a/tools/testing/selftests/riscv/dtso/dtso.c b/tools/testing/self= tests/riscv/dtso/dtso.c new file mode 100644 index 000000000000..b9ca33ca6551 --- /dev/null +++ b/tools/testing/selftests/riscv/dtso/dtso.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* dtso - used for functional tests of memory consistency model switching + * at run-time. + * + * Copyright (c) 2023 Christoph Muellner + */ + +#include +#include +#include + +#include "../hwprobe/hwprobe.h" +#include "../../kselftest_harness.h" + +/* + * We have the following cases: + * 1) DTSO support disabed in the kernel config: + * - Ssdtso is not detected + * - {G,S}ET_MEMORY_CONSISTENCY_MODEL fails with EINVAL + * 2) DTSO support enabled and Ssdtso not available: + * - Ssdtso is not detected + * - {G,S}ET_MEMORY_CONSISTENCY_MODEL works for WMO and fails for TSO w= ith EINVAL: + * 3) DTSO support enabled and Ssdtso available + * - Ssdtso is detected + * - {G,S}ET_MEMORY_CONSISTENCY_MODEL works for WMO and TSO + */ + +TEST(dtso) +{ + struct riscv_hwprobe pair; + int ret; + bool ssdtso_configured; + bool ssdtso_available; + + ret =3D prctl(PR_GET_MEMORY_CONSISTENCY_MODEL); + if (ret < 0) { + ASSERT_EQ(errno, EINVAL); + ssdtso_configured =3D false; + } else { + ASSERT_TRUE(ret =3D=3D PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO || + ret =3D=3D PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + ssdtso_configured =3D true; + } + + pair.key =3D RISCV_HWPROBE_KEY_IMA_EXT_0; + ret =3D riscv_hwprobe(&pair, 1, 0, NULL, 0); + ASSERT_GE(ret, 0); + ASSERT_EQ(pair.key, RISCV_HWPROBE_KEY_IMA_EXT_0); + ssdtso_available =3D !!(pair.value & RISCV_HWPROBE_EXT_SSDTSO); + + if (ssdtso_configured) { + ret =3D prctl(PR_GET_MEMORY_CONSISTENCY_MODEL); + ASSERT_TRUE(ret =3D=3D PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO || + ret =3D=3D PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + + if (ssdtso_available) { + ret =3D prctl(PR_SET_MEMORY_CONSISTENCY_MODEL, + PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + ASSERT_EQ(ret, 0); + ret =3D prctl(PR_GET_MEMORY_CONSISTENCY_MODEL); + ASSERT_TRUE(ret =3D=3D PR_MEMORY_CONSISTENCY_MODEL_RISCV_TSO); + } else { + ksft_test_result_skip("Ssdtso not available\n"); + } + + ret =3D prctl(PR_SET_MEMORY_CONSISTENCY_MODEL, + PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO); + ASSERT_EQ(ret, 0); + ret =3D prctl(PR_GET_MEMORY_CONSISTENCY_MODEL); + ASSERT_TRUE(ret =3D=3D PR_MEMORY_CONSISTENCY_MODEL_RISCV_WMO); + } else { + ASSERT_EQ(ssdtso_available, false); + ksft_test_result_skip("Ssdtso not configured\n"); + } +} + +TEST_HARNESS_MAIN --=20 2.41.0