From nobody Thu Dec 18 06:01:40 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66A3AC61D97 for ; Fri, 24 Nov 2023 13:29:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235259AbjKXN2y (ORCPT ); Fri, 24 Nov 2023 08:28:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37644 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231940AbjKXN2U (ORCPT ); Fri, 24 Nov 2023 08:28:20 -0500 X-Greylist: delayed 566 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Fri, 24 Nov 2023 05:27:33 PST Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [IPv6:2001:41d0:1004:224b::b8]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1631B173B for ; Fri, 24 Nov 2023 05:27:32 -0800 (PST) X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=key1; t=1700831884; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9RrzoAEWD55Vu9YEym/LtHCmjuM1Yz6YgX98UoAgqeQ=; b=Sv8rKBcJaCmN2hGbGAi/kx1O9vrr303kCr9Ci/e4w4Ryoe/cNwfBG1ZDm7IQNyVLpAly4b BCEAH9Ih16Fd4ibn9PB1FU/zdgoWQfFre6lRUYXEN5t5renUdPKe6GTN86GjtA5UmmgvA6 1m3EBSDO4DNOxgToKUNVsUrwiWtl5/eJgzkH2xNoRejXUcaa037Da3yAOAnd51AM5bdgKp QQqmxP4DkNkVN5tJZMEPgXG24p8WvwUur0zr3ktqmy1av9C9L8IzEuHfntpDedRtx1JrnF rPyHVFDWcETuqdmTalOKKEapVpX4MxX3WjOBwEkorymT4m+DqLHhylJJ4zT1hA== From: =?utf-8?q?Alvin_=C5=A0ipraga?= Date: Fri, 24 Nov 2023 14:17:43 +0100 Subject: [PATCH v6 2/3] dt-bindings: clock: si5351: add PLL reset mode property MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231124-alvin-clk-si5351-no-pll-reset-v6-2-69b82311cb90@bang-olufsen.dk> References: <20231124-alvin-clk-si5351-no-pll-reset-v6-0-69b82311cb90@bang-olufsen.dk> In-Reply-To: <20231124-alvin-clk-si5351-no-pll-reset-v6-0-69b82311cb90@bang-olufsen.dk> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Alvin_=C5=A0ipraga?= Cc: Sebastian Hesselbarth , Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rob Herring X-Migadu-Flow: FLOW_OUT Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Alvin =C5=A0ipraga For applications where the PLL must be adjusted without glitches in the clock output(s), a new silabs,pll-reset-mode property is added. It can be used to specify whether or not the PLL should be reset after adjustment. Resetting is known to cause glitches. For compatibility with older device trees, it must be assumed that the default PLL reset mode is to unconditionally reset after adjustment. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Reviewed-by: Rob Herring Signed-off-by: Alvin =C5=A0ipraga --- .../devicetree/bindings/clock/silabs,si5351.yaml | 24 ++++++++++++++++++= ++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/D= ocumentation/devicetree/bindings/clock/silabs,si5351.yaml index 494fa49a0c1b..d3e0ec29993b 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -62,6 +62,27 @@ properties: - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). enum: [ 0, 1 ] =20 + silabs,pll-reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 2 + description: A list of cell pairs containing a PLL index and its reset= mode. + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: | + Reset mode for the PLL. Mode can be one of: + + 0 - reset whenever PLL rate is adjusted (default mode) + 1 - do not reset when PLL rate is adjusted + + In mode 1, the PLL is only reset if the silabs,pll-reset is + specified in one of the clock output child nodes that also sou= rces + the PLL. This mode may be preferable if output clocks are expe= cted + to be adjusted without glitches. + enum: [ 0, 1 ] + patternProperties: "^clkout@[0-7]$": type: object @@ -195,6 +216,9 @@ examples: /* Use XTAL input as source of PLL0 and PLL1 */ silabs,pll-source =3D <0 0>, <1 0>; =20 + /* Don't reset PLL1 on rate adjustment */ + silabs,pll-reset-mode =3D <1 1>; + /* * Overwrite CLK0 configuration with: * - 8 mA output drive strength --=20 2.42.1