From nobody Mon Dec 29 20:13:42 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C8F6C61D97 for ; Thu, 23 Nov 2023 17:44:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346027AbjKWRof (ORCPT ); Thu, 23 Nov 2023 12:44:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345778AbjKWRoH (ORCPT ); Thu, 23 Nov 2023 12:44:07 -0500 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2DDF610CA; Thu, 23 Nov 2023 09:44:13 -0800 (PST) Received: from lhrpeml500006.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4SblnK1kn3z6K8sc; Fri, 24 Nov 2023 01:42:45 +0800 (CST) Received: from SecurePC30232.china.huawei.com (10.122.247.234) by lhrpeml500006.china.huawei.com (7.191.161.198) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 23 Nov 2023 17:44:10 +0000 From: To: , , , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 08/11] memory: scrub: Add scrub control attributes for the DDR5 ECS Date: Fri, 24 Nov 2023 01:43:51 +0800 Message-ID: <20231123174355.1176-9-shiju.jose@huawei.com> X-Mailer: git-send-email 2.35.1.windows.2 In-Reply-To: <20231123174355.1176-1-shiju.jose@huawei.com> References: <20231123174355.1176-1-shiju.jose@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.234] X-ClientProxiedBy: lhrpeml100003.china.huawei.com (7.191.160.210) To lhrpeml500006.china.huawei.com (7.191.161.198) X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Shiju Jose Add scrub control attributes for the DDR5 ECS feature. The Error Check Scrub (ECS) is a feature defined in JEDEC DDR5 SDRAM Specification (JESD79-5) and allows the DRAM to internally read, correct single-bit errors, and write back corrected data bits to the DRAM array while providing transparency to error counts. The ECS control feature allows the request to configure ECS input configurations during system boot or at run-time. The ECS control allows the requester to change the ECS threshold count provided that the request is within the definition specified in DDR5 mode registers, change mode between codeword mode and row count mode, and reset the ECS counter. Signed-off-by: Shiju Jose --- drivers/memory/scrub/memory-scrub.c | 13 ++++++++++++- include/memory/memory-scrub.h | 10 ++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/memory/scrub/memory-scrub.c b/drivers/memory/scrub/mem= ory-scrub.c index c2d794b2624b..43b7da43114f 100755 --- a/drivers/memory/scrub/memory-scrub.c +++ b/drivers/memory/scrub/memory-scrub.c @@ -208,7 +208,8 @@ static bool is_hex_attr(u32 attr) =20 static bool is_string_attr(u32 attr) { - return attr =3D=3D scrub_speed_available; + return attr =3D=3D scrub_speed_available || + attr =3D=3D scrub_threshold_available; } =20 static struct attribute *scrub_genattr(const void *drvdata, @@ -269,6 +270,16 @@ static const char * const scrub_common_attrs[] =3D { [scrub_enable] =3D "enable", [scrub_speed] =3D "speed", [scrub_speed_available] =3D "speed_available", + /* scrub attributes - DDR5 ECS/common */ + [scrub_ecs_log_entry_type] =3D "ecs_log_entry_type", + [scrub_ecs_log_entry_type_per_dram] =3D "ecs_log_entry_type_per_dram", + [scrub_ecs_log_entry_type_per_memory_media] =3D "ecs_log_entry_type_per_m= emory_media", + [scrub_mode] =3D "mode", + [scrub_mode_counts_rows] =3D "mode_counts_rows", + [scrub_mode_counts_codewords] =3D "mode_counts_codewords", + [scrub_reset_counter] =3D "reset_counter", + [scrub_threshold] =3D "threshold", + [scrub_threshold_available] =3D "threshold_available", }; =20 static struct attribute ** diff --git a/include/memory/memory-scrub.h b/include/memory/memory-scrub.h index d7cbde4718d0..74ad5addd5b3 100755 --- a/include/memory/memory-scrub.h +++ b/include/memory/memory-scrub.h @@ -23,6 +23,16 @@ enum scrub_attributes { scrub_enable, scrub_speed, scrub_speed_available, + /* scrub attributes - DDR5 ECS/common */ + scrub_ecs_log_entry_type, + scrub_ecs_log_entry_type_per_dram, + scrub_ecs_log_entry_type_per_memory_media, + scrub_mode, + scrub_mode_counts_rows, + scrub_mode_counts_codewords, + scrub_reset_counter, + scrub_threshold, + scrub_threshold_available, max_attrs, }; =20 --=20 2.34.1