From nobody Tue Dec 30 02:02:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B24F5C61D9B for ; Wed, 22 Nov 2023 12:19:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344193AbjKVMTC (ORCPT ); Wed, 22 Nov 2023 07:19:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58946 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344110AbjKVMSi (ORCPT ); Wed, 22 Nov 2023 07:18:38 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C4CA10D8; Wed, 22 Nov 2023 04:18:29 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3AMCGwQb025259; Wed, 22 Nov 2023 20:16:58 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 22 Nov 2023 20:16:54 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 11/13] riscv: dts: allwinner: Add T-Head PMU extension Date: Wed, 22 Nov 2023 20:12:33 +0800 Message-ID: <20231122121235.827122-12-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122121235.827122-1-peterlin@andestech.com> References: <20231122121235.827122-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3AMCGwQb025259 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Guo Ren --- Changes v2 -> v3: - New patch Changes v3 -> v4: - No change --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boo= t/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..7dcba86cfdd0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { riscv,isa =3D "rv64imafdc"; riscv,isa-base =3D "rv64i"; riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", "zicntr", "zicsr= ", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; #cooling-cells =3D <2>; =20 cpu0_intc: interrupt-controller { --=20 2.34.1