From nobody Tue Dec 30 02:02:57 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92573C61D97 for ; Wed, 22 Nov 2023 12:19:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344194AbjKVMTF (ORCPT ); Wed, 22 Nov 2023 07:19:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344091AbjKVMSy (ORCPT ); Wed, 22 Nov 2023 07:18:54 -0500 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACFF1D4F; Wed, 22 Nov 2023 04:18:32 -0800 (PST) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3AMCGrBM025240; Wed, 22 Nov 2023 20:16:53 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Wed, 22 Nov 2023 20:16:49 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v4 10/13] dt-bindings: riscv: Add Andes PMU extension description Date: Wed, 22 Nov 2023 20:12:32 +0800 Message-ID: <20231122121235.827122-11-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122121235.827122-1-peterlin@andestech.com> References: <20231122121235.827122-1-peterlin@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DNSRBL: X-MAIL: Atcsqr.andestech.com 3AMCGrBM025240 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Document the ISA string for Andes Technology performance monitor extension which provides counter overflow interrupt and mode filtering mechanisms. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar --- Changes v2 -> v3: - New patch Changes v3 -> v4: - Include Conor's Acked-by --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 694efaea8fce..4e0066afc848 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -258,6 +258,13 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. =20 + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter= overflow + and privilege mode filtering. For more details, see Counter Re= lated + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.= 0.0-Datasheet.pdf + - const: xtheadpmu description: The T-Head performance monitor extension for counter overflow.= For more --=20 2.34.1