From nobody Wed Dec 17 20:40:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5A74C61D92 for ; Wed, 22 Nov 2023 03:30:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343604AbjKVDaf (ORCPT ); Tue, 21 Nov 2023 22:30:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343543AbjKVDae (ORCPT ); Tue, 21 Nov 2023 22:30:34 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25B4490 for ; Tue, 21 Nov 2023 19:30:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700623831; x=1732159831; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=abHIAVCO67I12DlkhVd7oB9ud5ZE5PyjC/pWsosPfw4=; b=BzQ2mmjSZoZbiMhIyTTe1JAx9MXWsqIahXGRi2cz358Ya/thXd9WhLkX ahRxzuKEGDpmXgJJmI9auINpdP3x8mE33eWh7im6bqZFX9nZbFZyRW+Be iP6UuoXbGyHV91HZ8bbX3+WT6zhOBxLzAz+AwaLMi3ZkCSbyVAjq4A1Lz koHGwWioLIyQJQOCu2FOLvhEfk9uM/sEXlnDbzZDAiqtH1tWJP4aMOTsC fPmykcBB2xPXLdGp0CUvjZHy3tH1RZr4HZchPt7Bm9z5GAWGyqvimW7s7 4WbLQEHme8b/ki99gj8MohhjdsXKoewWgnEivVLz4Rpesa5Q465LLR7c6 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="391742768" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="391742768" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 19:30:30 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="8090161" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa002.jf.intel.com with ESMTP; 21 Nov 2023 19:30:30 -0800 From: Lu Baolu To: Joerg Roedel Cc: mohd.syazwan.abdul.halim@intel.com, Kunwu Chan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 1/7] iommu/vt-d: Support enforce_cache_coherency only for empty domains Date: Wed, 22 Nov 2023 11:26:02 +0800 Message-Id: <20231122032608.165144-2-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122032608.165144-1-baolu.lu@linux.intel.com> References: <20231122032608.165144-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The enforce_cache_coherency callback ensures DMA cache coherency for devices attached to the domain. Intel IOMMU supports enforced DMA cache coherency when the Snoop Control bit in the IOMMU's extended capability register is set. Supporting it differs between legacy and scalable modes. In legacy mode, it's supported page-level by setting the SNP field in second-stage page-table entries. In scalable mode, it's supported in PASID-table granularity by setting the PGSNP field in PASID-table entries. In legacy mode, mappings before attaching to a device have SNP fields cleared, while mappings after the callback have them set. This means partial DMAs are cache coherent while others are not. One possible fix is replaying mappings and flipping SNP bits when attaching a domain to a device. But this seems to be over-engineered, given that all real use cases just attach an empty domain to a device. To meet practical needs while reducing mode differences, only support enforce_cache_coherency on a domain without mappings if SNP field is used. Fixes: fc0051cb9590 ("iommu/vt-d: Check domain force_snooping against attac= hed devices") Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20231114011036.70142-1-baolu.lu@linux.intel= .com --- drivers/iommu/intel/iommu.h | 3 +++ drivers/iommu/intel/iommu.c | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h index 65d37a138c75..ce030c5b5772 100644 --- a/drivers/iommu/intel/iommu.h +++ b/drivers/iommu/intel/iommu.h @@ -602,6 +602,9 @@ struct dmar_domain { */ u8 dirty_tracking:1; /* Dirty tracking is enabled */ u8 nested_parent:1; /* Has other domains nested on it */ + u8 has_mappings:1; /* Has mappings configured through + * iommu_map() interface. + */ =20 spinlock_t lock; /* Protect device tracking lists */ struct list_head devices; /* all devices' list */ diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 3531b956556c..11670cd812a3 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2207,6 +2207,8 @@ __domain_mapping(struct dmar_domain *domain, unsigned= long iov_pfn, attr |=3D DMA_FL_PTE_DIRTY; } =20 + domain->has_mappings =3D true; + pteval =3D ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | attr; =20 while (nr_pages > 0) { @@ -4360,7 +4362,8 @@ static bool intel_iommu_enforce_cache_coherency(struc= t iommu_domain *domain) return true; =20 spin_lock_irqsave(&dmar_domain->lock, flags); - if (!domain_support_force_snooping(dmar_domain)) { + if (!domain_support_force_snooping(dmar_domain) || + (!dmar_domain->use_first_level && dmar_domain->has_mappings)) { spin_unlock_irqrestore(&dmar_domain->lock, flags); return false; } --=20 2.34.1 From nobody Wed Dec 17 20:40:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 020D2C61D92 for ; Wed, 22 Nov 2023 03:30:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343614AbjKVDah (ORCPT ); Tue, 21 Nov 2023 22:30:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343543AbjKVDag (ORCPT ); Tue, 21 Nov 2023 22:30:36 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D40FE18C for ; Tue, 21 Nov 2023 19:30:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700623832; x=1732159832; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HFcvyEodi+fPlzWO9+8MOcJlJiNIw4yl1ellDdedZDU=; b=mCXu6BCEPVWJxYwSEWT+hpiZM/HrZyLORxOCpdBdCRV4uDSMekERy+uB 5jdqAh0Pg0zLaC1j5O3M+dQE2lwcfkPcjsJDKnPMEi8FnTNQ+4hWocnL1 3sG5/YFg4KYUULknC9fri8SjJ/Se5yAACuYAsTETRQtNDRsdm6kFJEXBO LtVBW2t3FOrL0V8nS80xeWcLkKOVatqnzMcSFJ+owG/FZaT1wVhnVdOzD 6+ITNw3ntUAl5pub1Y713cVVeAADwIbwmgCqIClJCSJXrkkacbCiOgfF8 5WfXnc+A3hPR0y54g6xL30nH/9hpABBGnxRn/TIdEdiaEXbK9qjcXP7X8 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="391742773" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="391742773" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 19:30:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="8090164" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa002.jf.intel.com with ESMTP; 21 Nov 2023 19:30:31 -0800 From: Lu Baolu To: Joerg Roedel Cc: mohd.syazwan.abdul.halim@intel.com, Kunwu Chan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 2/7] iommu/vt-d: Omit devTLB invalidation requests when TES=0 Date: Wed, 22 Nov 2023 11:26:03 +0800 Message-Id: <20231122032608.165144-3-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122032608.165144-1-baolu.lu@linux.intel.com> References: <20231122032608.165144-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The latest VT-d spec indicates that when remapping hardware is disabled (TES=3D0 in Global Status Register), upstream ATS Invalidation Completion requests are treated as UR (Unsupported Request). Consequently, the spec recommends in section 4.3 Handling of Device-TLB Invalidations that software refrain from submitting any Device-TLB invalidation requests when address remapping hardware is disabled. Verify address remapping hardware is enabled prior to submitting Device- TLB invalidation requests. Fixes: 792fb43ce2c9 ("iommu/vt-d: Enable Intel IOMMU scalable mode by defau= lt") Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20231114011036.70142-2-baolu.lu@linux.intel= .com --- drivers/iommu/intel/dmar.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c index a3414afe11b0..23cb80d62a9a 100644 --- a/drivers/iommu/intel/dmar.c +++ b/drivers/iommu/intel/dmar.c @@ -1522,6 +1522,15 @@ void qi_flush_dev_iotlb(struct intel_iommu *iommu, u= 16 sid, u16 pfsid, { struct qi_desc desc; =20 + /* + * VT-d spec, section 4.3: + * + * Software is recommended to not submit any Device-TLB invalidation + * requests while address remapping hardware is disabled. + */ + if (!(iommu->gcmd & DMA_GCMD_TE)) + return; + if (mask) { addr |=3D (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; desc.qw1 =3D QI_DEV_IOTLB_ADDR(addr) | QI_DEV_IOTLB_SIZE; @@ -1587,6 +1596,15 @@ void qi_flush_dev_iotlb_pasid(struct intel_iommu *io= mmu, u16 sid, u16 pfsid, unsigned long mask =3D 1UL << (VTD_PAGE_SHIFT + size_order - 1); struct qi_desc desc =3D {.qw1 =3D 0, .qw2 =3D 0, .qw3 =3D 0}; =20 + /* + * VT-d spec, section 4.3: + * + * Software is recommended to not submit any Device-TLB invalidation + * requests while address remapping hardware is disabled. + */ + if (!(iommu->gcmd & DMA_GCMD_TE)) + return; + desc.qw0 =3D QI_DEV_EIOTLB_PASID(pasid) | QI_DEV_EIOTLB_SID(sid) | QI_DEV_EIOTLB_QDEP(qdep) | QI_DEIOTLB_TYPE | QI_DEV_IOTLB_PFSID(pfsid); --=20 2.34.1 From nobody Wed Dec 17 20:40:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A46CFC072A2 for ; Wed, 22 Nov 2023 03:30:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343627AbjKVDak (ORCPT ); Tue, 21 Nov 2023 22:30:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343543AbjKVDai (ORCPT ); Tue, 21 Nov 2023 22:30:38 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8EA11197 for ; Tue, 21 Nov 2023 19:30:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700623834; x=1732159834; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p7LbYR2l9zkvd8N1/omkWM+xVFNd9JQUzHnkehfNbv0=; b=SjM8YVZEpDfiA3QDfYfXZkgqhHOqXC5TB/Bm/45dFiHapHU9YI5EHeBJ 28RQG6QzlTeojxrSFCBpmfNqEzqy/r0XC9k49niUs53TotyIqldS3nl1w CpcI6rn8u3yyfRRHoiw/pjFX8Qg5DalI8sAefyyh9FtGRap2AsXri4XLW OCGaDNs3WqKe0+41w+akSFsEyEniGBevfMDeXzAcGL6SjSpVfNbbrSY7n mICsNEzWcVRNmp0ek8j7iA869m6o9XitNFSPE8z4moUIyUpUWoxZNv+rb f66DE+XKM1rdjwnGTF9hCXRpj3gEFbLMP7WvE6Yg1nwWnZeh9VEBWhvTc g==; X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="391742778" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="391742778" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 19:30:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="8090170" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa002.jf.intel.com with ESMTP; 21 Nov 2023 19:30:33 -0800 From: Lu Baolu To: Joerg Roedel Cc: mohd.syazwan.abdul.halim@intel.com, Kunwu Chan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/7] iommu/vt-d: Disable PCI ATS in legacy passthrough mode Date: Wed, 22 Nov 2023 11:26:04 +0800 Message-Id: <20231122032608.165144-4-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122032608.165144-1-baolu.lu@linux.intel.com> References: <20231122032608.165144-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" When IOMMU hardware operates in legacy mode, the TT field of the context entry determines the translation type, with three supported types (Section 9.3 Context Entry): - DMA translation without device TLB support - DMA translation with device TLB support - Passthrough mode with translated and translation requests blocked Device TLB support is absent when hardware is configured in passthrough mode. Disable the PCI ATS feature when IOMMU is configured for passthrough translation type in legacy (non-scalable) mode. Fixes: 0faa19a1515f ("iommu/vt-d: Decouple PASID & PRI enabling from SVA") Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20231114011036.70142-3-baolu.lu@linux.intel= .com --- drivers/iommu/intel/iommu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 11670cd812a3..9bddd4fbbdf8 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -2492,7 +2492,8 @@ static int dmar_domain_attach_device(struct dmar_doma= in *domain, return ret; } =20 - iommu_enable_pci_caps(info); + if (sm_supported(info->iommu) || !domain_type_is_si(info->domain)) + iommu_enable_pci_caps(info); =20 return 0; } --=20 2.34.1 From nobody Wed Dec 17 20:40:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1BB70C072A2 for ; Wed, 22 Nov 2023 03:30:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343641AbjKVDas (ORCPT ); Tue, 21 Nov 2023 22:30:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343631AbjKVDak (ORCPT ); Tue, 21 Nov 2023 22:30:40 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 457A31AC for ; Tue, 21 Nov 2023 19:30:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700623836; x=1732159836; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HNzfhWQdyUFZ+2JhkpASHOjsLgru+N06mUEX2ecKBAw=; b=BjaR7wRyYoc/uxaECAiHjC3y7cvSPpiVfOSwyCdam/FLcH9TZHodU9rV 0sBQJZ7Q5g5M3jLPN2nOH/0LqbCgZr7WxdHDrPRoGrJu4aInTU9uSo6gJ 6qcnKL/xFE8IAvTlszVONB0qLVJLzH/kBr2uvFPPcgcXkU1aHjzpFms1q xOgGAeqx81q/kYrri3UfxGPN8T5F93hNE1Zv5MHXPEqgk0l0DmAxMzMoJ dLiIvSC9aNewwTdI0+4jYhxqyrXc9XAKOCroZ97OdsUjXV/V+BHfqHvaf TB6yu0ru3NJNQETadN2detsFA01d4Wi2u1cbUzDAW2rm8UN93RjkWi15u Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="391742785" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="391742785" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 19:30:36 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="8090181" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa002.jf.intel.com with ESMTP; 21 Nov 2023 19:30:35 -0800 From: Lu Baolu To: Joerg Roedel Cc: mohd.syazwan.abdul.halim@intel.com, Kunwu Chan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 4/7] iommu/vt-d: Make context clearing consistent with context mapping Date: Wed, 22 Nov 2023 11:26:05 +0800 Message-Id: <20231122032608.165144-5-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122032608.165144-1-baolu.lu@linux.intel.com> References: <20231122032608.165144-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In the iommu probe_device path, domain_context_mapping() allows setting up the context entry for a non-PCI device. However, in the iommu release_device path, domain_context_clear() only clears context entries for PCI devices. Make domain_context_clear() behave consistently with domain_context_mapping() by clearing context entries for both PCI and non-PCI devices. Fixes: 579305f75d34 ("iommu/vt-d: Update to use PCI DMA aliases") Signed-off-by: Lu Baolu Reviewed-by: Kevin Tian Link: https://lore.kernel.org/r/20231114011036.70142-4-baolu.lu@linux.intel= .com --- drivers/iommu/intel/iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 9bddd4fbbdf8..4c257ccf9dc3 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -3928,8 +3928,8 @@ static int domain_context_clear_one_cb(struct pci_dev= *pdev, u16 alias, void *op */ static void domain_context_clear(struct device_domain_info *info) { - if (!info->iommu || !info->dev || !dev_is_pci(info->dev)) - return; + if (!dev_is_pci(info->dev)) + domain_context_clear_one(info, info->bus, info->devfn); =20 pci_for_each_dma_alias(to_pci_dev(info->dev), &domain_context_clear_one_cb, info); --=20 2.34.1 From nobody Wed Dec 17 20:40:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67CCEC072A2 for ; Wed, 22 Nov 2023 03:30:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343623AbjKVDav (ORCPT ); Tue, 21 Nov 2023 22:30:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58796 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343659AbjKVDam (ORCPT ); Tue, 21 Nov 2023 22:30:42 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C258D66 for ; Tue, 21 Nov 2023 19:30:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700623838; x=1732159838; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9uOrSuBrG6UnY5yl9x5aH3IwGdyhH17pmuoXWWC5qd0=; b=XIYDsTI8SNl3rYp1/xzyDudtSICUtrXQ+mEfB2rsL0MglgknAjJ1EB0P 7YcJu1nCHdHj+7ltmO7mPoyarQFM9D75B3WZepCR6WwKhJaVdyvTxVrTX HRyo60fbErkmxuPqavEcuW5hGvSKb2YKB+SR5PWAuDDXNBtCwIWZHgsp8 c9gfwRg0BPHgYWTFOvjeArkagTMsL0BN7v8DRgfkmq2sGmV+DHZ4CLpAv 4alH6Iw1RRNA0+xhnfZhcYNHyQS6iFBb8tD1IBLGcDtUPhL6nP6RvxxE+ NQfq76SzzrMTXs+t6Ov4DIPjt6U+Qygt4vSL8PnOgRKgFtB59XkRkl0Cg g==; X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="391742797" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="391742797" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 19:30:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="8090186" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa002.jf.intel.com with ESMTP; 21 Nov 2023 19:30:37 -0800 From: Lu Baolu To: Joerg Roedel Cc: mohd.syazwan.abdul.halim@intel.com, Kunwu Chan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 5/7] iommu/vt-d: Add MTL to quirk list to skip TE disabling Date: Wed, 22 Nov 2023 11:26:06 +0800 Message-Id: <20231122032608.165144-6-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122032608.165144-1-baolu.lu@linux.intel.com> References: <20231122032608.165144-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: "Abdul Halim, Mohd Syazwan" The VT-d spec requires (10.4.4 Global Command Register, TE field) that: Hardware implementations supporting DMA draining must drain any in-flight DMA read/write requests queued within the Root-Complex before switching address translation on or off and reflecting the status of the command through the TES field in the Global Status register. Unfortunately, some integrated graphic devices fail to do so after some kind of power state transition. As the result, the system might stuck in iommu_disable_translation(), waiting for the completion of TE transition. Add MTL to the quirk list for those devices and skips TE disabling if the qurik hits. Fixes: b1012ca8dc4f ("iommu/vt-d: Skip TE disabling on quirky gfx dedicated= iommu") Cc: stable@vger.kernel.org Signed-off-by: Abdul Halim, Mohd Syazwan Signed-off-by: Lu Baolu Link: https://lore.kernel.org/r/20231116022324.30120-1-baolu.lu@linux.intel= .com --- drivers/iommu/intel/iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 4c257ccf9dc3..68f121c28fbf 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -5077,7 +5077,7 @@ static void quirk_igfx_skip_te_disable(struct pci_dev= *dev) ver =3D (dev->device >> 8) & 0xff; if (ver !=3D 0x45 && ver !=3D 0x46 && ver !=3D 0x4c && ver !=3D 0x4e && ver !=3D 0x8a && ver !=3D 0x98 && - ver !=3D 0x9a && ver !=3D 0xa7) + ver !=3D 0x9a && ver !=3D 0xa7 && ver !=3D 0x7d) return; =20 if (risky_device(dev)) --=20 2.34.1 From nobody Wed Dec 17 20:40:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 548BFC072A2 for ; Wed, 22 Nov 2023 03:30:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343559AbjKVDaz (ORCPT ); Tue, 21 Nov 2023 22:30:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343688AbjKVDap (ORCPT ); Tue, 21 Nov 2023 22:30:45 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13D3AD45 for ; Tue, 21 Nov 2023 19:30:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700623840; x=1732159840; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NBrfwbm+D/NKidPUfm+0chk1dT5BhEPaSaHHnHNJrj0=; b=nGiWSzhaCDDwzYkEPliowY7FE5g0ai6A7kMobnPC5TT0OMJN7a9QnFNh n45JnP8Fvk3QgP/Z/kkF53+ODg4OJRE8tKBxUn/7XYOXNRjkkdTbwx7Q3 CeM4WIjx8ategYHG3+EgTZzNoFI2xUNonvfiRwPia9id/XRAtHW4fL3Mc cnMrgQCVGZR6RguFMJXYGS6PXEVqX1MCAjG0JXB+E+g+pjPnsrLnDkbUj 5B6v8ILVhyY4VXLpd+7nxowf7c9NUTOz3OZbNWISZ6GZol2SZytkNwazv F6zrgeLlP+QERbTGNW3RvOy0TBhdg+vGiH0WmtMGI1M2laPsbrCKS8zah A==; X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="391742801" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="391742801" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 19:30:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="8090190" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa002.jf.intel.com with ESMTP; 21 Nov 2023 19:30:38 -0800 From: Lu Baolu To: Joerg Roedel Cc: mohd.syazwan.abdul.halim@intel.com, Kunwu Chan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 6/7] iommu/vt-d: Fix incorrect cache invalidation for mm notification Date: Wed, 22 Nov 2023 11:26:07 +0800 Message-Id: <20231122032608.165144-7-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122032608.165144-1-baolu.lu@linux.intel.com> References: <20231122032608.165144-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Commit 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when invalidating TLBs") moved the secondary TLB invalidations into the TLB invalidation functions to ensure that all secondary TLB invalidations happen at the same time as the CPU invalidation and added a flush-all type of secondary TLB invalidation for the batched mode, where a range of [0, -1UL) is used to indicates that the range extends to the end of the address space. However, using an end address of -1UL caused an overflow in the Intel IOMMU driver, where the end address was rounded up to the next page. As a result, both the IOTLB and device ATC were not invalidated correctly. Add a flush all helper function and call it when the invalidation range is from 0 to -1UL, ensuring that the entire caches are invalidated correctly. Fixes: 6bbd42e2df8f ("mmu_notifiers: call invalidate_range() when invalidat= ing TLBs") Cc: stable@vger.kernel.org Cc: Huang Ying Cc: Alistair Popple Tested-by: Luo Yuzhang # QAT Tested-by: Tony Zhu # DSA Reviewed-by: Jason Gunthorpe Reviewed-by: Alistair Popple Signed-off-by: Lu Baolu Link: https://lore.kernel.org/r/20231117090933.75267-1-baolu.lu@linux.intel= .com --- drivers/iommu/intel/svm.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/iommu/intel/svm.c b/drivers/iommu/intel/svm.c index 50a481c895b8..ac12f76c1212 100644 --- a/drivers/iommu/intel/svm.c +++ b/drivers/iommu/intel/svm.c @@ -216,6 +216,27 @@ static void intel_flush_svm_range(struct intel_svm *sv= m, unsigned long address, rcu_read_unlock(); } =20 +static void intel_flush_svm_all(struct intel_svm *svm) +{ + struct device_domain_info *info; + struct intel_svm_dev *sdev; + + rcu_read_lock(); + list_for_each_entry_rcu(sdev, &svm->devs, list) { + info =3D dev_iommu_priv_get(sdev->dev); + + qi_flush_piotlb(sdev->iommu, sdev->did, svm->pasid, 0, -1UL, 0); + if (info->ats_enabled) { + qi_flush_dev_iotlb_pasid(sdev->iommu, sdev->sid, info->pfsid, + svm->pasid, sdev->qdep, + 0, 64 - VTD_PAGE_SHIFT); + quirk_extra_dev_tlb_flush(info, 0, 64 - VTD_PAGE_SHIFT, + svm->pasid, sdev->qdep); + } + } + rcu_read_unlock(); +} + /* Pages have been freed at this point */ static void intel_arch_invalidate_secondary_tlbs(struct mmu_notifier *mn, struct mm_struct *mm, @@ -223,6 +244,11 @@ static void intel_arch_invalidate_secondary_tlbs(struc= t mmu_notifier *mn, { struct intel_svm *svm =3D container_of(mn, struct intel_svm, notifier); =20 + if (start =3D=3D 0 && end =3D=3D -1UL) { + intel_flush_svm_all(svm); + return; + } + intel_flush_svm_range(svm, start, (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0); } --=20 2.34.1 From nobody Wed Dec 17 20:40:13 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 010B8C072A2 for ; Wed, 22 Nov 2023 03:30:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343620AbjKVDa7 (ORCPT ); Tue, 21 Nov 2023 22:30:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39668 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343642AbjKVDas (ORCPT ); Tue, 21 Nov 2023 22:30:48 -0500 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AF8F9D6F for ; Tue, 21 Nov 2023 19:30:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1700623841; x=1732159841; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l8mKiuMBoMj92zKyDcAwd723ed3hnwwboBhJ8sse7us=; b=KoCXRkn3I3jEqOHOpuBkxmPX6V5YgMQxaowr6X8F7mP8XbHStGHpSv6w EvMMVBccFXUVq7FdrMaepP0iiT2ScvYO0mtimnEk+4dciEUzHsgwLTlXU h9IjqqFv4JXuUchsm6KG689XFFfQq3RXE5Lou3QEr2ZA7lG4iDt42xJLl whCkcYayCo1DlnRGdhA0ba8LYqEP2HkzvaYESpPPWyC777e1OERj96ojW fsX48WSL+GGA7bqx+eCkl32F84mOU/+MrfxdIouCHemVfVZDBzuGoiZtz YKM7opJUeMYM0glMRk/1T9FnuLnbIQTB3/jZhKLleWctl8NTKNoHaNb82 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10901"; a="391742807" X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="391742807" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Nov 2023 19:30:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.04,217,1695711600"; d="scan'208";a="8090194" Received: from allen-box.sh.intel.com ([10.239.159.127]) by orviesa002.jf.intel.com with ESMTP; 21 Nov 2023 19:30:40 -0800 From: Lu Baolu To: Joerg Roedel Cc: mohd.syazwan.abdul.halim@intel.com, Kunwu Chan , iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 7/7] iommu/vt-d: Set variable intel_dirty_ops to static Date: Wed, 22 Nov 2023 11:26:08 +0800 Message-Id: <20231122032608.165144-8-baolu.lu@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231122032608.165144-1-baolu.lu@linux.intel.com> References: <20231122032608.165144-1-baolu.lu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Kunwu Chan Fix the following warning: drivers/iommu/intel/iommu.c:302:30: warning: symbol 'intel_dirty_ops' was not declared. Should it be static? This variable is only used in its defining file, so it should be static. Fixes: f35f22cc760e ("iommu/vt-d: Access/Dirty bit support for SS domains") Signed-off-by: Kunwu Chan Reviewed-by: Jason Gunthorpe Reviewed-by: Joao Martins Link: https://lore.kernel.org/r/20231120101025.1103404-1-chentao@kylinos.cn Signed-off-by: Lu Baolu --- drivers/iommu/intel/iommu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index 68f121c28fbf..897159dba47d 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -299,7 +299,7 @@ static int iommu_skip_te_disable; #define IDENTMAP_AZALIA 4 =20 const struct iommu_ops intel_iommu_ops; -const struct iommu_dirty_ops intel_dirty_ops; +static const struct iommu_dirty_ops intel_dirty_ops; =20 static bool translation_pre_enabled(struct intel_iommu *iommu) { @@ -4929,7 +4929,7 @@ static int intel_iommu_read_and_clear_dirty(struct io= mmu_domain *domain, return 0; } =20 -const struct iommu_dirty_ops intel_dirty_ops =3D { +static const struct iommu_dirty_ops intel_dirty_ops =3D { .set_dirty_tracking =3D intel_iommu_set_dirty_tracking, .read_and_clear_dirty =3D intel_iommu_read_and_clear_dirty, }; --=20 2.34.1