From nobody Wed Dec 17 21:01:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 225EDC61D92 for ; Wed, 22 Nov 2023 03:06:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343550AbjKVDGe (ORCPT ); Tue, 21 Nov 2023 22:06:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36352 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235035AbjKVDGb (ORCPT ); Tue, 21 Nov 2023 22:06:31 -0500 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF6E012C for ; Tue, 21 Nov 2023 19:06:27 -0800 (PST) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-6c115026985so6373921b3a.1 for ; Tue, 21 Nov 2023 19:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1700622387; x=1701227187; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xQTyfvTA/sT9rfHfHNgSFRFvzietrqmBvaroSzp1CzI=; b=GJkkVI7WcCmlpXCnMuay2CNDJOZacbcwlgUAnb8Xfl4Xaz2iatpSI1l7x9cpE4ESN/ uyVSUTJC/LEsx1/KfZedaEpHA1mntL7uq7t0lMu9yA6nxIRXz4Ek26Z5JyBCvsphNz0H QCuHig0kc/J4QI8BMl0O6qfr1jJSFa7cLoZLHMn4Z2JeX+ey0RA07pqUYU896/pMZ9Y9 /ar2HKRhvcjrYuYxrVkZmO9RhDsvZQgDrn8QA7+shJ3uG9sbtqEmuldlybyJYIGdM0x4 3ZgNOBIdtOfvwZbSxso0IUV+iego45YucPVUIw+7tm+zLgchCuOsteANbg1FtHarMosh 42pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700622387; x=1701227187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xQTyfvTA/sT9rfHfHNgSFRFvzietrqmBvaroSzp1CzI=; b=uF5/Lp3w5AdeWCQh8Bq6/ihT8WyrfVVY+Fkdjs+Df5ppASnhzCMoveOadSL8ImXWWW 556GV+oE+eF5Y+X3yi1mGaIUSgR93petnIdWLM8omUSGmra3/JugBpyXf15tepmku9gw 5FyXTk9AA6g9lxZx6Fgqz0EvX9bHUn9O7iLF5bkeJPpFgwWfptVBDeA+Duaa8B8ZKc6l uZ3WvNuTQ5sOcFSSaXC8sZFTyLmPPsXwt+FEnBw8SRAz9BjN9YPretBOkCS4H5af8PP6 U+QUURxf/bc720D2Ka4DZ4yeYvmpIk4Vko7n0plwnmo/4bqCyW8W9Nz4Y7EPOkFvLJcX B3wA== X-Gm-Message-State: AOJu0YyiZszv/MgVzBb+i8dY0NLIxmyvqHGYf3eEOGcRZgdhcDHiyKYp ZJAGR+p8G47ntGmEd+OUeOwC4A== X-Google-Smtp-Source: AGHT+IHMBi1+1x3Yt/bfrl9gyv/iDKPNW7+yCziyo+xCTBYWw/hNzj1p+tHsCVOZgnyBdWAdN+80eQ== X-Received: by 2002:a05:6a20:78a2:b0:186:2389:a73e with SMTP id d34-20020a056a2078a200b001862389a73emr933242pzg.55.1700622387226; Tue, 21 Nov 2023 19:06:27 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s2-20020aa78282000000b006a77343b0ccsm8614917pfm.89.2023.11.21.19.06.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 19:06:26 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt , Harry Wentland , Leo Li , Rodrigo Siqueira , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , =?UTF-8?q?Christian=20K=C3=B6nig?= , Alex Deucher , Pan Xinhui , Daniel Vetter , amd-gfx@lists.freedesktop.org, Samuel Holland Subject: [PATCH 1/3] riscv: Add support for kernel-mode FPU Date: Tue, 21 Nov 2023 19:05:13 -0800 Message-ID: <20231122030621.3759313-2-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122030621.3759313-1-samuel.holland@sifive.com> References: <20231122030621.3759313-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" This is needed to support recent hardware in the amdgpu DRM driver. The FPU code in that driver is not performance-critical, so only provide the minimal support. Signed-off-by: Samuel Holland --- arch/riscv/include/asm/switch_to.h | 14 ++++++++++++++ arch/riscv/kernel/process.c | 3 +++ 2 files changed, 17 insertions(+) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/sw= itch_to.h index f90d8e42f3c7..4b15f1292fc4 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -63,6 +63,20 @@ static __always_inline bool has_fpu(void) return riscv_has_extension_likely(RISCV_ISA_EXT_f) || riscv_has_extension_likely(RISCV_ISA_EXT_d); } + +static inline void kernel_fpu_begin(void) +{ + preempt_disable(); + fstate_save(current, task_pt_regs(current)); + csr_set(CSR_SSTATUS, SR_FS); +} + +static inline void kernel_fpu_end(void) +{ + csr_clear(CSR_SSTATUS, SR_FS); + fstate_restore(current, task_pt_regs(current)); + preempt_enable(); +} #else static __always_inline bool has_fpu(void) { return false; } #define fstate_save(task, regs) do { } while (0) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index 4f21d970a129..6a18bc709d1c 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -225,3 +225,6 @@ int copy_thread(struct task_struct *p, const struct ker= nel_clone_args *args) p->thread.sp =3D (unsigned long)childregs; /* kernel sp */ return 0; } + +EXPORT_SYMBOL_GPL(__fstate_save); +EXPORT_SYMBOL_GPL(__fstate_restore); --=20 2.42.0 From nobody Wed Dec 17 21:01:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF366C61D85 for ; Wed, 22 Nov 2023 03:06:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343557AbjKVDGg (ORCPT ); Tue, 21 Nov 2023 22:06:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235046AbjKVDGc (ORCPT ); Tue, 21 Nov 2023 22:06:32 -0500 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3668090 for ; Tue, 21 Nov 2023 19:06:29 -0800 (PST) Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-6cbb71c3020so298311b3a.1 for ; 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charset="utf-8" Since it is not possible to incrementally add/remove extensions from the compiler's ISA string by appending arguments, any code that wants to modify the ISA string must recreate the whole thing. To support this, factor out the logic for generating the -march argument so it can be reused where needed. Signed-off-by: Samuel Holland --- arch/riscv/Makefile | 12 +----------- arch/riscv/Makefile.isa | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 11 deletions(-) create mode 100644 arch/riscv/Makefile.isa diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile index a74be78678eb..c738eafe67a0 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile @@ -58,22 +58,12 @@ ifeq ($(CONFIG_SHADOW_CALL_STACK),y) KBUILD_LDFLAGS +=3D --no-relax-gp endif =20 -# ISA string setting -riscv-march-$(CONFIG_ARCH_RV32I) :=3D rv32ima -riscv-march-$(CONFIG_ARCH_RV64I) :=3D rv64ima -riscv-march-$(CONFIG_FPU) :=3D $(riscv-march-y)fd -riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c -riscv-march-$(CONFIG_RISCV_ISA_V) :=3D $(riscv-march-y)v - ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC KBUILD_CFLAGS +=3D -Wa,-misa-spec=3D2.2 KBUILD_AFLAGS +=3D -Wa,-misa-spec=3D2.2 -else -riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) :=3D $(riscv= -march-y)_zicsr_zifencei endif =20 -# Check if the toolchain supports Zihintpause extension -riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) :=3D $(riscv-march-y)_zihi= ntpause +include $(srctree)/arch/riscv/Makefile.isa =20 # Remove F,D,V from isa string for all. Keep extensions between "fd" and "= v" by # matching non-v and non-multi-letter extensions out with the filter ([^v_= ]*) diff --git a/arch/riscv/Makefile.isa b/arch/riscv/Makefile.isa new file mode 100644 index 000000000000..e10c77e26fe6 --- /dev/null +++ b/arch/riscv/Makefile.isa @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0-only + +# ISA string setting +riscv-march-$(CONFIG_ARCH_RV32I) :=3D rv32ima +riscv-march-$(CONFIG_ARCH_RV64I) :=3D rv64ima +riscv-march-$(CONFIG_FPU) :=3D $(riscv-march-y)fd +riscv-march-$(CONFIG_RISCV_ISA_C) :=3D $(riscv-march-y)c +riscv-march-$(CONFIG_RISCV_ISA_V) :=3D $(riscv-march-y)v + +ifndef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC +riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) :=3D $(riscv= -march-y)_zicsr_zifencei +endif + +# Check if the toolchain supports Zihintpause extension +riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) :=3D $(riscv-march-y)_zihi= ntpause --=20 2.42.0 From nobody Wed Dec 17 21:01:25 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CA8EC61D97 for ; Wed, 22 Nov 2023 03:06:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343564AbjKVDGi (ORCPT ); Tue, 21 Nov 2023 22:06:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343551AbjKVDGe (ORCPT ); Tue, 21 Nov 2023 22:06:34 -0500 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9F7EF4 for ; Tue, 21 Nov 2023 19:06:30 -0800 (PST) Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-6cbc8199a2aso659631b3a.1 for ; Tue, 21 Nov 2023 19:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1700622390; x=1701227190; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oBSDlJJdl9cJTZEKARyFff2b3kLrE8gro26mzSoUMfg=; b=kKAPHuA5bShBI1m2kdLOwPZWo8rdZdMqdWYrYnxgC8FodR0uho+MtADydgTUEbiBuN 8mnXYcbNH53F4H69ufumyBCjhq/Un3bEB/7P901+gV595tFRhk9NMn31GuUIMMdxBH50 SB1jAK05uJxHWDdSIGlB2pD00GD1/Gx+W9S3+9QWa1SxPHgBtjjSbhoez7j19sDuqlZT e6q8RuL5mo6z29SGBsLAvzhEDJjqKRjLcr/y/HVvdNQUiiJ/e47Mf0Sp962coyiGqhje RCtJBuaCF5R3BPbMQ6uPXJ4QrqlGjb5LT6DiOAkzu1yWzochUKd6aeBykAqp1P80eclp c5jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700622390; x=1701227190; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oBSDlJJdl9cJTZEKARyFff2b3kLrE8gro26mzSoUMfg=; b=NYhogTze78FWoglGmIm6ZyCHgANciqaGsxM08/9kDtV533G7bOzUbTzup1gF9WdKyM EASbL4JP5gN6SRsp2Xr7OeuVOut1ugRvOsO8wTHcb6AwLYbVotXOtbY/oxr8rV4bDJVC pvij6diNLdbC5adxwOpL23U4nT9ud1tuYFuUOJ9ZwBlsKSjrK9aXBWBzg2xTlLc3cNtP g+yTT0cuS3S4zCfFfKAduvWWsu9qnV9jFIvLK1//t5D5eXhYSFVSXYrDYoVsgNite4PI jJ46EYlagLLZeLp3GG+SmC5PPzVYt2r28M9ONE3gpUTxqwMpvia4iO0GwG9SDPR0OQ6n bYRQ== X-Gm-Message-State: AOJu0YyDwxbASTVR9dEyCCspeQJjUWP4kGr6S41//QuWmHMJU8qfsF5g FL6PKbhh2kNVi7ToD5qZL1/+ug== X-Google-Smtp-Source: AGHT+IGAWRMig9MTM8HwbUunWOHJsJ/tdXoUczvav4ujcqkNnMcjGyNXeyS3D3MD4r1LtBjigmKHkw== X-Received: by 2002:a05:6a00:98e:b0:6cb:cdd0:76f7 with SMTP id u14-20020a056a00098e00b006cbcdd076f7mr417804pfg.21.1700622390174; Tue, 21 Nov 2023 19:06:30 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id s2-20020aa78282000000b006a77343b0ccsm8614917pfm.89.2023.11.21.19.06.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 19:06:29 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt , Harry Wentland , Leo Li , Rodrigo Siqueira , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, David Airlie , =?UTF-8?q?Christian=20K=C3=B6nig?= , Alex Deucher , Pan Xinhui , Daniel Vetter , amd-gfx@lists.freedesktop.org, Samuel Holland Subject: [PATCH 3/3] drm/amd/display: Support DRM_AMD_DC_FP on RISC-V Date: Tue, 21 Nov 2023 19:05:15 -0800 Message-ID: <20231122030621.3759313-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231122030621.3759313-1-samuel.holland@sifive.com> References: <20231122030621.3759313-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RISC-V uses kernel_fpu_begin()/kernel_fpu_end() like several other architectures. Enabling hardware FP requires overriding the ISA string for the relevant compilation units. Signed-off-by: Samuel Holland --- drivers/gpu/drm/amd/display/Kconfig | 5 ++++- drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 6 ++++-- drivers/gpu/drm/amd/display/dc/dml/Makefile | 6 ++++++ drivers/gpu/drm/amd/display/dc/dml2/Makefile | 6 ++++++ 4 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/disp= lay/Kconfig index 901d1961b739..49b33b2f6701 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -8,7 +8,10 @@ config DRM_AMD_DC depends on BROKEN || !CC_IS_CLANG || ARM64 || RISCV || SPARC64 || X86_64 select SND_HDA_COMPONENT if SND_HDA_CORE # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 - select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64= && KERNEL_MODE_NEON && !CC_IS_CLANG)) + select DRM_AMD_DC_FP if ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG + select DRM_AMD_DC_FP if PPC64 && ALTIVEC + select DRM_AMD_DC_FP if RISCV && FPU + select DRM_AMD_DC_FP if LOONGARCH || X86 help Choose this option if you want to use the new display engine support for AMDGPU. This adds required support for Vega and diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/d= rm/amd/display/amdgpu_dm/dc_fpu.c index 4ae4720535a5..834dca0396f1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -35,6 +35,8 @@ #include #elif defined(CONFIG_LOONGARCH) #include +#elif defined(CONFIG_RISCV) +#include #endif =20 /** @@ -89,7 +91,7 @@ void dc_fpu_begin(const char *function_name, const int li= ne) depth =3D __this_cpu_inc_return(fpu_recursion_depth); =20 if (depth =3D=3D 1) { -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) || defined(CONFIG_RIS= CV) kernel_fpu_begin(); #elif defined(CONFIG_PPC64) if (cpu_has_feature(CPU_FTR_VSX_COMP)) @@ -122,7 +124,7 @@ void dc_fpu_end(const char *function_name, const int li= ne) =20 depth =3D __this_cpu_dec_return(fpu_recursion_depth); if (depth =3D=3D 0) { -#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) || defined(CONFIG_RIS= CV) kernel_fpu_end(); #elif defined(CONFIG_PPC64) if (cpu_has_feature(CPU_FTR_VSX_COMP)) diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/= amd/display/dc/dml/Makefile index ea7d60f9a9b4..5c8f840ef323 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -43,6 +43,12 @@ dml_ccflags :=3D -mfpu=3D64 dml_rcflags :=3D -msoft-float endif =20 +ifdef CONFIG_RISCV +include $(srctree)/arch/riscv/Makefile.isa +# Remove V from the ISA string, like in arch/riscv/Makefile, but keep F an= d D. +dml_ccflags :=3D -march=3D$(shell echo $(riscv-march-y) | sed -E 's/(rv32i= ma|rv64ima)([^v_]*)v?/\1\2/') +endif + ifdef CONFIG_CC_IS_GCC ifneq ($(call gcc-min-version, 70100),y) IS_OLD_GCC =3D 1 diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm= /amd/display/dc/dml2/Makefile index acff3449b8d7..15ad6e3a2173 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2/Makefile @@ -42,6 +42,12 @@ dml2_ccflags :=3D -mfpu=3D64 dml2_rcflags :=3D -msoft-float endif =20 +ifdef CONFIG_RISCV +include $(srctree)/arch/riscv/Makefile.isa +# Remove V from the ISA string, like in arch/riscv/Makefile, but keep F an= d D. +dml2_ccflags :=3D -march=3D$(shell echo $(riscv-march-y) | sed -E 's/(rv32= ima|rv64ima)([^v_]*)v?/\1\2/') +endif + ifdef CONFIG_CC_IS_GCC ifeq ($(call cc-ifversion, -lt, 0701, y), y) IS_OLD_GCC =3D 1 --=20 2.42.0