From nobody Wed Dec 17 23:40:45 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23613C61D99 for ; Tue, 21 Nov 2023 23:47:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234944AbjKUXrt (ORCPT ); Tue, 21 Nov 2023 18:47:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234900AbjKUXrp (ORCPT ); Tue, 21 Nov 2023 18:47:45 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD4FC19E for ; Tue, 21 Nov 2023 15:47:41 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-285196aaecaso2339465a91.0 for ; Tue, 21 Nov 2023 15:47:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1700610461; x=1701215261; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yfO2TsuP5+bzwc+1UBNKacN7ooenjZKMpjxDQuaWHLs=; b=aZrT63MgnuSZW4fEYf/0NWsduVv1PId3L91IjnWURSTnyE/T44v7vPbC5kuMGAqT0D 1kCJWNo6GONRkpF9EDupy47EueoEjG/tArf234YzpkaI3YOB/cpoKgy1OSneoYxXvORN DAJUvg5gBhZpm2t6KlFoo2YA7KlksPlY/64vIh0662J/TVmDd8J/OXRx/O/2vgRwpfPA 5TF+K1crnC+SZ3ZX2rtUlihyPhe86nNqCTCA9HALAeFuhDiBZxzeHtrTSUPpUyTHxQI6 rBQKdgSTvLdCS4El1suH7s3Qz8Y40rCjQ9AXtdL+xbzdsUL9/V76DrE1xjY7J260DgS3 yt/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700610461; x=1701215261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yfO2TsuP5+bzwc+1UBNKacN7ooenjZKMpjxDQuaWHLs=; b=t/YpmZH0SZOl0tqfCOARNSUSLQ9cLojpes6taKpL7MNJJ6q8pJtvr0T8G9ZXP6vZet +1DRa4Qu1VCpNYKs43LJYixlMVBU4zEfxvJEh3sL+2KHkUM4onPnvSauOm73jIoxqtNd YTnJZZdLK+dA47PmRFcDYqEimUNrR2Hn0F4FMwuIjm3ecSZorx3xqScY1bGCflsBZrFT WKEly3z5rbgQyn8ZghRVW20VJdEUfw4H5lnLPFrktTAzeVZhb/hAsIier0JnN8CqYRnn drrGlbfiLErCGfb6HFzUi8tLhPXMj2ZiotvZ2piDK7zl3Y1I+0x2rZ2ExPMjjWI08iNf hCew== X-Gm-Message-State: AOJu0YzweT0Of1CeeN4Kvxl++AZWPiYB287pYMWTi1mf/aZl8l1D2Czt jKKND/aimibSVozs10lO5jP1Mg== X-Google-Smtp-Source: AGHT+IEuxWeyQyxVZpHs2HhfPBfaktXQRoOaYpXSTZYzhyVnj051EXkgI0JValZG2raCSDzrUvzGGg== X-Received: by 2002:a17:90b:17c9:b0:27d:661f:59ac with SMTP id me9-20020a17090b17c900b0027d661f59acmr803651pjb.38.1700610461416; Tue, 21 Nov 2023 15:47:41 -0800 (PST) Received: from sw06.internal.sifive.com ([4.53.31.132]) by smtp.gmail.com with ESMTPSA id f8-20020a17090ace0800b002802d9d4e96sm82234pju.54.2023.11.21.15.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Nov 2023 15:47:41 -0800 (PST) From: Samuel Holland To: Palmer Dabbelt , linux-riscv@lists.infradead.org Cc: linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH 3/3] riscv: Use the same CPU operations for all CPUs Date: Tue, 21 Nov 2023 15:47:26 -0800 Message-ID: <20231121234736.3489608-4-samuel.holland@sifive.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121234736.3489608-1-samuel.holland@sifive.com> References: <20231121234736.3489608-1-samuel.holland@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" RISC-V provides no binding (ACPI or DT) to describe per-cpu start/stop operations, so cpu_set_ops() will always detect the same operations for every CPU. Replace the cpu_ops array with a single pointer to save space and reduce boot time. Signed-off-by: Samuel Holland Reviewed-by: Conor Dooley --- arch/riscv/include/asm/cpu_ops.h | 4 ++-- arch/riscv/kernel/cpu-hotplug.c | 10 +++++----- arch/riscv/kernel/cpu_ops.c | 12 +++++------- arch/riscv/kernel/smp.c | 2 +- arch/riscv/kernel/smpboot.c | 13 +++++-------- 5 files changed, 18 insertions(+), 23 deletions(-) diff --git a/arch/riscv/include/asm/cpu_ops.h b/arch/riscv/include/asm/cpu_= ops.h index 18af75e6873c..176b570ef982 100644 --- a/arch/riscv/include/asm/cpu_ops.h +++ b/arch/riscv/include/asm/cpu_ops.h @@ -29,7 +29,7 @@ struct cpu_operations { }; =20 extern const struct cpu_operations cpu_ops_spinwait; -extern const struct cpu_operations *cpu_ops[NR_CPUS]; -void __init cpu_set_ops(int cpu); +extern const struct cpu_operations *cpu_ops; +void __init cpu_set_ops(void); =20 #endif /* ifndef __ASM_CPU_OPS_H */ diff --git a/arch/riscv/kernel/cpu-hotplug.c b/arch/riscv/kernel/cpu-hotplu= g.c index 934eb64da0d0..28b58fc5ad19 100644 --- a/arch/riscv/kernel/cpu-hotplug.c +++ b/arch/riscv/kernel/cpu-hotplug.c @@ -18,7 +18,7 @@ =20 bool cpu_has_hotplug(unsigned int cpu) { - if (cpu_ops[cpu]->cpu_stop) + if (cpu_ops->cpu_stop) return true; =20 return false; @@ -31,7 +31,7 @@ int __cpu_disable(void) { unsigned int cpu =3D smp_processor_id(); =20 - if (!cpu_ops[cpu] || !cpu_ops[cpu]->cpu_stop) + if (!cpu_ops->cpu_stop) return -EOPNOTSUPP; =20 remove_cpu_topology(cpu); @@ -55,8 +55,8 @@ void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) pr_notice("CPU%u: off\n", cpu); =20 /* Verify from the firmware if the cpu is really stopped*/ - if (cpu_ops[cpu]->cpu_is_stopped) - ret =3D cpu_ops[cpu]->cpu_is_stopped(cpu); + if (cpu_ops->cpu_is_stopped) + ret =3D cpu_ops->cpu_is_stopped(cpu); if (ret) pr_warn("CPU%d may not have stopped: %d\n", cpu, ret); } @@ -70,7 +70,7 @@ void __noreturn arch_cpu_idle_dead(void) =20 cpuhp_ap_report_dead(); =20 - cpu_ops[smp_processor_id()]->cpu_stop(); + cpu_ops->cpu_stop(); /* It should never reach here */ BUG(); } diff --git a/arch/riscv/kernel/cpu_ops.c b/arch/riscv/kernel/cpu_ops.c index 5540e2880abb..6a8bd8f4db07 100644 --- a/arch/riscv/kernel/cpu_ops.c +++ b/arch/riscv/kernel/cpu_ops.c @@ -13,7 +13,7 @@ #include #include =20 -const struct cpu_operations *cpu_ops[NR_CPUS] __ro_after_init; +const struct cpu_operations *cpu_ops __ro_after_init =3D &cpu_ops_spinwait; =20 extern const struct cpu_operations cpu_ops_sbi; #ifndef CONFIG_RISCV_BOOT_SPINWAIT @@ -22,14 +22,12 @@ const struct cpu_operations cpu_ops_spinwait =3D { }; #endif =20 -void __init cpu_set_ops(int cpuid) +void __init cpu_set_ops(void) { #if IS_ENABLED(CONFIG_RISCV_SBI) if (sbi_probe_extension(SBI_EXT_HSM)) { - if (!cpuid) - pr_info("SBI HSM extension detected\n"); - cpu_ops[cpuid] =3D &cpu_ops_sbi; - } else + pr_info("SBI HSM extension detected\n"); + cpu_ops =3D &cpu_ops_sbi; + } #endif - cpu_ops[cpuid] =3D &cpu_ops_spinwait; } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 40420afbb1a0..45dd4035416e 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -81,7 +81,7 @@ static inline void ipi_cpu_crash_stop(unsigned int cpu, s= truct pt_regs *regs) =20 #ifdef CONFIG_HOTPLUG_CPU if (cpu_has_hotplug(cpu)) - cpu_ops[cpu]->cpu_stop(); + cpu_ops->cpu_stop(); #endif =20 for(;;) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 5551945255cd..519b6bd946e5 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -166,25 +166,22 @@ void __init setup_smp(void) { int cpuid; =20 - cpu_set_ops(0); + cpu_set_ops(); =20 if (acpi_disabled) of_parse_and_init_cpus(); else acpi_parse_and_init_cpus(); =20 - for (cpuid =3D 1; cpuid < nr_cpu_ids; cpuid++) { - if (cpuid_to_hartid_map(cpuid) !=3D INVALID_HARTID) { - cpu_set_ops(cpuid); + for (cpuid =3D 1; cpuid < nr_cpu_ids; cpuid++) + if (cpuid_to_hartid_map(cpuid) !=3D INVALID_HARTID) set_cpu_possible(cpuid, true); - } - } } =20 static int start_secondary_cpu(int cpu, struct task_struct *tidle) { - if (cpu_ops[cpu]->cpu_start) - return cpu_ops[cpu]->cpu_start(cpu, tidle); + if (cpu_ops->cpu_start) + return cpu_ops->cpu_start(cpu, tidle); =20 return -EOPNOTSUPP; } --=20 2.42.0