From nobody Fri Sep 20 10:49:52 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17B9FC61D94 for ; Tue, 21 Nov 2023 12:51:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233966AbjKUMvY (ORCPT ); Tue, 21 Nov 2023 07:51:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233752AbjKUMvE (ORCPT ); Tue, 21 Nov 2023 07:51:04 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27B53D69; Tue, 21 Nov 2023 04:51:00 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BA65B6607319; Tue, 21 Nov 2023 12:50:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571059; bh=n+I9YOPDM99MnwpUCp/Jyp5QiCWQ9S9IzP9LXdnM4XE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Dy8nGXWdvPSsM5zqAHNWXFtkPY/CD+8TDJ2WuIQR9lA0ZWOv00MoLYVOgZz0vsC9u VE10qlW9gQereyffjew/gDsiCsH8lmSZSA7aAdVWf0PbEPr+C8Bwjeo0cRNIhWAJr7 r0JsNv9fC1IBlvvR+Fm9jW8/p2yRO9GnNMuAP4xI+ROp68uKwjvzR+XL358m7Sbfxz bJg9u7ozDj7Nyeli27vVe74BouUZmuKGK672lWp8sUSCNkGehPMDoFtPRETcm3jHL0 pcuEuerVqQCbLbwVP3EDPn5Cb5nDTOjRgF5z7GmGQwNWa2yqvqtM1tXav4pcbZd4/h qiY11JeHYz2HQ== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 08/20] soc: mediatek: mtk-svs: Add SVS-Thermal coefficient to SoC platform data Date: Tue, 21 Nov 2023 13:50:32 +0100 Message-ID: <20231121125044.78642-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" In preparation for commonizing the efuse parsing function, add the SVS-Thermal coefficients for all SoCs for which said function can be commonized (MT8186, MT8188, MT8192, MT8195) and assign those to their platform data structure. That will be used to calculate the MTS parameter with the equation MTS =3D (ts_coeff * 2) / 1000 This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 6c6f133c327f..ab564d48092b 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -118,6 +118,10 @@ #define SVSB_VOPS_FLD_VOP2_6 GENMASK(23, 16) #define SVSB_VOPS_FLD_VOP3_7 GENMASK(31, 24) =20 +/* SVS Thermal Coefficients */ +#define SVSB_TS_COEFF_MT8195 250460 +#define SVSB_TS_COEFF_MT8186 204650 + /* svs bank related setting */ #define BITS8 8 #define MAX_OPP_ENTRIES 16 @@ -374,6 +378,7 @@ struct svs_fusemap { * @bank_max: total number of svs banks * @efuse: svs efuse data received from NVMEM framework * @tefuse: thermal efuse data received from NVMEM framework + * @ts_coeff: thermal sensors coefficient */ struct svs_platform { void __iomem *base; @@ -388,6 +393,7 @@ struct svs_platform { u32 bank_max; u32 *efuse; u32 *tefuse; + u32 ts_coeff; }; =20 struct svs_platform_data { @@ -398,6 +404,7 @@ struct svs_platform_data { const struct svs_fusemap *glb_fuse_map; const u32 *regs; u32 bank_max; + u32 ts_coeff; }; =20 /** @@ -2926,6 +2933,7 @@ static const struct svs_platform_data svs_mt8195_plat= form_data =3D { .probe =3D svs_mt8192_platform_probe, .regs =3D svs_regs_v2, .bank_max =3D ARRAY_SIZE(svs_mt8195_banks), + .ts_coeff =3D SVSB_TS_COEFF_MT8195, .glb_fuse_map =3D (const struct svs_fusemap[GLB_MAX]) { { 0, 0 }, { 19, 4 } } @@ -2938,6 +2946,7 @@ static const struct svs_platform_data svs_mt8192_plat= form_data =3D { .probe =3D svs_mt8192_platform_probe, .regs =3D svs_regs_v2, .bank_max =3D ARRAY_SIZE(svs_mt8192_banks), + .ts_coeff =3D SVSB_TS_COEFF_MT8195, .glb_fuse_map =3D (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM not present */ { -1, 0 }, { 19, 4 } @@ -2951,6 +2960,7 @@ static const struct svs_platform_data svs_mt8188_plat= form_data =3D { .probe =3D svs_mt8192_platform_probe, .regs =3D svs_regs_v2, .bank_max =3D ARRAY_SIZE(svs_mt8188_banks), + .ts_coeff =3D SVSB_TS_COEFF_MT8195, .glb_fuse_map =3D (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM and VMIN not present */ { -1, 0 }, { -1, 0 } @@ -2964,6 +2974,7 @@ static const struct svs_platform_data svs_mt8186_plat= form_data =3D { .probe =3D svs_mt8186_platform_probe, .regs =3D svs_regs_v2, .bank_max =3D ARRAY_SIZE(svs_mt8186_banks), + .ts_coeff =3D SVSB_TS_COEFF_MT8186, .glb_fuse_map =3D (const struct svs_fusemap[GLB_MAX]) { /* FT_PGM and VMIN not present */ { -1, 0 }, { -1, 0 } @@ -3021,6 +3032,7 @@ static int svs_probe(struct platform_device *pdev) svsp->banks =3D svsp_data->banks; svsp->regs =3D svsp_data->regs; svsp->bank_max =3D svsp_data->bank_max; + svsp->ts_coeff =3D svsp_data->ts_coeff; =20 ret =3D svsp_data->probe(svsp); if (ret) --=20 2.42.0