From nobody Fri Sep 20 10:44:46 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 453C3C61D98 for ; Tue, 21 Nov 2023 12:52:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234051AbjKUMwD (ORCPT ); Tue, 21 Nov 2023 07:52:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234026AbjKUMva (ORCPT ); Tue, 21 Nov 2023 07:51:30 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5ED8CD71; Tue, 21 Nov 2023 04:51:13 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3748F6607319; Tue, 21 Nov 2023 12:51:11 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700571072; bh=6uV/aa1GXqZk9w0ZoiU/aw6OTSIwDj0KZLX0pQNrucc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gTH53GTfmI0yj69H84sNUw/o1GfBc0RPwtqU956LSEUYkdzVdK+rs6Vxzt4jmo5VW gaquzXsQFkH/PivbRg+Ug2iCwrqiIPhi2cE6exT3izeEzH6HpR5CT5xCfMC3t9sL6U 9g6pZu2nHjuKUY44UEuOcCoBErJG4TKWf1HFjR9mvM1KBEV93hgEr12hIfuOQdy+vs x5FY4Pj/4SUGn9WPtpt3s3JWy6p8eSOLGDwdu2e9YOCgAptH4gq4h9ULFxdqGA25UZ pcJojGZkWJCltiCsOH+g3EvBx7muBViZzmGvX6KjkacPQ0sBypAaGn3C8H/kFPkGv8 Xdcb0wBIOsO/g== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v3 20/20] arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace Date: Tue, 21 Nov 2023 13:50:44 +0100 Message-ID: <20231121125044.78642-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> References: <20231121125044.78642-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the MediaTek SVS node: this will lower the voltage of various components of the SoC based on chip quality (read from fuses) in order to save power and generate less heat. Also, reduce the LVTS_AP iospace to 0xc00, because that's exactly where SVS starts. - LVTS_AP start: 0x1100b000 length: 0xc00 - SVS start: 0x1100bc00 length: 0x400 Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 54c674c45b49..54debd4cf8e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1115,7 +1115,7 @@ spi0: spi@1100a000 { =20 lvts_ap: thermal-sensor@1100b000 { compatible =3D "mediatek,mt8195-lvts-ap"; - reg =3D <0 0x1100b000 0 0x1000>; + reg =3D <0 0x1100b000 0 0xc00>; interrupts =3D ; clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; resets =3D <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; @@ -1124,6 +1124,18 @@ lvts_ap: thermal-sensor@1100b000 { #thermal-sensor-cells =3D <1>; }; =20 + svs: svs@1100bc00 { + compatible =3D "mediatek,mt8195-svs"; + reg =3D <0 0x1100bc00 0 0x400>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names =3D "main"; + nvmem-cells =3D <&svs_calib_data &lvts_efuse_data1>; + nvmem-cell-names =3D "svs-calibration-data", "t-calibration-data"; + resets =3D <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; + reset-names =3D "svs_rst"; + }; + disp_pwm0: pwm@1100e000 { compatible =3D "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; reg =3D <0 0x1100e000 0 0x1000>; @@ -1682,6 +1694,9 @@ lvts_efuse_data1: lvts1-calib@1bc { lvts_efuse_data2: lvts2-calib@1d0 { reg =3D <0x1d0 0x38>; }; + svs_calib_data: svs-calib@580 { + reg =3D <0x580 0x64>; + }; }; =20 u3phy2: t-phy@11c40000 { --=20 2.42.0