From nobody Thu Dec 18 07:37:23 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D2DBC61D93 for ; Tue, 21 Nov 2023 11:57:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234673AbjKUL6A (ORCPT ); Tue, 21 Nov 2023 06:58:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234646AbjKUL45 (ORCPT ); Tue, 21 Nov 2023 06:56:57 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B05D7BA; Tue, 21 Nov 2023 03:56:53 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A94466607286; Tue, 21 Nov 2023 11:56:51 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700567812; bh=6uV/aa1GXqZk9w0ZoiU/aw6OTSIwDj0KZLX0pQNrucc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AzcJTJtcns2hZVQxPv//hCU1Ktg1kQPx1j+4phznifkdcfkG6kMM+QLmJDK1YlFxP RSq201iTG5sE8ggnON3rAC6anpXaj8FKY2VYWKYwQEr789kooV+0FamtKG9wfY41F9 NVni+Ire/E2C1Xaw60EzwIdhA4cABDHzsvUN2Dq85o+edij3aud1JL4lXXJTGAVVAS 3er6SsEHOFfC1hNpZkPix07W7GIDAZ0ulKN6wWP96LOARRWiJmLhY1eK7eqf/QIe76 miwiqWJceqJvECbus/En8QaCH5FKdYyMsjzEss9o4Bu6WbDdqkusT+D9YBFZ6k2e33 M1ScoW6Kkwdaw== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v2 20/20] arm64: dts: mediatek: mt8195: Add SVS node and reduce LVTS_AP iospace Date: Tue, 21 Nov 2023 12:56:24 +0100 Message-ID: <20231121115624.56855-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> References: <20231121115624.56855-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the MediaTek SVS node: this will lower the voltage of various components of the SoC based on chip quality (read from fuses) in order to save power and generate less heat. Also, reduce the LVTS_AP iospace to 0xc00, because that's exactly where SVS starts. - LVTS_AP start: 0x1100b000 length: 0xc00 - SVS start: 0x1100bc00 length: 0x400 Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts= /mediatek/mt8195.dtsi index 54c674c45b49..54debd4cf8e6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1115,7 +1115,7 @@ spi0: spi@1100a000 { =20 lvts_ap: thermal-sensor@1100b000 { compatible =3D "mediatek,mt8195-lvts-ap"; - reg =3D <0 0x1100b000 0 0x1000>; + reg =3D <0 0x1100b000 0 0xc00>; interrupts =3D ; clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; resets =3D <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; @@ -1124,6 +1124,18 @@ lvts_ap: thermal-sensor@1100b000 { #thermal-sensor-cells =3D <1>; }; =20 + svs: svs@1100bc00 { + compatible =3D "mediatek,mt8195-svs"; + reg =3D <0 0x1100bc00 0 0x400>; + interrupts =3D ; + clocks =3D <&infracfg_ao CLK_INFRA_AO_THERM>; + clock-names =3D "main"; + nvmem-cells =3D <&svs_calib_data &lvts_efuse_data1>; + nvmem-cell-names =3D "svs-calibration-data", "t-calibration-data"; + resets =3D <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; + reset-names =3D "svs_rst"; + }; + disp_pwm0: pwm@1100e000 { compatible =3D "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; reg =3D <0 0x1100e000 0 0x1000>; @@ -1682,6 +1694,9 @@ lvts_efuse_data1: lvts1-calib@1bc { lvts_efuse_data2: lvts2-calib@1d0 { reg =3D <0x1d0 0x38>; }; + svs_calib_data: svs-calib@580 { + reg =3D <0x580 0x64>; + }; }; =20 u3phy2: t-phy@11c40000 { --=20 2.42.0