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([82.78.167.183]) by smtp.gmail.com with ESMTPSA id p2-20020a5d4582000000b003316d1a3b05sm8777667wrq.78.2023.11.19.23.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Nov 2023 23:01:34 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux@armlinux.org.uk, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, p.zabel@pengutronix.de, arnd@arndb.de, m.szyprowski@samsung.com, alexandre.torgue@foss.st.com, afd@ti.com, broonie@kernel.org, alexander.stein@ew.tq-group.com, eugen.hristev@collabora.com, sergei.shtylyov@gmail.com, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com Cc: linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH 11/14] arm64: renesas: rzg3s-smarc-som: Invert the logic for SW_SD2_EN macro Date: Mon, 20 Nov 2023 09:00:21 +0200 Message-Id: <20231120070024.4079344-12-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231120070024.4079344-1-claudiu.beznea.uj@bp.renesas.com> References: <20231120070024.4079344-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The intention of SW_SD2_EN macro was to reflect the state of SW_CONFIG3 switch available on RZ/G3S Smarc Module. According to documentation SD2 is enabled when switch is in OFF state. For this, changed the logic of marco to map value 0 to switch's OFF state and value 1 to switch's ON state. Along with this update the description for each state for better understanding. The value of SW_SD2_EN macro was not changed in file because, according to documentation, the default state for this switch is ON. Fixes: adb4f0c5699c ("arm64: dts: renesas: Add initial support for RZ/G3S S= MARC SoM") Signed-off-by: Claudiu Beznea --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 01a4a9da7afc..275b14acd2ee 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -14,8 +14,8 @@ * 0 - SD0 is connected to eMMC * 1 - SD0 is connected to uSD0 card * @SW_SD2_EN: - * 0 - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC - * 1 - SD2 is connected to SoC + * 0 - (switch OFF) SD2 is connected to SoC + * 1 - (switch ON) SCIF1, SSI0, IRQ0, IRQ1 connected to SoC */ #define SW_SD0_DEV_SEL 1 #define SW_SD2_EN 1 @@ -25,7 +25,7 @@ / { =20 aliases { mmc0 =3D &sdhi0; -#if SW_SD2_EN +#if !SW_SD2_EN mmc2 =3D &sdhi2; #endif }; @@ -116,7 +116,7 @@ &sdhi0 { }; #endif =20 -#if SW_SD2_EN +#if !SW_SD2_EN &sdhi2 { pinctrl-0 =3D <&sdhi2_pins>; pinctrl-names =3D "default"; --=20 2.39.2