From nobody Thu Dec 18 18:04:15 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BA90C5AD4C for ; Mon, 20 Nov 2023 06:32:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231974AbjKTGc1 (ORCPT ); Mon, 20 Nov 2023 01:32:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbjKTGc0 (ORCPT ); Mon, 20 Nov 2023 01:32:26 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B630D7; Sun, 19 Nov 2023 22:32:22 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3AK6W4Qj073731; Mon, 20 Nov 2023 00:32:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1700461924; bh=yQ3hU54tqGWh+bOEfiNvlZ+MBk2NolkvtMHhi6QCw2g=; h=From:To:CC:Subject:Date; b=QghNXANbExbi2s6AZ73aUMIOX6rle8qDutPvS8YIhESHuvpmxirQvDzQGTcDEb9sz QVxFQ0gD5rmQ3Pc2yXgl+MUNtvYw92gIzQBKU9GKY7NUw9gqi69BS04meMxKwhwHYh xdIekGJZ6gkpBpur+eF/tb1nIDeUcYFBgaBtnCVE= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3AK6W3m2080586 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 20 Nov 2023 00:32:04 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 20 Nov 2023 00:32:03 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 20 Nov 2023 00:32:03 -0600 Received: from uda0492258.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3AK6VxGU074809; Mon, 20 Nov 2023 00:32:00 -0600 From: Siddharth Vadapalli To: , , , , , CC: , , , , , , Subject: [PATCH] arm64: dts: ti: k3-am654-icssg2: Enable PHY interrupts for ICSSG2 Date: Mon, 20 Nov 2023 12:01:59 +0530 Message-ID: <20231120063159.539306-1-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable interrupt mode of operation of the DP83867 Ethernet PHY which is used by ICSSG2. The DP83867 PHY driver already supports interrupt handling for interrupts generated by the PHY. Thus, add the necessary device-tree support to enable it. Since the GPIO1_87 line is muxed with EXT_REFCLK1 and SYNC1_OUT, update the pinmux to select GPIO1_87 for routing the interrupt. Signed-off-by: Siddharth Vadapalli Reviewed-by: MD Danish Anwar --- This patch is based on linux-next tagged next-20231120. Regards, Siddharth. arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso b/arch/arm64/boot/= dts/ti/k3-am654-icssg2.dtso index ec8cf20ca3ac..9f723592d0f4 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso +++ b/arch/arm64/boot/dts/ti/k3-am654-icssg2.dtso @@ -124,21 +124,34 @@ AM65X_IOPAD(0x0088, PIN_INPUT, 2) /* (AG17) PRG2_PRU0= _GPO4.PRG2_RGMII1_RX_CTL */ }; }; =20 +&main_pmx1 { + /* Select GPIO1_87 for ICSSG2 PHY interrupt */ + icssg2_phy_irq_pins_default: icssg2-phy-irq-default-pins { + pinctrl-single,pins =3D < + AM65X_IOPAD(0x0014, PIN_INPUT, 7) /* (A22) EXT_REFCLK1.GPIO1_87 */ + >; + }; +}; + &icssg2_mdio { status =3D "okay"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&icssg2_mdio_pins_default>; + pinctrl-names =3D "default", "icssg2-phy-irq"; + pinctrl-0 =3D <&icssg2_mdio_pins_default>, <&icssg2_phy_irq_pins_default>; #address-cells =3D <1>; #size-cells =3D <0>; =20 icssg2_phy0: ethernet-phy@0 { reg =3D <0>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <87 0x2>; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; }; =20 icssg2_phy1: ethernet-phy@3 { reg =3D <3>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <87 0x2>; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; }; --=20 2.34.1