From nobody Thu Dec 18 19:06:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 531DFC5ACB3 for ; Sun, 19 Nov 2023 12:13:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230444AbjKSMNu (ORCPT ); Sun, 19 Nov 2023 07:13:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229703AbjKSMNt (ORCPT ); Sun, 19 Nov 2023 07:13:49 -0500 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84E76126; Sun, 19 Nov 2023 04:13:45 -0800 (PST) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-5401bab7525so4940197a12.2; Sun, 19 Nov 2023 04:13:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700396024; x=1701000824; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YVr7goYhFLlmDZmc5xEl9s20CmZbe4+FAt3N2E9piDg=; b=k4wCUNeg4CBKnxnqD9cVlYYuPUs1MS134M8W7OvFRA8DN7cdv8G736PbOg6QTS8i4x nsCHJrlJzA0Gkp5YqgMhySJRFGMFTMuQVBc/rvLwE05eQ4hyXbHkvhH4X+eEQ1xXfIj0 2BLf9tyezXWn9pM1Qvq/zZmP6Cjz4QbhB7jmC4B1CoHVyoaYoPELfZ8JuALSp2+Pai1f vbuKHPiDvigDCwQr4xhGpo8LESEnCoiljPRst6VhNrT0wb3I8DC/PJ5hVzu4zDO10nRh aeDiMYvNZgnKPdIM8c6wJyIf7ygoNnFp8nDBDF9pr28qUSm5OgD3RXUjtfQz5hJB3ztu knDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700396024; x=1701000824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YVr7goYhFLlmDZmc5xEl9s20CmZbe4+FAt3N2E9piDg=; b=mHNei6ufjC2Gx2sz4As96d1e7ZRCAGGADvfX51CZzyT1J4KAmi4aY8m9dfzW6tW9kK vaDs3IM00ThpmZgYaKMei9YNEiT/HsI8E/pAh325GHc6PXdyk43C0dfSVRLPuKV8GjQB P5/W1LrrkoE+QBmw4rkmTQ/O6Am+5DcbkrYT/gwfjbZLLvEUHlKk8BzUT4tMe/6pdZHG tG76JZcQ4zmP01v88L7jIr4xYstRtidvsylrJEtClx04AEYWKQUEU30s5H1PuFyQeDSD tTQmuDj++0Nf0MaQcg6JwCUk1kckOy6TfzCW6BtTfszXxMrP2UbUSJGaI/RHhGogdlfv G2rA== X-Gm-Message-State: AOJu0YxaKBJWZzvzt10xWbwoIsN2Vt4eeQX2AIvg7ASEGlkO5EnD0d3j NXTA6bU8q3RykrXh7RL2DQ== X-Google-Smtp-Source: AGHT+IHBJU9wdIXPTCBk407dwoGGEi1XpoVY+fEgUXOjjM0NXJSTbbLeARn5Up3BUus6sIH24XikDw== X-Received: by 2002:a05:6402:64f:b0:548:4dd2:aa58 with SMTP id u15-20020a056402064f00b005484dd2aa58mr3510536edx.28.1700396023758; Sun, 19 Nov 2023 04:13:43 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:7017:f42c:e243:8c57]) by smtp.gmail.com with ESMTPSA id r5-20020a056402018500b0053dec545c8fsm2523634edv.3.2023.11.19.04.13.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Nov 2023 04:13:43 -0800 (PST) From: Alex Bee To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH v3 1/5] phy: rockchip-inno-usb2: Split ID interrupt phy registers Date: Sun, 19 Nov 2023 13:13:36 +0100 Message-ID: <20231119121340.109025-2-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231119121340.109025-1-knaerzche@gmail.com> References: <20231119121340.109025-1-knaerzche@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Commit 51a9b2c03dd3 ("phy: rockchip-inno-usb2: Handle ID IRQ") added ID detection interrupt registers. However the current implementation assumes that falling and rising edge interrupt are always enabled in registers spanning over subsequent bits. That is not the case for RK3128's version of the phy and this implementation can't be used as-is, since there are bits with different purpose in between. This splits up the register definitions for id_det_en, id_det_en and id_det_clr registers in rising and falling edge variants. It's required as preparation to support RK3128's Innosilicon usb2 phy as well in this driver and matches pretty much to what the vendor does, so I'm not expecting issues for other SoCs with that change. Signed-off-by: Alex Bee Reviewed-by: Heiko Stuebner --- Changes in v3: - rebased on linux-next =20 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 99 +++++++++++++------ 1 file changed, 70 insertions(+), 29 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/ro= ckchip/phy-rockchip-inno-usb2.c index a24d2af154df..b5a1d30df83a 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -123,9 +123,12 @@ struct rockchip_chg_det_reg { * @disrise_en: host disconnect rise edge detection enable. * @disrise_st: host disconnect rise edge detection state. * @disrise_clr: host disconnect rise edge detection clear. - * @id_det_en: id detection enable register. - * @id_det_st: id detection state register. - * @id_det_clr: id detection clear register. + * @idfall_det_en: id detection enable register, falling edge + * @idfall_det_st: id detection state register, falling edge + * @idfall_det_clr: id detection clear register, falling edge + * @idrise_det_en: id detection enable register, rising edge + * @idrise_det_st: id detection state register, rising edge + * @idrise_det_clr: id detection clear register, rising edge * @ls_det_en: linestate detection enable register. * @ls_det_st: linestate detection state register. * @ls_det_clr: linestate detection clear register. @@ -146,9 +149,12 @@ struct rockchip_usb2phy_port_cfg { struct usb2phy_reg disrise_en; struct usb2phy_reg disrise_st; struct usb2phy_reg disrise_clr; - struct usb2phy_reg id_det_en; - struct usb2phy_reg id_det_st; - struct usb2phy_reg id_det_clr; + struct usb2phy_reg idfall_det_en; + struct usb2phy_reg idfall_det_st; + struct usb2phy_reg idfall_det_clr; + struct usb2phy_reg idrise_det_en; + struct usb2phy_reg idrise_det_st; + struct usb2phy_reg idrise_det_clr; struct usb2phy_reg ls_det_en; struct usb2phy_reg ls_det_st; struct usb2phy_reg ls_det_clr; @@ -488,15 +494,27 @@ static int rockchip_usb2phy_init(struct phy *phy) if (ret) goto out; =20 - /* clear id status and enable id detect irq */ + /* clear id status and enable id detect irqs */ ret =3D property_enable(rphy->grf, - &rport->port_cfg->id_det_clr, + &rport->port_cfg->idfall_det_clr, true); if (ret) goto out; =20 ret =3D property_enable(rphy->grf, - &rport->port_cfg->id_det_en, + &rport->port_cfg->idrise_det_clr, + true); + if (ret) + goto out; + + ret =3D property_enable(rphy->grf, + &rport->port_cfg->idfall_det_en, + true); + if (ret) + goto out; + + ret =3D property_enable(rphy->grf, + &rport->port_cfg->idrise_det_en, true); if (ret) goto out; @@ -1030,11 +1048,16 @@ static irqreturn_t rockchip_usb2phy_id_irq(int irq,= void *data) struct rockchip_usb2phy *rphy =3D dev_get_drvdata(rport->phy->dev.parent); bool id; =20 - if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st)) + if (!property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st) && + !property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st)) return IRQ_NONE; =20 /* clear id detect irq pending status */ - property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true); + if (property_enabled(rphy->grf, &rport->port_cfg->idfall_det_st)) + property_enable(rphy->grf, &rport->port_cfg->idfall_det_clr, true); + + if (property_enabled(rphy->grf, &rport->port_cfg->idrise_det_st)) + property_enable(rphy->grf, &rport->port_cfg->idrise_det_clr, true); =20 id =3D property_enabled(rphy->grf, &rport->port_cfg->utmi_id); extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id); @@ -1524,9 +1547,12 @@ static const struct rockchip_usb2phy_cfg rk3228_phy_= cfgs[] =3D { .bvalid_det_en =3D { 0x0680, 3, 3, 0, 1 }, .bvalid_det_st =3D { 0x0690, 3, 3, 0, 1 }, .bvalid_det_clr =3D { 0x06a0, 3, 3, 0, 1 }, - .id_det_en =3D { 0x0680, 6, 5, 0, 3 }, - .id_det_st =3D { 0x0690, 6, 5, 0, 3 }, - .id_det_clr =3D { 0x06a0, 6, 5, 0, 3 }, + .idfall_det_en =3D { 0x0680, 6, 6, 0, 1 }, + .idfall_det_st =3D { 0x0690, 6, 6, 0, 1 }, + .idfall_det_clr =3D { 0x06a0, 6, 6, 0, 1 }, + .idrise_det_en =3D { 0x0680, 5, 5, 0, 1 }, + .idrise_det_st =3D { 0x0690, 5, 5, 0, 1 }, + .idrise_det_clr =3D { 0x06a0, 5, 5, 0, 1 }, .ls_det_en =3D { 0x0680, 2, 2, 0, 1 }, .ls_det_st =3D { 0x0690, 2, 2, 0, 1 }, .ls_det_clr =3D { 0x06a0, 2, 2, 0, 1 }, @@ -1587,9 +1613,12 @@ static const struct rockchip_usb2phy_cfg rk3308_phy_= cfgs[] =3D { .bvalid_det_en =3D { 0x3020, 3, 2, 0, 3 }, .bvalid_det_st =3D { 0x3024, 3, 2, 0, 3 }, .bvalid_det_clr =3D { 0x3028, 3, 2, 0, 3 }, - .id_det_en =3D { 0x3020, 5, 4, 0, 3 }, - .id_det_st =3D { 0x3024, 5, 4, 0, 3 }, - .id_det_clr =3D { 0x3028, 5, 4, 0, 3 }, + .idfall_det_en =3D { 0x3020, 5, 5, 0, 1 }, + .idfall_det_st =3D { 0x3024, 5, 5, 0, 1 }, + .idfall_det_clr =3D { 0x3028, 5, 5, 0, 1 }, + .idrise_det_en =3D { 0x3020, 4, 4, 0, 1 }, + .idrise_det_st =3D { 0x3024, 4, 4, 0, 1 }, + .idrise_det_clr =3D { 0x3028, 4, 4, 0, 1 }, .ls_det_en =3D { 0x3020, 0, 0, 0, 1 }, .ls_det_st =3D { 0x3024, 0, 0, 0, 1 }, .ls_det_clr =3D { 0x3028, 0, 0, 0, 1 }, @@ -1634,9 +1663,12 @@ static const struct rockchip_usb2phy_cfg rk3328_phy_= cfgs[] =3D { .bvalid_det_en =3D { 0x0110, 3, 2, 0, 3 }, .bvalid_det_st =3D { 0x0114, 3, 2, 0, 3 }, .bvalid_det_clr =3D { 0x0118, 3, 2, 0, 3 }, - .id_det_en =3D { 0x0110, 5, 4, 0, 3 }, - .id_det_st =3D { 0x0114, 5, 4, 0, 3 }, - .id_det_clr =3D { 0x0118, 5, 4, 0, 3 }, + .idfall_det_en =3D { 0x0110, 5, 5, 0, 1 }, + .idfall_det_st =3D { 0x0114, 5, 5, 0, 1 }, + .idfall_det_clr =3D { 0x0118, 5, 5, 0, 1 }, + .idrise_det_en =3D { 0x0110, 4, 4, 0, 1 }, + .idrise_det_st =3D { 0x0114, 4, 4, 0, 1 }, + .idrise_det_clr =3D { 0x0118, 4, 4, 0, 1 }, .ls_det_en =3D { 0x0110, 0, 0, 0, 1 }, .ls_det_st =3D { 0x0114, 0, 0, 0, 1 }, .ls_det_clr =3D { 0x0118, 0, 0, 0, 1 }, @@ -1700,9 +1732,12 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_= cfgs[] =3D { .bvalid_det_en =3D { 0xe3c0, 3, 3, 0, 1 }, .bvalid_det_st =3D { 0xe3e0, 3, 3, 0, 1 }, .bvalid_det_clr =3D { 0xe3d0, 3, 3, 0, 1 }, - .id_det_en =3D { 0xe3c0, 5, 4, 0, 3 }, - .id_det_st =3D { 0xe3e0, 5, 4, 0, 3 }, - .id_det_clr =3D { 0xe3d0, 5, 4, 0, 3 }, + .idfall_det_en =3D { 0xe3c0, 5, 5, 0, 1 }, + .idfall_det_st =3D { 0xe3e0, 5, 5, 0, 1 }, + .idfall_det_clr =3D { 0xe3d0, 5, 5, 0, 1 }, + .idrise_det_en =3D { 0xe3c0, 4, 4, 0, 1 }, + .idrise_det_st =3D { 0xe3e0, 4, 4, 0, 1 }, + .idrise_det_clr =3D { 0xe3d0, 4, 4, 0, 1 }, .utmi_avalid =3D { 0xe2ac, 7, 7, 0, 1 }, .utmi_bvalid =3D { 0xe2ac, 12, 12, 0, 1 }, .utmi_id =3D { 0xe2ac, 8, 8, 0, 1 }, @@ -1739,9 +1774,12 @@ static const struct rockchip_usb2phy_cfg rk3399_phy_= cfgs[] =3D { .bvalid_det_en =3D { 0xe3c0, 8, 8, 0, 1 }, .bvalid_det_st =3D { 0xe3e0, 8, 8, 0, 1 }, .bvalid_det_clr =3D { 0xe3d0, 8, 8, 0, 1 }, - .id_det_en =3D { 0xe3c0, 10, 9, 0, 3 }, - .id_det_st =3D { 0xe3e0, 10, 9, 0, 3 }, - .id_det_clr =3D { 0xe3d0, 10, 9, 0, 3 }, + .idfall_det_en =3D { 0xe3c0, 10, 10, 0, 1 }, + .idfall_det_st =3D { 0xe3e0, 10, 10, 0, 1 }, + .idfall_det_clr =3D { 0xe3d0, 10, 10, 0, 1 }, + .idrise_det_en =3D { 0xe3c0, 9, 9, 0, 1 }, + .idrise_det_st =3D { 0xe3e0, 9, 9, 0, 1 }, + .idrise_det_clr =3D { 0xe3d0, 9, 9, 0, 1 }, .utmi_avalid =3D { 0xe2ac, 10, 10, 0, 1 }, .utmi_bvalid =3D { 0xe2ac, 16, 16, 0, 1 }, .utmi_id =3D { 0xe2ac, 11, 11, 0, 1 }, @@ -1770,9 +1808,12 @@ static const struct rockchip_usb2phy_cfg rk3568_phy_= cfgs[] =3D { .bvalid_det_en =3D { 0x0080, 3, 2, 0, 3 }, .bvalid_det_st =3D { 0x0084, 3, 2, 0, 3 }, .bvalid_det_clr =3D { 0x0088, 3, 2, 0, 3 }, - .id_det_en =3D { 0x0080, 5, 4, 0, 3 }, - .id_det_st =3D { 0x0084, 5, 4, 0, 3 }, - .id_det_clr =3D { 0x0088, 5, 4, 0, 3 }, + .idfall_det_en =3D { 0x0080, 5, 5, 0, 1 }, + .idfall_det_st =3D { 0x0084, 5, 5, 0, 1 }, + .idfall_det_clr =3D { 0x0088, 5, 5, 0, 1 }, + .idrise_det_en =3D { 0x0080, 4, 4, 0, 1 }, + .idrise_det_st =3D { 0x0084, 4, 4, 0, 1 }, + .idrise_det_clr =3D { 0x0088, 4, 4, 0, 1 }, .utmi_avalid =3D { 0x00c0, 10, 10, 0, 1 }, .utmi_bvalid =3D { 0x00c0, 9, 9, 0, 1 }, .utmi_id =3D { 0x00c0, 6, 6, 0, 1 }, --=20 2.42.0 From nobody Thu Dec 18 19:06:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5852C5AD4C for ; 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Sun, 19 Nov 2023 04:13:44 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:7017:f42c:e243:8c57]) by smtp.gmail.com with ESMTPSA id r5-20020a056402018500b0053dec545c8fsm2523634edv.3.2023.11.19.04.13.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Nov 2023 04:13:44 -0800 (PST) From: Alex Bee To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH v3 2/5] phy: phy-rockchip-inno-usb2: Add RK3128 support Date: Sun, 19 Nov 2023 13:13:37 +0100 Message-ID: <20231119121340.109025-3-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231119121340.109025-1-knaerzche@gmail.com> References: <20231119121340.109025-1-knaerzche@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add registers to support the 2-port usb2 phy found in RK312x SoC familiy. Signed-off-by: Alex Bee Reviewed-by: Heiko Stuebner --- Changes in v3: - added phy_tuning-callback for RK3128 =20 drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/ro= ckchip/phy-rockchip-inno-usb2.c index b5a1d30df83a..4f71373ae6e1 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c @@ -1487,6 +1487,14 @@ static int rockchip_usb2phy_probe(struct platform_de= vice *pdev) return ret; } =20 +static int rk3128_usb2phy_tuning(struct rockchip_usb2phy *rphy) +{ + /* Turn off differential receiver in suspend mode */ + return regmap_write_bits(rphy->grf, 0x298, + BIT(2) << BIT_WRITEABLE_SHIFT | BIT(2), + BIT(2) << BIT_WRITEABLE_SHIFT | 0); +} + static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy) { int ret; @@ -1536,6 +1544,54 @@ static int rk3588_usb2phy_tuning(struct rockchip_usb= 2phy *rphy) return ret; } =20 +static const struct rockchip_usb2phy_cfg rk3128_phy_cfgs[] =3D { + { + .reg =3D 0x17c, + .num_ports =3D 2, + .phy_tuning =3D rk3128_usb2phy_tuning, + .clkout_ctl =3D { 0x0190, 15, 15, 1, 0 }, + .port_cfgs =3D { + [USB2PHY_PORT_OTG] =3D { + .phy_sus =3D { 0x017c, 8, 0, 0, 0x1d1 }, + .bvalid_det_en =3D { 0x017c, 14, 14, 0, 1 }, + .bvalid_det_st =3D { 0x017c, 15, 15, 0, 1 }, + .bvalid_det_clr =3D { 0x017c, 15, 15, 0, 1 }, + .idfall_det_en =3D { 0x01a0, 2, 2, 0, 1 }, + .idfall_det_st =3D { 0x01a0, 3, 3, 0, 1 }, + .idfall_det_clr =3D { 0x01a0, 3, 3, 0, 1 }, + .idrise_det_en =3D { 0x01a0, 0, 0, 0, 1 }, + .idrise_det_st =3D { 0x01a0, 1, 1, 0, 1 }, + .idrise_det_clr =3D { 0x01a0, 1, 1, 0, 1 }, + .ls_det_en =3D { 0x017c, 12, 12, 0, 1 }, + .ls_det_st =3D { 0x017c, 13, 13, 0, 1 }, + .ls_det_clr =3D { 0x017c, 13, 13, 0, 1 }, + .utmi_bvalid =3D { 0x014c, 5, 5, 0, 1 }, + .utmi_id =3D { 0x014c, 8, 8, 0, 1 }, + .utmi_ls =3D { 0x014c, 7, 6, 0, 1 }, + }, + [USB2PHY_PORT_HOST] =3D { + .phy_sus =3D { 0x0194, 8, 0, 0, 0x1d1 }, + .ls_det_en =3D { 0x0194, 14, 14, 0, 1 }, + .ls_det_st =3D { 0x0194, 15, 15, 0, 1 }, + .ls_det_clr =3D { 0x0194, 15, 15, 0, 1 } + } + }, + .chg_det =3D { + .opmode =3D { 0x017c, 3, 0, 5, 1 }, + .cp_det =3D { 0x02c0, 6, 6, 0, 1 }, + .dcp_det =3D { 0x02c0, 5, 5, 0, 1 }, + .dp_det =3D { 0x02c0, 7, 7, 0, 1 }, + .idm_sink_en =3D { 0x0184, 8, 8, 0, 1 }, + .idp_sink_en =3D { 0x0184, 7, 7, 0, 1 }, + .idp_src_en =3D { 0x0184, 9, 9, 0, 1 }, + .rdm_pdwn_en =3D { 0x0184, 10, 10, 0, 1 }, + .vdm_src_en =3D { 0x0184, 12, 12, 0, 1 }, + .vdp_src_en =3D { 0x0184, 11, 11, 0, 1 }, + }, + }, + { /* sentinel */ } +}; + static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] =3D { { .reg =3D 0x760, @@ -2031,6 +2087,7 @@ static const struct rockchip_usb2phy_cfg rv1108_phy_c= fgs[] =3D { =20 static const struct of_device_id rockchip_usb2phy_dt_match[] =3D { { .compatible =3D "rockchip,px30-usb2phy", .data =3D &rk3328_phy_cfgs }, + { .compatible =3D "rockchip,rk3128-usb2phy", .data =3D &rk3128_phy_cfgs }, { .compatible =3D "rockchip,rk3228-usb2phy", .data =3D &rk3228_phy_cfgs }, { .compatible =3D "rockchip,rk3308-usb2phy", .data =3D &rk3308_phy_cfgs }, { .compatible =3D "rockchip,rk3328-usb2phy", .data =3D &rk3328_phy_cfgs }, --=20 2.42.0 From nobody Thu Dec 18 19:06:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F41DCC5AE5B for ; Sun, 19 Nov 2023 12:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231161AbjKSMNy (ORCPT ); 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Sun, 19 Nov 2023 04:13:45 -0800 (PST) From: Alex Bee To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH v3 3/5] ARM: dts: rockchip: Add USB host clocks for RK3128 Date: Sun, 19 Nov 2023 13:13:38 +0100 Message-ID: <20231119121340.109025-4-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231119121340.109025-1-knaerzche@gmail.com> References: <20231119121340.109025-1-knaerzche@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add the required AHB clocks for both the ehci and ohci controller. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/roc= kchip/rk3128.dtsi index 7bf557c99561..074dffa377cc 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -163,6 +163,7 @@ usb_host_ehci: usb@101c0000 { compatible =3D "generic-ehci"; reg =3D <0x101c0000 0x20000>; interrupts =3D ; + clocks =3D <&cru HCLK_HOST2>; phys =3D <&usb2phy_host>; phy-names =3D "usb"; status =3D "disabled"; @@ -172,6 +173,7 @@ usb_host_ohci: usb@101e0000 { compatible =3D "generic-ohci"; reg =3D <0x101e0000 0x20000>; interrupts =3D ; + clocks =3D <&cru HCLK_HOST2>; phys =3D <&usb2phy_host>; phy-names =3D "usb"; status =3D "disabled"; --=20 2.42.0 From nobody Thu Dec 18 19:06:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4F5AC5ACB3 for ; Sun, 19 Nov 2023 12:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231191AbjKSMN4 (ORCPT ); Sun, 19 Nov 2023 07:13:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229703AbjKSMNv (ORCPT ); Sun, 19 Nov 2023 07:13:51 -0500 Received: from mail-ed1-x52f.google.com (mail-ed1-x52f.google.com [IPv6:2a00:1450:4864:20::52f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8E06182; Sun, 19 Nov 2023 04:13:47 -0800 (PST) Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-5437d60fb7aso5072524a12.3; Sun, 19 Nov 2023 04:13:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700396026; x=1701000826; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wFwnZSi+N4JIV79XXnkhp+/hoZIyLal8XhxbYAVRQ04=; b=dlBumDtI38HjOnrpS+s664RQ6rT0e+59TIOYdPeGhDj13tPrULx3+vAb3lrYkvlj1m OWxSDfVtdJ3U7wDRM+TZyXtYh1ughIUvIg/zz+3g4BX9rlLwFA4bL5jcqsh+4iZnXP9s pl2jk2p4cfAiuNSI7Few+tPKEDaITuwF8rZggOrtZf+LyC0RpSnFmwQ9PhB3TiaydeXf iOIsSNGRCe+8Puw/nXIhvm6lKC7hzyMijq7Hz0lx1NwyJfq/zKymLz7NOrmQR37mLzG5 xzWF4Ht1XaXQJt1ikT/1SqQw27x2VCmC62vqyoSrmyzz/Z9qzNu9Q8V91roMUPl7jKsz neaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700396026; x=1701000826; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wFwnZSi+N4JIV79XXnkhp+/hoZIyLal8XhxbYAVRQ04=; b=LPI11+CxoVrhdGVT40MlYNm9RXm582ue9CVfAHoJF0yTKklCzr9hKR6erakFdiojRe G8Dy1Qy4Mhr5nhAjHG9qTsGvR1sn8rEz8hWi6+JB+LjVnQz1PQl7PXMgjL3w3qU9ImGw vJWx5fLdt47aoK9woqY7eJMGtUleOJOVP/QRqA6Ht3ij4X1p0WBUKi9OxzLze6+VeP/n eG68sC7Z9/5j99QSLcSHAfyneQv9M6WUNicFMwxlLVHuWGW98vJlP1GpjvWG4Ls4HyB4 a5uyUs+DyEAEmpF7bkn5hQn+OrGUFCXY1sTOTZ9GzeOxaXQumhZkxfApH6pvPaFV43m1 z1kw== X-Gm-Message-State: AOJu0YzzIgoP3K52tsFdKmhSYIV8KEW6z9Uj9EmryHmEFktwSli9WESg zFe+On4PCRqgwUzt/D+GXQ== X-Google-Smtp-Source: AGHT+IFa1MdSQwDpFizg9mjE0jro6ti3S0NsdG4dJFDLIacwN3M11znKrlgdju1QRwUDDleLY9D5uA== X-Received: by 2002:aa7:c0cd:0:b0:53d:f072:7b0a with SMTP id j13-20020aa7c0cd000000b0053df0727b0amr3531026edp.39.1700396026174; Sun, 19 Nov 2023 04:13:46 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:7017:f42c:e243:8c57]) by smtp.gmail.com with ESMTPSA id r5-20020a056402018500b0053dec545c8fsm2523634edv.3.2023.11.19.04.13.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Nov 2023 04:13:45 -0800 (PST) From: Alex Bee To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH v3 4/5] ARM: dts: rockchip: Add dwc2 otg fifo siztes for RK3128 Date: Sun, 19 Nov 2023 13:13:39 +0100 Message-ID: <20231119121340.109025-5-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231119121340.109025-1-knaerzche@gmail.com> References: <20231119121340.109025-1-knaerzche@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The driver currently won't probe correctly if those values are missing. They have been taken from dowstream kernel and match those of other Rockchip SoCs. Signed-off-by: Alex Bee --- arch/arm/boot/dts/rockchip/rk3128.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/roc= kchip/rk3128.dtsi index 074dffa377cc..c8844e0024dc 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -154,6 +154,9 @@ usb_otg: usb@10180000 { clocks =3D <&cru HCLK_OTG>; clock-names =3D "otg"; dr_mode =3D "otg"; + g-np-tx-fifo-size =3D <16>; + g-rx-fifo-size =3D <280>; + g-tx-fifo-size =3D <256 128 128 64 32 16>; phys =3D <&usb2phy_otg>; phy-names =3D "usb2-phy"; status =3D "disabled"; --=20 2.42.0 From nobody Thu Dec 18 19:06:26 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3D6DC5AE5C for ; Sun, 19 Nov 2023 12:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231233AbjKSMN6 (ORCPT ); Sun, 19 Nov 2023 07:13:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230481AbjKSMNx (ORCPT ); Sun, 19 Nov 2023 07:13:53 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1F4311D; Sun, 19 Nov 2023 04:13:48 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-507962561adso5081620e87.0; Sun, 19 Nov 2023 04:13:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1700396027; x=1701000827; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IRvQu7v2aw6b3c6XSPxt/GFQ2vthRnfEbysoDl+IjOE=; b=So/Q3q6CX1GQh4TRr/h61jWDX1ugqisPkJ0FBbYplxRBIkCLITqOiKoWNMq1Qw0HLr ejDZ9QEKEAbFFqaCDB6mGxp11wi9wEy8Iq8QZNwUvNQnvvX/F3/DjO2jF3c6OouXCwwR swx8BtWPvOBXlVFtlt3FYhd93NQJkHjula2r8EcsUm69dko1jk7b/OTzURRYEy4t4885 T6z21CTkU0WGLv0RsPdPVBX0QMSdjMzXPpL4oY8VeQhpY5ePAgLiPNHAIu/tvdSHtiaH OG3wFSy22QXI6nJ9cwxehvXCNYG7fUIlZ1PildkDRhXtEoGi2IIZoy5ZQuaBJEcQ9C8m grHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700396027; x=1701000827; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IRvQu7v2aw6b3c6XSPxt/GFQ2vthRnfEbysoDl+IjOE=; b=XliKHWCSZAWKMsFsO6pYnTkYk6/u3TTtul3rGjQxZYnjqrnx3GS5RDEeLdoMtnKoTR qc2TTqYPdhr9pSGI7ewFJ0c4OUJpx3PWSxFir9PL6NFIBYaWb9BsfClDkTt+pH4wQY4i w8rDl4yW3/K6X6aA6ZaQsryULZGZL2Vh9Z9bE21sNVi2Fvs4jGH2jK52nAISav9Fz6bi 5pX0Zw9TlZFPGwWaaRZYbaRCYbAJu+sNmcLShaJMZs41ljYvxFmFR5fjbkmMkAghKLVy BrHXbYnFCoILPD1eS5wdNK2UoHxMiI4jY4HQO0/rMRQVBdaAA3v+2Mbc2/6d5u2zTyfk 6onA== X-Gm-Message-State: AOJu0Yzwws2B4iBPAzInUolCjxFGSEIxZOeHgfcEslJTj9zOBZorY/3k Tcw4uwKHF8NfJNPG4lFySQ== X-Google-Smtp-Source: AGHT+IFclIkGd4gUltycd20mO39V01aWQkCtlOGJQGc8SY39GQWh+136ifIDd6KIpOUu229lqj1sxw== X-Received: by 2002:a05:6512:485b:b0:4fe:1681:9377 with SMTP id ep27-20020a056512485b00b004fe16819377mr3313345lfb.44.1700396026949; Sun, 19 Nov 2023 04:13:46 -0800 (PST) Received: from U4.lan ([2a02:810b:f40:4300:7017:f42c:e243:8c57]) by smtp.gmail.com with ESMTPSA id r5-20020a056402018500b0053dec545c8fsm2523634edv.3.2023.11.19.04.13.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Nov 2023 04:13:46 -0800 (PST) From: Alex Bee To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Alex Bee Subject: [PATCH v3 5/5] ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK3128 Date: Sun, 19 Nov 2023 13:13:40 +0100 Message-ID: <20231119121340.109025-6-knaerzche@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231119121340.109025-1-knaerzche@gmail.com> References: <20231119121340.109025-1-knaerzche@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Without setting the parent for SCLK_USB480M the clock will use xin24m as it's default parent. While this is generally not an issue for the usb blocks to work, it becomes an issue for RK3128 since SCLK_USB480M can be a parent for other HW blocks (GPU, VPU, VIO), but they will never chose it, since it is currently always running at OSC frequency which is to slow for their needs. This sets the usb2 phy's output as SCLK_USB480M's parent and it's users can chose it if desired. Signed-off-by: Alex Bee --- Changes in v3: - moved parent assignment to the phy node arch/arm/boot/dts/rockchip/rk3128.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/roc= kchip/rk3128.dtsi index c8844e0024dc..61b292c7c4c3 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -266,6 +266,8 @@ usb2phy: usb2phy@17c { clocks =3D <&cru SCLK_OTGPHY0>; clock-names =3D "phyclk"; clock-output-names =3D "usb480m_phy"; + assigned-clocks =3D <&cru SCLK_USB480M>; + assigned-clock-parents =3D <&usb2phy>; #clock-cells =3D <0>; status =3D "disabled"; =20 --=20 2.42.0