From nobody Fri Sep 20 10:39:01 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3298EC2BB3F for ; Sat, 18 Nov 2023 13:14:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229670AbjKRNO5 (ORCPT ); Sat, 18 Nov 2023 08:14:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229735AbjKRNOy (ORCPT ); Sat, 18 Nov 2023 08:14:54 -0500 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [217.70.183.200]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1CF2CD5B; Sat, 18 Nov 2023 05:14:49 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 8766D20003; Sat, 18 Nov 2023 13:14:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700313288; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=usciJlF0tBj+65L/MlcGZT5V9mSdub2woDEGmaEy00Q=; b=IUGvmTrE7zpTGuWVyUr1MAfWYeD72X5M9kUZK8NY93Gsl96zfAnW0ZR9hI6NrxtsJ6bt9Z +t8QADbxAftCTShuFDLuT44B41TzpUyUqNXH8yHpFMgmQyNrVgww07n18VGzVLY1HX7W9I bzPBr6TfnxuV4MWjw+87vEA4dygZnAzyiZO3e3sGkwK7FViaKLRTrPTdmXhn+3kUg7Ifcy hw2gZqdykB2UGeGfmOxz1cQdp2MUsgxB0sUun7IN78sRhBPxvWtdi7eEKml+/66xUskX7v o84kCnkBEEv+uRkiXrnKq+Wbhy024z8ckKegMzM9cRdzK8O3MTP8lNvd/XPWUA== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 13/15] net: dsa: mt7530: simplify mt7530_setup_port6() and change to void Date: Sat, 18 Nov 2023 16:13:15 +0300 Message-Id: <20231118131317.295591-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This code is from before this driver was converted to phylink API. Phylink deals with the unsupported interface cases before mt7530_setup_port6() is run. Therefore, the default case would never run. However, it must be defined nonetheless to handle all the remaining enumeration values, the phy-modes. Switch to if statement for RGMII and return which simplifies the code and saves an indent. Do not set P6_INTF_MODE, which is the the three least significant bits of the MT7530_P6ECR register, to 0 for RGMII as it will already be 0 after reset. Read XTAL after checking for RGMII as it's only needed for the TRGMII interface mode. Change mt7530_setup_port6() to void now that there're no error cases left. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 100 ++++++++++++++++----------------------- 1 file changed, 40 insertions(+), 60 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 2608b09d3295..f36f240231b5 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -414,72 +414,56 @@ mt753x_preferred_default_local_cpu_port(struct dsa_sw= itch *ds) } =20 /* Setup port 6 interface mode and TRGMII TX circuit */ -static int +static void mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - u32 ncpo1, ssc_delta, trgint, xtal; + u32 ncpo1, ssc_delta, xtal; =20 mt7530_clear(priv, MT7530_MHWTRAP, MHWTRAP_P6_DIS); =20 + if (interface =3D=3D PHY_INTERFACE_MODE_RGMII) + return; + + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, P6_INTF_MODE(1)); + xtal =3D mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; =20 - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - trgint =3D 0; - break; - case PHY_INTERFACE_MODE_TRGMII: - trgint =3D 1; + if (xtal =3D=3D HWTRAP_XTAL_25MHZ) + ssc_delta =3D 0x57; + else + ssc_delta =3D 0x87; + + if (priv->id =3D=3D ID_MT7621) { + /* PLL frequency: 125MHz: 1.0GBit */ + if (xtal =3D=3D HWTRAP_XTAL_40MHZ) + ncpo1 =3D 0x0640; if (xtal =3D=3D HWTRAP_XTAL_25MHZ) - ssc_delta =3D 0x57; - else - ssc_delta =3D 0x87; - if (priv->id =3D=3D ID_MT7621) { - /* PLL frequency: 125MHz: 1.0GBit */ - if (xtal =3D=3D HWTRAP_XTAL_40MHZ) - ncpo1 =3D 0x0640; - if (xtal =3D=3D HWTRAP_XTAL_25MHZ) - ncpo1 =3D 0x0a00; - } else { /* PLL frequency: 250MHz: 2.0Gbit */ - if (xtal =3D=3D HWTRAP_XTAL_40MHZ) - ncpo1 =3D 0x0c80; - if (xtal =3D=3D HWTRAP_XTAL_25MHZ) - ncpo1 =3D 0x1400; - } - break; - default: - dev_err(priv->dev, "xMII interface %d not supported\n", - interface); - return -EINVAL; + ncpo1 =3D 0x0a00; + } else { /* PLL frequency: 250MHz: 2.0Gbit */ + if (xtal =3D=3D HWTRAP_XTAL_40MHZ) + ncpo1 =3D 0x0c80; + if (xtal =3D=3D HWTRAP_XTAL_25MHZ) + ncpo1 =3D 0x1400; } =20 - mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, - P6_INTF_MODE(trgint)); - - if (trgint) { - /* Disable the MT7530 TRGMII clocks */ - core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); - - /* Setup the MT7530 TRGMII Tx Clock */ - core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); - core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); - core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); - core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); - core_write(priv, CORE_PLL_GROUP4, - RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | - RG_SYSPLL_BIAS_LPF_EN); - core_write(priv, CORE_PLL_GROUP2, - RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | - RG_SYSPLL_POSDIV(1)); - core_write(priv, CORE_PLL_GROUP7, - RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | - RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); + /* Disable the MT7530 TRGMII clocks */ + core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); =20 - /* Enable the MT7530 TRGMII clocks */ - core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); - } + /* Setup the MT7530 TRGMII Tx Clock */ + core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); + core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); + core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); + core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); + core_write(priv, CORE_PLL_GROUP4, RG_SYSPLL_DDSFBK_EN | + RG_SYSPLL_BIAS_EN | RG_SYSPLL_BIAS_LPF_EN); + core_write(priv, CORE_PLL_GROUP2, RG_SYSPLL_EN_NORMAL | + RG_SYSPLL_VODEN | RG_SYSPLL_POSDIV(1)); + core_write(priv, CORE_PLL_GROUP7, RG_LCDDS_PCW_NCPO_CHG | + RG_LCCDS_C(3) | RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); =20 - return 0; + /* Enable the MT7530 TRGMII clocks */ + core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); } =20 static void @@ -2597,15 +2581,11 @@ mt7530_mac_config(struct dsa_switch *ds, int port, = unsigned int mode, phy_interface_t interface) { struct mt7530_priv *priv =3D ds->priv; - int ret; =20 - if (port =3D=3D 5) { + if (port =3D=3D 5) mt7530_setup_port5(priv->ds, interface); - } else if (port =3D=3D 6) { - ret =3D mt7530_setup_port6(priv->ds, interface); - if (ret) - return ret; - } + else if (port =3D=3D 6) + mt7530_setup_port6(priv->ds, interface); =20 return 0; } --=20 2.40.1