From nobody Fri Sep 20 11:59:09 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3C58C5ACB3 for ; Sat, 18 Nov 2023 13:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229744AbjKRNOt (ORCPT ); Sat, 18 Nov 2023 08:14:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229731AbjKRNOs (ORCPT ); Sat, 18 Nov 2023 08:14:48 -0500 Received: from relay7-d.mail.gandi.net (relay7-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::227]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2A920D47; Sat, 18 Nov 2023 05:14:43 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 1474B20002; Sat, 18 Nov 2023 13:14:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700313282; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S3MEYC7gqOMpfZ2Sz1eq2IzjVR1wvtK+PgC+zCdTF1s=; b=SD0WaCM256ys8s8rdqlsCKTRgDW5r4oP7kAF4v8vnFA7OdoXbe+ebcUTtnIGkvJ3Tzqy9H CCP6zlQu7MHZGBJ0EFgOyRPnlJswtwj2ripKseEEzOIzuVi6VBVxzcGz0nh9AhpjBXlUtn V3ZtU4KMuWfSnkPUIUq5AsySqo+rBJPR7lNlk9y4wPvF/sZ8yyGaDXWQ6M/zkyUO4+OdSe 6MPcz3us6drJ6mARadUTrdW2dmHz2VJ3xb79ozZf8MZ3eUrKlXeCMbtg9iNG6gTj25jtFs TtYqOt0VmA2OSj0uVyzOCCGeOjNlBkOCGE8gPb2W2ZCyzZNPJRyONjYArsMeJg== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 12/15] net: dsa: mt7530: move enabling port 6 to mt7530_setup_port6() Date: Sat, 18 Nov 2023 16:13:14 +0300 Message-Id: <20231118131317.295591-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enable port 6 only when port 6 is being used. Update the comment on mt7530_setup() with a better explanation. Do not set MHWTRAP_MANUAL on mt7530_setup_port5() as it's already done on mt7530_setup() beforehand. Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 167b340350b3..2608b09d3295 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -420,6 +420,8 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface= _t interface) struct mt7530_priv *priv =3D ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; =20 + mt7530_clear(priv, MT7530_MHWTRAP, MHWTRAP_P6_DIS); + xtal =3D mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; =20 switch (interface) { @@ -910,7 +912,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, p= hy_interface_t interface) =20 val =3D mt7530_read(priv, MT7530_MHWTRAP); =20 - val |=3D MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; + val |=3D MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; val &=3D ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; =20 switch (priv->p5_intf_sel) { @@ -2250,9 +2252,11 @@ mt7530_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_MASK, RD_TAP(16)); =20 - /* Enable port 6 */ + /* Directly access the PHY registers via C_MDC/C_MDIO. The bit that + * enables modifying the hardware trap must be set for this. + */ val =3D mt7530_read(priv, MT7530_MHWTRAP); - val &=3D ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; + val &=3D ~MHWTRAP_PHY_ACCESS; val |=3D MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); =20 --=20 2.40.1