From nobody Fri Sep 20 10:31:03 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAADDC5ACB3 for ; Sat, 18 Nov 2023 12:33:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229699AbjKRMdG (ORCPT ); Sat, 18 Nov 2023 07:33:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229662AbjKRMdF (ORCPT ); Sat, 18 Nov 2023 07:33:05 -0500 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [IPv6:2001:4b98:dc4:8::224]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56D72D61; Sat, 18 Nov 2023 04:33:01 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 7534EE0004; Sat, 18 Nov 2023 12:32:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arinc9.com; s=gm1; t=1700310779; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=t0oGbCGDDoO0IuxC5hzh9krVhy5dPwQKpeDyRtL3LFM=; b=AtETbQCz70fJDRVZ2q+zWVB+dSJ+JHeLm1UsgRxF9HlTc7F5gvH9h1UDjRJ6uyuiSAZIUs aoHcPLB0ytsh4nmUwDq3xxZeaDqkmMF2FHc6ZR6B1tCLrQ6/V8h9zbf3srYBAtJFz6eRzX ylDCXCGl0yjCZdzXA7zQrdCdduYFhLXuzmh1upRn0fLh+5mTYytengW9soUlDwhsiHPSlY rQnBHBrWs2RWB8MDflsRBmv1nl7GRvJkeE5vS3xmOAizMCahD5JzE3rhqVRKko6bYWlnNj D2Pl27NSoKudNHpq/GB9f83h+lYdHZrBGx2sPdxfhxNdiQxWg9BthUxXWpIXGg== From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= To: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= , Daniel Golle , Landen Chao , DENG Qingfang , Sean Wang , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Frank Wunderlich , Bartel Eerdekens , mithat.guner@xeront.com, erkin.bozoglu@xeront.com Subject: [PATCH net-next 01/15] net: dsa: mt7530: always trap frames to active CPU port on MT7530 Date: Sat, 18 Nov 2023 15:31:51 +0300 Message-Id: <20231118123205.266819-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231118123205.266819-1-arinc.unal@arinc9.com> References: <20231118123205.266819-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-GND-Sasl: arinc.unal@arinc9.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On the MT7530 switch, the CPU_PORT field indicates which CPU port to trap frames to, regardless of the affinity of the inbound user port. When multiple CPU ports are in use, if the DSA conduit interface is down, trapped frames won't be passed to the conduit interface. To make trapping frames work including this case, implement ds->ops->master_state_change() on this subdriver and set the CPU_PORT field to the numerically smallest CPU port which the DSA conduit interface its affine to is up. Introduce the active_cpu_ports field to store the information of the active CPU ports. Correct the macros, CPU_PORT is bits 4 through 6 of the register. Add a comment to explain frame trapping for this switch. Currently, the driver doesn't support the use of multiple CPU ports so this is not necessarily a bug fix. Suggested-by: Vladimir Oltean Suggested-by: Russell King (Oracle) Signed-off-by: Ar=C4=B1n=C3=A7 =C3=9CNAL --- drivers/net/dsa/mt7530.c | 30 ++++++++++++++++++++++++++---- drivers/net/dsa/mt7530.h | 6 ++++-- 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index d27c6b70a2f6..442492d62670 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -1035,10 +1035,6 @@ mt753x_cpu_port_enable(struct dsa_switch *ds, int po= rt) mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); =20 - /* Set CPU port number */ - if (priv->id =3D=3D ID_MT7530 || priv->id =3D=3D ID_MT7621) - mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); - /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that * is affine to the inbound user port. @@ -3075,6 +3071,31 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds,= int port, return 0; } =20 +static void +mt753x_conduit_state_change(struct dsa_switch *ds, + const struct net_device *conduit, + bool operational) +{ + struct mt7530_priv *priv =3D ds->priv; + struct dsa_port *cpu_dp =3D conduit->dsa_ptr; + + /* Set the CPU port to trap frames to for MT7530. Trapped frames will be + * forwarded to the numerically smallest CPU port which the DSA conduit + * interface its affine to is up. + */ + if (priv->id !=3D ID_MT7530 && priv->id !=3D ID_MT7621) + return; + + if (operational) + priv->active_cpu_ports |=3D BIT(cpu_dp->index); + else + priv->active_cpu_ports &=3D ~BIT(cpu_dp->index); + + if (priv->active_cpu_ports) + mt7530_rmw(priv, MT7530_MFC, CPU_EN | CPU_PORT_MASK, CPU_EN | + CPU_PORT(__ffs(priv->active_cpu_ports))); +} + static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interfa= ce) { return 0; @@ -3130,6 +3151,7 @@ const struct dsa_switch_ops mt7530_switch_ops =3D { .phylink_mac_link_up =3D mt753x_phylink_mac_link_up, .get_mac_eee =3D mt753x_get_mac_eee, .set_mac_eee =3D mt753x_set_mac_eee, + .conduit_state_change =3D mt753x_conduit_state_change, }; EXPORT_SYMBOL_GPL(mt7530_switch_ops); =20 diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 17e42d30fff4..96d610f5bcf9 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -41,8 +41,8 @@ enum mt753x_id { #define UNU_FFP(x) (((x) & 0xff) << 8) #define UNU_FFP_MASK UNU_FFP(~0) #define CPU_EN BIT(7) -#define CPU_PORT(x) ((x) << 4) -#define CPU_MASK (0xf << 4) +#define CPU_PORT_MASK GENMASK(6, 4) +#define CPU_PORT(x) FIELD_PREP(CPU_PORT_MASK, x) #define MIRROR_EN BIT(3) #define MIRROR_PORT(x) ((x) & 0x7) #define MIRROR_MASK 0x7 @@ -760,6 +760,7 @@ struct mt753x_info { * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN * @create_sgmii: Pointer to function creating SGMII PCS instance(s) + * @active_cpu_ports: Holding the active CPU ports */ struct mt7530_priv { struct device *dev; @@ -786,6 +787,7 @@ struct mt7530_priv { struct irq_domain *irq_domain; u32 irq_enable; int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + unsigned long active_cpu_ports; }; =20 struct mt7530_hw_vlan_entry { --=20 2.40.1