From nobody Tue Dec 30 09:49:36 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F98EC197A0 for ; Fri, 17 Nov 2023 12:59:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346041AbjKQM7t (ORCPT ); Fri, 17 Nov 2023 07:59:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231345AbjKQM7k (ORCPT ); Fri, 17 Nov 2023 07:59:40 -0500 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 741BDD4E for ; Fri, 17 Nov 2023 04:59:36 -0800 (PST) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2c83d37a492so24072831fa.3 for ; Fri, 17 Nov 2023 04:59:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1700225975; x=1700830775; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z0+vsbx15h8F7iZEWw3YAZV40GdDwQ9Lrg1zkM7+uXE=; b=f1vbLFKbCxf1qaLMeJ9Et6yioqpJyOc3Pv4oaLZe2GJCrw6YjgexKqCEdg7T8rzaky RRPRpVJxdGKp/1X3K/zmEnJSlWFpppPVHtfbtkdDqZ9jjh5X/BEQIzEyuIZTLVrbfuK+ mn57Lo+RBEhFHs6yfnGQ+z9CZENL5BUgrTFyTtcTTYuwKsqwvX03uIcISPKJogruIusd FVUnPUNmXc428qm3Q0F1NLAJPu4lux017ZmdGmMb0aRua5kUK0fBTZm0tG9ujNqz/oXD xSEBUgUhVHRi/4iksBLi5v90qORKfzoM5rbsUL0/C0uLBfpJvI27yVy/wYxnxCvMZU1J 0ltA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700225975; x=1700830775; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z0+vsbx15h8F7iZEWw3YAZV40GdDwQ9Lrg1zkM7+uXE=; b=n+Z7Cwf/zhYOoolef/Pa7VC9SPCdQxkklU6NKEIrgHdpMOUADxpQOJ7tO2/NDzIFX3 jrOBA8QTXKfIr8rY7j3KaCgZJoUNigrBC8zD2xqebDM3E/0EBi1bAKWfTI2fOXU9yAQW mIqpguQ3vqxc1NSjn3iA1O0NDklZEPVNck2BXK2wPFC1UoKNUtYhHPXEiwFpqkAosSsK 1xG2lH24hCstSrhzxvKsO0ljRxcTkvmLz18Q7asG/txPj072jiBGKftJsQGoNa9+l02X yQTNnx0oDHrYtMZR1jSazqv3z+O/wmCW+uMgEA4eNZ3j0xwSFh/gP456okwDDZ/RhQy4 ihjg== X-Gm-Message-State: AOJu0YxPdcsrs7Pj9vZEd7AawV+mG3JSryh8egBUDi8ss3yEPMx0V+Q6 tZx9abAW5ICVuphIPKkT+SB9pw== X-Google-Smtp-Source: AGHT+IGJ93FYlL+cy3KwwRdf3ox5rL+XG565HjiI5mzfzk1o0QIlpVLsJKpJC3axOkG6BvOv/0BAbA== X-Received: by 2002:a2e:a4dc:0:b0:2c6:f768:fbd4 with SMTP id p28-20020a2ea4dc000000b002c6f768fbd4mr7335289ljm.53.1700225974606; Fri, 17 Nov 2023 04:59:34 -0800 (PST) Received: from toaster.lan ([2a01:e0a:3c5:5fb1:8196:e423:38cb:9a09]) by smtp.googlemail.com with ESMTPSA id k21-20020a05600c1c9500b0040a487758dcsm2671343wms.6.2023.11.17.04.59.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 04:59:34 -0800 (PST) From: Jerome Brunet To: Thierry Reding , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Jerome Brunet , Kevin Hilman , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-pwm@vger.kernel.org, JunYi Zhao Subject: [PATCH v2 3/6] pwm: meson: prepare addition of new compatible types Date: Fri, 17 Nov 2023 13:59:13 +0100 Message-ID: <20231117125919.1696980-4-jbrunet@baylibre.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231117125919.1696980-1-jbrunet@baylibre.com> References: <20231117125919.1696980-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Clean the amlogic pwm driver to prepare the addition of new pwm compatibles * Generalize 4 inputs clock per channel. AO pwm may just get 2 extra NULL entries which actually better describes the reality of the HW. * Use driver data to carry the device data and remove pwm_chip from it * Stop carrying the internal clock elements with the device data. These are not needed past init. Signed-off-by: Jerome Brunet --- drivers/pwm/pwm-meson.c | 150 +++++++++++++++++++++++----------------- 1 file changed, 87 insertions(+), 63 deletions(-) diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c index 5bea53243ed2..5cbd65cae28a 100644 --- a/drivers/pwm/pwm-meson.c +++ b/drivers/pwm/pwm-meson.c @@ -60,7 +60,7 @@ #define MISC_A_EN BIT(0) =20 #define MESON_NUM_PWMS 2 -#define MESON_MAX_MUX_PARENTS 4 +#define MESON_NUM_MUX_PARENTS 4 =20 static struct meson_pwm_channel_data { u8 reg_offset; @@ -90,19 +90,14 @@ struct meson_pwm_channel { unsigned int hi; unsigned int lo; =20 - struct clk_mux mux; - struct clk_divider div; - struct clk_gate gate; struct clk *clk; }; =20 struct meson_pwm_data { const char * const *parent_names; - unsigned int num_parents; }; =20 struct meson_pwm { - struct pwm_chip chip; const struct meson_pwm_data *data; struct meson_pwm_channel channels[MESON_NUM_PWMS]; void __iomem *base; @@ -115,7 +110,7 @@ struct meson_pwm { =20 static inline struct meson_pwm *to_meson_pwm(struct pwm_chip *chip) { - return container_of(chip, struct meson_pwm, chip); + return dev_get_drvdata(chip->dev); } =20 static int meson_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) @@ -147,6 +142,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, stru= ct pwm_device *pwm, const struct pwm_state *state) { struct meson_pwm_channel *channel =3D &meson->channels[pwm->hwpwm]; + struct device *dev =3D pwm->chip->dev; unsigned int cnt, duty_cnt; unsigned long fin_freq; u64 duty, period, freq; @@ -169,19 +165,19 @@ static int meson_pwm_calc(struct meson_pwm *meson, st= ruct pwm_device *pwm, =20 fin_freq =3D clk_round_rate(channel->clk, freq); if (fin_freq =3D=3D 0) { - dev_err(meson->chip.dev, "invalid source clock frequency\n"); + dev_err(dev, "invalid source clock frequency\n"); return -EINVAL; } =20 - dev_dbg(meson->chip.dev, "fin_freq: %lu Hz\n", fin_freq); + dev_dbg(dev, "fin_freq: %lu Hz\n", fin_freq); =20 cnt =3D div_u64(fin_freq * period, NSEC_PER_SEC); if (cnt > 0xffff) { - dev_err(meson->chip.dev, "unable to get period cnt\n"); + dev_err(dev, "unable to get period cnt\n"); return -EINVAL; } =20 - dev_dbg(meson->chip.dev, "period=3D%llu cnt=3D%u\n", period, cnt); + dev_dbg(dev, "period=3D%llu cnt=3D%u\n", period, cnt); =20 if (duty =3D=3D period) { channel->hi =3D cnt; @@ -192,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson, stru= ct pwm_device *pwm, } else { duty_cnt =3D div_u64(fin_freq * duty, NSEC_PER_SEC); =20 - dev_dbg(meson->chip.dev, "duty=3D%llu duty_cnt=3D%u\n", duty, duty_cnt); + dev_dbg(dev, "duty=3D%llu duty_cnt=3D%u\n", duty, duty_cnt); =20 channel->hi =3D duty_cnt; channel->lo =3D cnt - duty_cnt; @@ -215,7 +211,7 @@ static void meson_pwm_enable(struct meson_pwm *meson, s= truct pwm_device *pwm) =20 err =3D clk_set_rate(channel->clk, channel->rate); if (err) - dev_err(meson->chip.dev, "setting clock rate failed\n"); + dev_err(pwm->chip->dev, "setting clock rate failed\n"); =20 spin_lock_irqsave(&meson->lock, flags); =20 @@ -343,7 +339,6 @@ static const char * const pwm_meson8b_parent_names[] = =3D { =20 static const struct meson_pwm_data pwm_meson8b_data =3D { .parent_names =3D pwm_meson8b_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_meson8b_parent_names), }; =20 /* @@ -351,12 +346,11 @@ static const struct meson_pwm_data pwm_meson8b_data = =3D { * The last 2 are grounded */ static const char * const pwm_gxbb_ao_parent_names[] =3D { - "xtal", "clk81" + "xtal", "clk81", NULL, NULL, }; =20 static const struct meson_pwm_data pwm_gxbb_ao_data =3D { .parent_names =3D pwm_gxbb_ao_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_gxbb_ao_parent_names), }; =20 static const char * const pwm_axg_ee_parent_names[] =3D { @@ -365,7 +359,6 @@ static const char * const pwm_axg_ee_parent_names[] =3D= { =20 static const struct meson_pwm_data pwm_axg_ee_data =3D { .parent_names =3D pwm_axg_ee_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_axg_ee_parent_names), }; =20 static const char * const pwm_axg_ao_parent_names[] =3D { @@ -374,7 +367,6 @@ static const char * const pwm_axg_ao_parent_names[] =3D= { =20 static const struct meson_pwm_data pwm_axg_ao_data =3D { .parent_names =3D pwm_axg_ao_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_axg_ao_parent_names), }; =20 static const char * const pwm_g12a_ao_ab_parent_names[] =3D { @@ -383,16 +375,14 @@ static const char * const pwm_g12a_ao_ab_parent_names= [] =3D { =20 static const struct meson_pwm_data pwm_g12a_ao_ab_data =3D { .parent_names =3D pwm_g12a_ao_ab_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_g12a_ao_ab_parent_names), }; =20 static const char * const pwm_g12a_ao_cd_parent_names[] =3D { - "xtal", "g12a_ao_clk81", + "xtal", "g12a_ao_clk81", NULL, NULL, }; =20 static const struct meson_pwm_data pwm_g12a_ao_cd_data =3D { .parent_names =3D pwm_g12a_ao_cd_parent_names, - .num_parents =3D ARRAY_SIZE(pwm_g12a_ao_cd_parent_names), }; =20 static const struct of_device_id meson_pwm_matches[] =3D { @@ -432,23 +422,25 @@ static const struct of_device_id meson_pwm_matches[] = =3D { }; MODULE_DEVICE_TABLE(of, meson_pwm_matches); =20 -static int meson_pwm_init_channels(struct meson_pwm *meson) +static int meson_pwm_init_clocks_legacy(struct device *dev, + struct clk_parent_data *mux_parent_data) { - struct clk_parent_data mux_parent_data[MESON_MAX_MUX_PARENTS] =3D {}; - struct device *dev =3D meson->chip.dev; + struct meson_pwm *meson =3D dev_get_drvdata(dev); unsigned int i; char name[255]; int err; =20 - for (i =3D 0; i < meson->data->num_parents; i++) { - mux_parent_data[i].index =3D -1; - mux_parent_data[i].name =3D meson->data->parent_names[i]; - } - - for (i =3D 0; i < meson->chip.npwm; i++) { + for (i =3D 0; i < MESON_NUM_PWMS; i++) { struct meson_pwm_channel *channel =3D &meson->channels[i]; struct clk_parent_data div_parent =3D {}, gate_parent =3D {}; struct clk_init_data init =3D {}; + struct clk_divider *div; + struct clk_gate *gate; + struct clk_mux *mux; + + mux =3D devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); + if (!mux) + return -ENOMEM; =20 snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i); =20 @@ -456,69 +448,76 @@ static int meson_pwm_init_channels(struct meson_pwm *= meson) init.ops =3D &clk_mux_ops; init.flags =3D 0; init.parent_data =3D mux_parent_data; - init.num_parents =3D meson->data->num_parents; - - channel->mux.reg =3D meson->base + REG_MISC_AB; - channel->mux.shift =3D - meson_pwm_per_channel_data[i].clk_sel_shift; - channel->mux.mask =3D MISC_CLK_SEL_MASK; - channel->mux.flags =3D 0; - channel->mux.lock =3D &meson->lock; - channel->mux.table =3D NULL; - channel->mux.hw.init =3D &init; - - err =3D devm_clk_hw_register(dev, &channel->mux.hw); + init.num_parents =3D MESON_NUM_MUX_PARENTS; + + mux->reg =3D meson->base + REG_MISC_AB; + mux->shift =3D meson_pwm_per_channel_data[i].clk_sel_shift; + mux->mask =3D MISC_CLK_SEL_MASK; + mux->flags =3D 0; + mux->lock =3D &meson->lock; + mux->table =3D NULL; + mux->hw.init =3D &init; + + err =3D devm_clk_hw_register(dev, &mux->hw); if (err) { dev_err(dev, "failed to register %s: %d\n", name, err); return err; } =20 + div =3D devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); + if (!div) + return -ENOMEM; + snprintf(name, sizeof(name), "%s#div%u", dev_name(dev), i); =20 init.name =3D name; init.ops =3D &clk_divider_ops; init.flags =3D CLK_SET_RATE_PARENT; div_parent.index =3D -1; - div_parent.hw =3D &channel->mux.hw; + div_parent.hw =3D &mux->hw; init.parent_data =3D &div_parent; init.num_parents =3D 1; =20 - channel->div.reg =3D meson->base + REG_MISC_AB; - channel->div.shift =3D meson_pwm_per_channel_data[i].clk_div_shift; - channel->div.width =3D MISC_CLK_DIV_WIDTH; - channel->div.hw.init =3D &init; - channel->div.flags =3D 0; - channel->div.lock =3D &meson->lock; + div->reg =3D meson->base + REG_MISC_AB; + div->shift =3D meson_pwm_per_channel_data[i].clk_div_shift; + div->width =3D MISC_CLK_DIV_WIDTH; + div->hw.init =3D &init; + div->flags =3D 0; + div->lock =3D &meson->lock; =20 - err =3D devm_clk_hw_register(dev, &channel->div.hw); + err =3D devm_clk_hw_register(dev, &div->hw); if (err) { dev_err(dev, "failed to register %s: %d\n", name, err); return err; } =20 + gate =3D devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL); + if (!gate) + return -ENOMEM; + snprintf(name, sizeof(name), "%s#gate%u", dev_name(dev), i); =20 init.name =3D name; init.ops =3D &clk_gate_ops; init.flags =3D CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED; gate_parent.index =3D -1; - gate_parent.hw =3D &channel->div.hw; + gate_parent.hw =3D &div->hw; init.parent_data =3D &gate_parent; init.num_parents =3D 1; =20 - channel->gate.reg =3D meson->base + REG_MISC_AB; - channel->gate.bit_idx =3D meson_pwm_per_channel_data[i].clk_en_shift; - channel->gate.hw.init =3D &init; - channel->gate.flags =3D 0; - channel->gate.lock =3D &meson->lock; + gate->reg =3D meson->base + REG_MISC_AB; + gate->bit_idx =3D meson_pwm_per_channel_data[i].clk_en_shift; + gate->hw.init =3D &init; + gate->flags =3D 0; + gate->lock =3D &meson->lock; =20 - err =3D devm_clk_hw_register(dev, &channel->gate.hw); + err =3D devm_clk_hw_register(dev, &gate->hw); if (err) { dev_err(dev, "failed to register %s: %d\n", name, err); return err; } =20 - channel->clk =3D devm_clk_hw_get_clk(dev, &channel->gate.hw, NULL); + channel->clk =3D devm_clk_hw_get_clk(dev, &gate->hw, NULL); if (IS_ERR(channel->clk)) { err =3D PTR_ERR(channel->clk); dev_err(dev, "failed to register %s: %d\n", name, err); @@ -529,31 +528,56 @@ static int meson_pwm_init_channels(struct meson_pwm *= meson) return 0; } =20 +static int meson_pwm_init_channels(struct device *dev) +{ + struct clk_parent_data mux_parent_data[MESON_NUM_MUX_PARENTS] =3D {}; + struct meson_pwm *meson =3D dev_get_drvdata(dev); + int i; + + for (i =3D 0; i < MESON_NUM_MUX_PARENTS; i++) { + mux_parent_data[i].index =3D -1; + mux_parent_data[i].name =3D meson->data->parent_names[i]; + } + + return meson_pwm_init_clocks_legacy(dev, mux_parent_data); +} + static int meson_pwm_probe(struct platform_device *pdev) { struct meson_pwm *meson; + struct pwm_chip *chip; int err; =20 + chip =3D devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); + if (!chip) + return -ENOMEM; + meson =3D devm_kzalloc(&pdev->dev, sizeof(*meson), GFP_KERNEL); if (!meson) return -ENOMEM; =20 + platform_set_drvdata(pdev, meson); + meson->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(meson->base)) return PTR_ERR(meson->base); =20 spin_lock_init(&meson->lock); - meson->chip.dev =3D &pdev->dev; - meson->chip.ops =3D &meson_pwm_ops; - meson->chip.npwm =3D MESON_NUM_PWMS; + chip->dev =3D &pdev->dev; + chip->ops =3D &meson_pwm_ops; + chip->npwm =3D MESON_NUM_PWMS; =20 meson->data =3D of_device_get_match_data(&pdev->dev); + if (!meson->data) { + dev_err(&pdev->dev, "failed to match device\n"); + return -ENODEV; + } =20 - err =3D meson_pwm_init_channels(meson); + err =3D meson_pwm_init_channels(&pdev->dev); if (err < 0) return err; =20 - err =3D devm_pwmchip_add(&pdev->dev, &meson->chip); + err =3D devm_pwmchip_add(&pdev->dev, chip); if (err < 0) { dev_err(&pdev->dev, "failed to register PWM chip: %d\n", err); return err; --=20 2.42.0