From nobody Fri Sep 20 11:45:07 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48043C072A2 for ; Fri, 17 Nov 2023 09:42:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345759AbjKQJmp (ORCPT ); Fri, 17 Nov 2023 04:42:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345738AbjKQJml (ORCPT ); Fri, 17 Nov 2023 04:42:41 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEEF3D4E; Fri, 17 Nov 2023 01:42:37 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E54486607391; Fri, 17 Nov 2023 09:42:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1700214156; bh=N42OlgtNsTN3hPgxRyKN1KLxCwyU6QyhLsWFXT5/rjk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BeE7QsE8mOzNICHzweqGtHYpDl3Mo+qrNevUZAS7+otN2WqGaRr56A4IodFQKPQKV lxI4zN341kiFSPYwNJCrgB6v6LfYrFps1IhE1jboetwf98/Mt97HDCjwdPqpHBXNat T0/sMyyigNW1jWSsQaSAyA8SwAGLshmybu3pqCKRNNZoCmxCzVVzWNufcJUkMYygIm I1+Hgjax8ZxQBvH+luaxCxOAayZLltpGFnpcdRAmiJKBp9wesvVr1K5ieDaHHiEGhJ eWGTw9gxM0PnRshD79D2HFPuN/GCjaPpMf0Q26ytkNtL5ptZKP087F0P0FUx/mPoWL SAcU9NEte1wzA== From: AngeloGioacchino Del Regno To: matthias.bgg@gmail.com Cc: krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robh+dt@kernel.org, angelogioacchino.delregno@collabora.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, kernel@collabora.com, wenst@chromium.org Subject: [PATCH v1 02/20] soc: mediatek: mtk-svs: Subtract offset from regs_v2 to avoid conflict Date: Fri, 17 Nov 2023 10:42:10 +0100 Message-ID: <20231117094228.40013-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231117094228.40013-1-angelogioacchino.delregno@collabora.com> References: <20231117094228.40013-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The svs_regs_v2 array of registers was offsetted by 0xc00 because the SVS node was supposed to have the same iostart as the thermal sensors. That's wrong for two reasons: 1. Two different devices cannot have the same iostart in devicetree, as those would technically be the same device otherwise; and 2. SVS and Thermal Sensor (be it LVTS or AUXADC thermal) are not the same IP, and those two do obviously have a different iospace. Even though there already are users of this register array, the only one that declares a devicetree node for SVS is MT8183 - but it never actually worked because the "tzts1" thermal zone missed thermal trips, hence this driver's probe always failed on that SoC. Knowing this - it is safe to say that keeping compatibility with older device trees is pointless, hence simply subtract the 0xc00 offset from the register offset array. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 108 ++++++++++++++++----------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 0f7cfbe5630b..416e9b313c0a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -256,60 +256,60 @@ enum svs_reg_index { }; =20 static const u32 svs_regs_v2[] =3D { - [DESCHAR] =3D 0xc00, - [TEMPCHAR] =3D 0xc04, - [DETCHAR] =3D 0xc08, - [AGECHAR] =3D 0xc0c, - [DCCONFIG] =3D 0xc10, - [AGECONFIG] =3D 0xc14, - [FREQPCT30] =3D 0xc18, - [FREQPCT74] =3D 0xc1c, - [LIMITVALS] =3D 0xc20, - [VBOOT] =3D 0xc24, - [DETWINDOW] =3D 0xc28, - [CONFIG] =3D 0xc2c, - [TSCALCS] =3D 0xc30, - [RUNCONFIG] =3D 0xc34, - [SVSEN] =3D 0xc38, - [INIT2VALS] =3D 0xc3c, - [DCVALUES] =3D 0xc40, - [AGEVALUES] =3D 0xc44, - [VOP30] =3D 0xc48, - [VOP74] =3D 0xc4c, - [TEMP] =3D 0xc50, - [INTSTS] =3D 0xc54, - [INTSTSRAW] =3D 0xc58, - [INTEN] =3D 0xc5c, - [CHKINT] =3D 0xc60, - [CHKSHIFT] =3D 0xc64, - [STATUS] =3D 0xc68, - [VDESIGN30] =3D 0xc6c, - [VDESIGN74] =3D 0xc70, - [DVT30] =3D 0xc74, - [DVT74] =3D 0xc78, - [AGECOUNT] =3D 0xc7c, - [SMSTATE0] =3D 0xc80, - [SMSTATE1] =3D 0xc84, - [CTL0] =3D 0xc88, - [DESDETSEC] =3D 0xce0, - [TEMPAGESEC] =3D 0xce4, - [CTRLSPARE0] =3D 0xcf0, - [CTRLSPARE1] =3D 0xcf4, - [CTRLSPARE2] =3D 0xcf8, - [CTRLSPARE3] =3D 0xcfc, - [CORESEL] =3D 0xf00, - [THERMINTST] =3D 0xf04, - [INTST] =3D 0xf08, - [THSTAGE0ST] =3D 0xf0c, - [THSTAGE1ST] =3D 0xf10, - [THSTAGE2ST] =3D 0xf14, - [THAHBST0] =3D 0xf18, - [THAHBST1] =3D 0xf1c, - [SPARE0] =3D 0xf20, - [SPARE1] =3D 0xf24, - [SPARE2] =3D 0xf28, - [SPARE3] =3D 0xf2c, - [THSLPEVEB] =3D 0xf30, + [DESCHAR] =3D 0x00, + [TEMPCHAR] =3D 0x04, + [DETCHAR] =3D 0x08, + [AGECHAR] =3D 0x0c, + [DCCONFIG] =3D 0x10, + [AGECONFIG] =3D 0x14, + [FREQPCT30] =3D 0x18, + [FREQPCT74] =3D 0x1c, + [LIMITVALS] =3D 0x20, + [VBOOT] =3D 0x24, + [DETWINDOW] =3D 0x28, + [CONFIG] =3D 0x2c, + [TSCALCS] =3D 0x30, + [RUNCONFIG] =3D 0x34, + [SVSEN] =3D 0x38, + [INIT2VALS] =3D 0x3c, + [DCVALUES] =3D 0x40, + [AGEVALUES] =3D 0x44, + [VOP30] =3D 0x48, + [VOP74] =3D 0x4c, + [TEMP] =3D 0x50, + [INTSTS] =3D 0x54, + [INTSTSRAW] =3D 0x58, + [INTEN] =3D 0x5c, + [CHKINT] =3D 0x60, + [CHKSHIFT] =3D 0x64, + [STATUS] =3D 0x68, + [VDESIGN30] =3D 0x6c, + [VDESIGN74] =3D 0x70, + [DVT30] =3D 0x74, + [DVT74] =3D 0x78, + [AGECOUNT] =3D 0x7c, + [SMSTATE0] =3D 0x80, + [SMSTATE1] =3D 0x84, + [CTL0] =3D 0x88, + [DESDETSEC] =3D 0xe0, + [TEMPAGESEC] =3D 0xe4, + [CTRLSPARE0] =3D 0xf0, + [CTRLSPARE1] =3D 0xf4, + [CTRLSPARE2] =3D 0xf8, + [CTRLSPARE3] =3D 0xfc, + [CORESEL] =3D 0x300, + [THERMINTST] =3D 0x304, + [INTST] =3D 0x308, + [THSTAGE0ST] =3D 0x30c, + [THSTAGE1ST] =3D 0x310, + [THSTAGE2ST] =3D 0x314, + [THAHBST0] =3D 0x318, + [THAHBST1] =3D 0x31c, + [SPARE0] =3D 0x320, + [SPARE1] =3D 0x324, + [SPARE2] =3D 0x328, + [SPARE3] =3D 0x32c, + [THSLPEVEB] =3D 0x330, }; =20 /** --=20 2.42.0