From nobody Tue Dec 30 09:36:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 440D1C54FB9 for ; Fri, 17 Nov 2023 21:28:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346356AbjKQV2v (ORCPT ); Fri, 17 Nov 2023 16:28:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57470 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235885AbjKQV2c (ORCPT ); Fri, 17 Nov 2023 16:28:32 -0500 Received: from mail-ot1-x332.google.com (mail-ot1-x332.google.com [IPv6:2607:f8b0:4864:20::332]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7563F1BF7 for ; Fri, 17 Nov 2023 13:28:13 -0800 (PST) Received: by mail-ot1-x332.google.com with SMTP id 46e09a7af769-6ce2fc858feso1375259a34.3 for ; Fri, 17 Nov 2023 13:28:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1700256492; x=1700861292; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AIPzAeBpfFKCf/gy5vzaJ56BSGUsbLFdz2SU2WRo3X0=; b=0zHNfDaX0kqMvQF3VGxGhlPNhN1ze/6hIeuzHNB1dDpxChP42748c5SHLokR4Ieuem hPlhq9pvE1ezma2EgvAbGiuqFwTQrxov9axawoKOPqiuhlgGKTa/lO4plk8loFCtpeLr c9aAvdDA6060J4p2oF4Wy6qdgEjwmJZtUrF76/LbdxUf47IcuTw/lyzvHsp2sCywPDaF vDPg/57YL9COZGQYVCAbE4xynTyU+YvM6l1Uxjrxs1tMmukv3ArzR8MQeaQ/lb+fSINl 0iOnNJn7p38/aLFx9v2ggQ2H2LIsd2vl1c3nXaV5w7RCurBZq127YBtEcBOYxFKyEQTm 326g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700256492; x=1700861292; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AIPzAeBpfFKCf/gy5vzaJ56BSGUsbLFdz2SU2WRo3X0=; b=TF/KjC5R9MgTx5vuWJltgRz8ETht2nfwhszwFFRbjrbdP023D6gT83GhMS3FAmLZTB PWDelxMnAeyj1uZXQUHrA5nFKE8d1gXVr0XH9Dy3oVBpdLa/cQwCPWPcEZdUhjPN84/2 pN5+20GX1zpvgrUCRdbhslm0YhJBe2BARPIRbIlOKK49NGBik4dJRLRSAMaqTCul8eA2 xOGtI/PcM6JcF5dnOWTrMb9IaKiWbd8/RUu91fIherS5gDc0aycHrwDFW8eYj23z3TvD xuFDjsBZ2Q2jB4NydSXTwbK641iwTeQbV9PFOgECwDyRI0ub27qcM/ZkttJIO2DgzMY1 EL/w== X-Gm-Message-State: AOJu0YwTtfOsu683za3sOUIFS3CFVkOywvJziU1AG4jOKq9Ek6tLocfP aYNfCU+ybwH7h8RTJSEJ/CfLqw== X-Google-Smtp-Source: AGHT+IFIIBVAsV+kXtymjmu0UMkaBI6XOoR2jmWzVQU/FDClYBpgbgiDERNrQVZezxkwjW1wgE724A== X-Received: by 2002:a9d:6310:0:b0:6d6:54ce:cad with SMTP id q16-20020a9d6310000000b006d654ce0cadmr434912otk.5.1700256492772; Fri, 17 Nov 2023 13:28:12 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id e2-20020a05683013c200b006d3127234d7sm365677otq.8.2023.11.17.13.28.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 13:28:12 -0800 (PST) From: Charlie Jenkins Date: Fri, 17 Nov 2023 13:28:01 -0800 Subject: [PATCH v11 3/5] riscv: Add checksum header MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231117-optimize_checksum-v11-3-7d9d954fe361@rivosinc.com> References: <20231117-optimize_checksum-v11-0-7d9d954fe361@rivosinc.com> In-Reply-To: <20231117-optimize_checksum-v11-0-7d9d954fe361@rivosinc.com> To: Charlie Jenkins , Palmer Dabbelt , Conor Dooley , Samuel Holland , David Laight , Xiao Wang , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org Cc: Paul Walmsley , Albert Ou , Arnd Bergmann , Conor Dooley X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Provide checksum algorithms that have been designed to leverage riscv instructions such as rotate. In 64-bit, can take advantage of the larger register to avoid some overflow checking. Signed-off-by: Charlie Jenkins Acked-by: Conor Dooley Reviewed-by: Xiao Wang --- arch/riscv/include/asm/checksum.h | 82 +++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 82 insertions(+) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/che= cksum.h new file mode 100644 index 000000000000..2fcf864186e7 --- /dev/null +++ b/arch/riscv/include/asm/checksum.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Checksum routines + * + * Copyright (C) 2023 Rivos Inc. + */ +#ifndef __ASM_RISCV_CHECKSUM_H +#define __ASM_RISCV_CHECKSUM_H + +#include +#include + +#define ip_fast_csum ip_fast_csum + +/* Define riscv versions of functions before importing asm-generic/checksu= m.h */ +#include + +/** + * Quickly compute an IP checksum with the assumption that IPv4 headers wi= ll + * always be in multiples of 32-bits, and have an ihl of at least 5. + * + * @ihl: the number of 32 bit segments and must be greater than or equal t= o 5. + * @iph: assumed to be word aligned given that NET_IP_ALIGN is set to 2 on + * riscv, defining IP headers to be aligned. + */ +static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl) +{ + unsigned long csum =3D 0; + int pos =3D 0; + + do { + csum +=3D ((const unsigned int *)iph)[pos]; + if (IS_ENABLED(CONFIG_32BIT)) + csum +=3D csum < ((const unsigned int *)iph)[pos]; + } while (++pos < ihl); + + /* + * ZBB only saves three instructions on 32-bit and five on 64-bit so not + * worth checking if supported without Alternatives. + */ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) { + unsigned long fold_temp; + + asm_volatile_goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, + RISCV_ISA_EXT_ZBB, 1) + : + : + : + : no_zbb); + + if (IS_ENABLED(CONFIG_32BIT)) { + asm(".option push \n\ + .option arch,+zbb \n\ + not %[fold_temp], %[csum] \n\ + rori %[csum], %[csum], 16 \n\ + sub %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp)); + } else { + asm(".option push \n\ + .option arch,+zbb \n\ + rori %[fold_temp], %[csum], 32 \n\ + add %[csum], %[fold_temp], %[csum] \n\ + srli %[csum], %[csum], 32 \n\ + not %[fold_temp], %[csum] \n\ + roriw %[csum], %[csum], 16 \n\ + subw %[csum], %[fold_temp], %[csum] \n\ + .option pop" + : [csum] "+r" (csum), [fold_temp] "=3D&r" (fold_temp)); + } + return csum >> 16; + } +no_zbb: +#ifndef CONFIG_32BIT + csum +=3D ror64(csum, 32); + csum >>=3D 32; +#endif + return csum_fold((__force __wsum)csum); +} + +#endif /* __ASM_RISCV_CHECKSUM_H */ --=20 2.34.1