From nobody Tue Dec 30 09:36:41 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76132C072A2 for ; Fri, 17 Nov 2023 21:28:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346348AbjKQV2r (ORCPT ); Fri, 17 Nov 2023 16:28:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235884AbjKQV2c (ORCPT ); Fri, 17 Nov 2023 16:28:32 -0500 Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12D0E1BC5 for ; Fri, 17 Nov 2023 13:28:12 -0800 (PST) Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-1f06931e4f7so1374094fac.1 for ; Fri, 17 Nov 2023 13:28:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1700256491; x=1700861291; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+Jfb6hOBzZpUnQKwLCoqR3E0xQBxJXpYyz1BMSpxkFw=; b=czjRIg3v7lsgfHsW+WWanB2XXXjfFifkb1W/CB1Xun8ObXrzB0WTUbWupN0BG+XbJW GffCYvqqYsacP97FRxpUg1RWotohciQ7DsbQp3XQjNBX9XrJMfhvnyB8nNWU+jD5OD9B bbRfHZulk6gAnMdCbBXsr7FuAZZiFIUXGUsShv6BNQ+FQER/ZVdFrlbzPNZUcQMwhPCh WLiknuiR9m6HJ83MdBed2wVoI2LjZYZFVIu1Yso4CpgBKbnjoynkg7daI04icKBrki5+ tUOc1X2/C3AteCjg8u64zu6Gtx2JJGhK18aCMTPuduawVtePOakUSuV2E/QWnvLChcWn iyYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1700256491; x=1700861291; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+Jfb6hOBzZpUnQKwLCoqR3E0xQBxJXpYyz1BMSpxkFw=; b=gkzLk9jU8Mm3bZvtE1/uSReQnKOeC37crgFLVZNL5UeyhLrRJDc2PLiYsAqjaDxPtz 8mbaZZHDY9k1pD7m1++/4XRppWo+nzlBBsS9w4zmPUUyPIceCEjaWfH/5vRuIAgcXCKO E6Nkk5Qo+AdusQOAz9opptbUvDyZNN+uuShC4BGMN7Ur2B8+nccH5+rPzBk0pf2X/Vvv v0E1fQ3t/UIl42OQ58GjybuZlj+AUbpYnKrPRSpC8NtMY2aQg5Y75zUbDkEbRT2oB7Ne LjDIXXAg0wTYp53neTi/G65/0p66N5y/LMoR/qZYh2OmZTjIObO4cDNYHuluVL80x2Rf Nz/g== X-Gm-Message-State: AOJu0Ywx4xZ9sqtBHJKwO47JyG6hqyuriKXKjYnHtOu+rZgRQXF29yo1 KZaUZpUiWusfxDwrKtTCfFQdyA== X-Google-Smtp-Source: AGHT+IHj2Z2pnZ38FwJpnREYBKN+j7xsKbex5lAWS4vYTRD8S4SLoyfV+5pXVCGwm6dxV9XFtThxlg== X-Received: by 2002:a05:6870:f608:b0:1e9:efa9:1199 with SMTP id ek8-20020a056870f60800b001e9efa91199mr585055oab.4.1700256491304; Fri, 17 Nov 2023 13:28:11 -0800 (PST) Received: from charlie.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id e2-20020a05683013c200b006d3127234d7sm365677otq.8.2023.11.17.13.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Nov 2023 13:28:10 -0800 (PST) From: Charlie Jenkins Date: Fri, 17 Nov 2023 13:28:00 -0800 Subject: [PATCH v11 2/5] riscv: Add static key for misaligned accesses MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231117-optimize_checksum-v11-2-7d9d954fe361@rivosinc.com> References: <20231117-optimize_checksum-v11-0-7d9d954fe361@rivosinc.com> In-Reply-To: <20231117-optimize_checksum-v11-0-7d9d954fe361@rivosinc.com> To: Charlie Jenkins , Palmer Dabbelt , Conor Dooley , Samuel Holland , David Laight , Xiao Wang , Evan Green , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org Cc: Paul Walmsley , Albert Ou , Arnd Bergmann X-Mailer: b4 0.12.3 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Support static branches depending on the value of misaligned accesses. This will be used by a later patch in the series. All cpus must be considered "fast" for this static branch to be flipped. Signed-off-by: Charlie Jenkins --- arch/riscv/include/asm/cpufeature.h | 3 +++ arch/riscv/kernel/cpufeature.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index b139796392d0..febd9de4373e 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -7,6 +7,7 @@ #define _ASM_CPUFEATURE_H =20 #include +#include #include =20 /* @@ -32,4 +33,6 @@ extern struct riscv_isainfo hart_isa[NR_CPUS]; =20 int check_unaligned_access(void *unused); =20 +DECLARE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); + #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 40bb854fcb96..8935481d32da 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -665,6 +666,35 @@ static int check_unaligned_access_all_cpus(void) =20 arch_initcall(check_unaligned_access_all_cpus); =20 +DEFINE_STATIC_KEY_FALSE(fast_misaligned_access_speed_key); + +static int set_unaligned_access_static_branches(void) +{ + /* + * This will be called after check_unaligned_access_all_cpus so the + * result of unaligned access speed for all cpus will be available. + */ + + int cpu; + bool fast_misaligned_access_speed =3D true; + + for_each_online_cpu(cpu) { + int this_perf =3D per_cpu(misaligned_access_speed, cpu); + + if (this_perf !=3D RISCV_HWPROBE_MISALIGNED_FAST) { + fast_misaligned_access_speed =3D false; + break; + } + } + + if (fast_misaligned_access_speed) + static_branch_enable(&fast_misaligned_access_speed_key); + + return 0; +} + +arch_initcall_sync(set_unaligned_access_static_branches); + #ifdef CONFIG_RISCV_ALTERNATIVE /* * Alternative patch sites consider 48 bits when determining when to patch --=20 2.34.1