From nobody Tue Dec 30 11:08:21 2025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3167C197A0 for ; Fri, 17 Nov 2023 10:04:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345832AbjKQKES (ORCPT ); Fri, 17 Nov 2023 05:04:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41822 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230383AbjKQKEM (ORCPT ); Fri, 17 Nov 2023 05:04:12 -0500 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 188ECA9; Fri, 17 Nov 2023 02:04:07 -0800 (PST) Received: by mail.gandi.net (Postfix) with ESMTPSA id 2DD6EFF81D; Fri, 17 Nov 2023 10:04:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1700215446; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MG/EpR8bVcQceln2f1UmgAvAjO7ip8LLXAJEWchyMuQ=; b=p3UZahcB5fPC27GIKBJabXO5yGHhpl+kOie0qlM7j1CpkzJyrQcOTgUyIeLo+dxwDCc8LJ wcIFqOwpqlsYXCZyC3le3j3IOn3+s3fBImDVtTnQ41iadU/8lxdtZZg4CnP8Mlg/8xvzIV gm9Ay9vzq98L1n6juEMCyLaOuGAe6XrCsCJ+b3llcTKwoyvmoeFRxxSQOZ/MoT8f3dtPVR 3zv1QPyoW0I/ySSr1IdJsaah5IkVDd5upVx/KnT7jijLnsi5M917oLCG8nefH7qc/R+JBt eWxxxA2FMtg4ejttruB5ZA8bpXRBqe4TgSxsKmm9N6PCNLxgQsvBQ11F6j7Ekw== From: Kory Maincent Date: Fri, 17 Nov 2023 11:03:49 +0100 Subject: [PATCH v6 1/6] dmaengine: dw-edma: Fix the ch_count hdma callback MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20231117-b4-feature_hdma_mainline-v6-1-ebf7aa0e40d7@bootlin.com> References: <20231117-b4-feature_hdma_mainline-v6-0-ebf7aa0e40d7@bootlin.com> In-Reply-To: <20231117-b4-feature_hdma_mainline-v6-0-ebf7aa0e40d7@bootlin.com> To: Manivannan Sadhasivam , Gustavo Pimentel , Serge Semin , Vinod Koul , Cai Huoqing Cc: Thomas Petazzoni , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Herve Codina , Kory Maincent , Manivannan Sadhasivam X-Mailer: b4 0.12.4 X-GND-Sasl: kory.maincent@bootlin.com Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The current check of ch_en enabled to know the maximum number of available hardware channels is wrong as it check the number of ch_en register set but all of them are unset at probe. This register is set at the dw_hdma_v0_core_start function which is run lately before a DMA transfer. The HDMA IP have no way to know the number of hardware channels available like the eDMA IP, then let set it to maximum channels and let the platform set the right number of channels. Fixes: e74c39573d35 ("dmaengine: dw-edma: Add support for native HDMA") Acked-by: Manivannan Sadhasivam Reviewed-by: Serge Semin Signed-off-by: Kory Maincent --- See the following thread mail that talk about this issue: https://lore.kernel.org/lkml/20230607095832.6d6b1a73@kmaincent-XPS-13-7390/ Changes in v2: - Add comment Changes in v3: - Fix comment style. --- drivers/dma/dw-edma/dw-hdma-v0-core.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw= -hdma-v0-core.c index 00b735a0202a..1f4cb7db5475 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -65,18 +65,12 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw) =20 static u16 dw_hdma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir d= ir) { - u32 num_ch =3D 0; - int id; - - for (id =3D 0; id < HDMA_V0_MAX_NR_CH; id++) { - if (GET_CH_32(dw, id, dir, ch_en) & BIT(0)) - num_ch++; - } - - if (num_ch > HDMA_V0_MAX_NR_CH) - num_ch =3D HDMA_V0_MAX_NR_CH; - - return (u16)num_ch; + /* + * The HDMA IP have no way to know the number of hardware channels + * available, we set it to maximum channels and let the platform + * set the right number of channels. + */ + return HDMA_V0_MAX_NR_CH; } =20 static enum dma_status dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan) --=20 2.25.1