From nobody Fri Sep 20 11:44:39 2024 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76A91C197A0 for ; Thu, 16 Nov 2023 11:05:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345056AbjKPLFN (ORCPT ); Thu, 16 Nov 2023 06:05:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345094AbjKPLFH (ORCPT ); Thu, 16 Nov 2023 06:05:07 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 26DFED52; Thu, 16 Nov 2023 03:04:56 -0800 (PST) X-UUID: f702f28e846f11eea33bb35ae8d461a2-20231116 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=SMvtmMFnnkXUvzAdpwW++EfhTeP/2PYazC7aVV/JGD8=; b=NuBZOL92QtJnjS5SDkemT2/H6kX3RQChSrjGd/ZKRKipoW8nbOUTlvJ6Ld+BrxPOMxeSGz70QYkwhx+l86qN8HASoiiizEmsZAfXD1Q5ppx4111hwNPrY9mHuqXlZlI5s2EG+A3pqmlwS4pDwnuZcFYjnknmyym7VKwUd2o5JTw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.33,REQID:995c9c96-ab56-464f-a250-64733334a857,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:364b77b,CLOUDID:c8319bfc-4a48-46e2-b946-12f04f20af8c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: f702f28e846f11eea33bb35ae8d461a2-20231116 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1298931495; Thu, 16 Nov 2023 19:04:51 +0800 Received: from mtkmbs13n2.mediatek.inc (172.21.101.108) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Thu, 16 Nov 2023 19:04:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Thu, 16 Nov 2023 19:04:50 +0800 From: Mark Tseng To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Roger Lu , Kevin Hilman CC: , , , , , Subject: [PATCH v2 1/3] soc: mediatek: svs: Add support for MT8195 SoC Date: Thu, 16 Nov 2023 19:04:45 +0800 Message-ID: <20231116110447.3598-2-chun-jen.tseng@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231116110447.3598-1-chun-jen.tseng@mediatek.com> References: <20231116110447.3598-1-chun-jen.tseng@mediatek.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MT8195 svs gpu uses 2-line high bank and low bank to optimize the voltage of opp table for higher and lower frequency respectively. Signed-off-by: Mark Tseng Reviewed-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-svs.c | 136 +++++++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index f31e3bedff50..317c402e673a 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1792,6 +1792,75 @@ static int svs_get_efuse_data(struct svs_platform *s= vsp, return 0; } =20 +static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + u32 idx, i, ft_pgm, vmin, golden_temp; + int ret; + + for (i =3D 0; i < svsp->efuse_max; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + if (!svsp->efuse[10]) { + dev_notice(svsp->dev, "svs_efuse[10] =3D 0x0?\n"); + return false; + } + + /* Svs efuse parsing */ + ft_pgm =3D svsp->efuse[0] & GENMASK(7, 0); + vmin =3D (svsp->efuse[19] >> 4) & GENMASK(1, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + + if (vmin =3D=3D 0x1) + svsb->vmin =3D 0x1e; + + if (ft_pgm =3D=3D 0) + svsb->volt_flags |=3D SVSB_INIT01_VOLT_IGNORE; + + if (svsb->type =3D=3D SVSB_LOW) { + svsb->mtdes =3D svsp->efuse[10] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[10] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[10] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } else if (svsb->type =3D=3D SVSB_HIGH) { + svsb->mtdes =3D svsp->efuse[9] & GENMASK(7, 0); + svsb->bdes =3D (svsp->efuse[9] >> 16) & GENMASK(7, 0); + svsb->mdes =3D (svsp->efuse[9] >> 24) & GENMASK(7, 0); + svsb->dcbdet =3D (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet =3D (svsp->efuse[8] >> 8) & GENMASK(7, 0); + } + + svsb->vmax +=3D svsb->dvt_fixed; + } + + ret =3D svs_get_efuse_data(svsp, "t-calibration-data", + &svsp->tefuse, &svsp->tefuse_max); + if (ret) + return false; + + for (i =3D 0; i < svsp->tefuse_max; i++) + if (svsp->tefuse[i] !=3D 0) + break; + + if (i =3D=3D svsp->tefuse_max) + golden_temp =3D 50; /* All thermal efuse data are 0 */ + else + golden_temp =3D (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx =3D 0; idx < svsp->bank_max; idx++) { + svsb =3D &svsp->banks[idx]; + svsb->mts =3D 500; + svsb->bts =3D (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -2222,6 +2291,61 @@ static int svs_mt8183_platform_probe(struct svs_plat= form *svsp) return 0; } =20 +static struct svs_bank svs_mt8195_banks[] =3D { + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_LOW, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT, + .mode_support =3D SVSB_MODE_INIT02, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 640000000, + .turn_freq_base =3D 640000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x14, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x1, + .vco =3D 0x18, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0100, + .int_st =3D BIT(0), + .ctl0 =3D 0x00540003, + }, + { + .sw_id =3D SVSB_GPU, + .type =3D SVSB_HIGH, + .set_freq_pct =3D svs_set_bank_freq_pct_v3, + .get_volts =3D svs_get_bank_volts_v3, + .tzone_name =3D "gpu1", + .volt_flags =3D SVSB_REMOVE_DVTFIXED_VOLT | + SVSB_MON_VOLT_IGNORE, + .mode_support =3D SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count =3D MAX_OPP_ENTRIES, + .freq_base =3D 880000000, + .turn_freq_base =3D 640000000, + .volt_step =3D 6250, + .volt_base =3D 400000, + .vmax =3D 0x38, + .vmin =3D 0x14, + .age_config =3D 0x555555, + .dc_config =3D 0x1, + .dvt_fixed =3D 0x6, + .vco =3D 0x18, + .chk_shift =3D 0x87, + .core_sel =3D 0x0fff0101, + .int_st =3D BIT(1), + .ctl0 =3D 0x00540003, + .tzone_htemp =3D 85000, + .tzone_htemp_voffset =3D 0, + .tzone_ltemp =3D 25000, + .tzone_ltemp_voffset =3D 7, + }, +}; + static struct svs_bank svs_mt8192_banks[] =3D { { .sw_id =3D SVSB_GPU, @@ -2441,6 +2565,15 @@ static struct svs_bank svs_mt8183_banks[] =3D { }, }; =20 +static const struct svs_platform_data svs_mt8195_platform_data =3D { + .name =3D "mt8195-svs", + .banks =3D svs_mt8195_banks, + .efuse_parsing =3D svs_mt8195_efuse_parsing, + .probe =3D svs_mt8192_platform_probe, + .regs =3D svs_regs_v2, + .bank_max =3D ARRAY_SIZE(svs_mt8195_banks), +}; + static const struct svs_platform_data svs_mt8192_platform_data =3D { .name =3D "mt8192-svs", .banks =3D svs_mt8192_banks, @@ -2470,6 +2603,9 @@ static const struct svs_platform_data svs_mt8183_plat= form_data =3D { =20 static const struct of_device_id svs_of_match[] =3D { { + .compatible =3D "mediatek,mt8195-svs", + .data =3D &svs_mt8195_platform_data, + }, { .compatible =3D "mediatek,mt8192-svs", .data =3D &svs_mt8192_platform_data, }, { --=20 2.18.0